1
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPsTM) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
CAT5241
Quad Digitally Programmable Potentiometers (DPPTM)
with 64 Taps and 2-wire Interface
FEATURES
s
Four linear-taper digitally programmable
potentiometers
s
64 resistor taps per potentiometer
s
End to end resistance 2.5k
, 10k
, 50k
or 100k
s
Potentiometer control and memory access via
2-wire interface (I
2
C like)
s
Low wiper resistance, typically 80
s
Nonvolatile memory storage for up to four wiper
settings for each potentiometer
s
Automatic recall of saved wiper settings at
power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
20-lead SOIC and TSSOP packages
s
Industrial temperature range
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2011, Rev. J
registers is via a 2-wire serial bus (I
2
C-like). On power-
up, the contents of the first data register (DR0) for each
of the four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
HA
LOGEN FREE
TM
LEAD FREE
R
H0
W0
W2
W3
W1
H1
H2
H3
R
R
R
R
L0
L1
L2
L3
R R
R
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
2-WIRE BUS
INTERFACE
CONTROL
LOGIC
SCL
SDA
A0
A1
A2
A3
R
R
R
R
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CAT
5241
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
SOIC Package (J, W)
TSSOP Package (U, Y)
2
CAT5241
Document No. 2011, Rev. J
PIN DESCRIPTION
Pin
(SOIC)
Name
Function
1
R
W0
Wiper Terminal for Potentiometer 0
2
R
L0
Low Reference Terminal for Potentiometer 0
3
R
H0
High Reference Terminal for Potentiometer 0
4
A0
Device Address, LSB
5
A2
Device Address
6
R
W1
Wiper Terminal for Potentiometer 1
7
R
L1
Low Reference Terminal for Potentiometer 1
8
R
H1
High Reference Terminal for Potentiometer 1
9
SDA
Serial Data Input/Output
10
GND
Ground
11
R
H2
High Reference Terminal for Potentiometer 2
12
R
L2
Low Reference Terminal for Potentiometer 2
13
R
W2
Wiper Terminal for Potentiometer 2
14
SCL
Bus Serial Clock
15
A3
Device Address
16
A1
Device Address
17
R
H3
High Reference Terminal for Potentiometer 3
18
R
L3
Low Reference Terminal for Potentiometer 3
19
R
W3
Wiper Terminal for Potentiometer 3
20
VCC
Supply Voltage
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT5241 serial clock input pin is used to clock
all data transfers into or out of the device.
SDA:
Serial Data
The CAT5241 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
or'd with the other open drain or open collector
outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when ad-
dressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with the
address input in order to initiate communication
with the CAT5241.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to
the terminal connections on a mechanical potenti-
ometer.
R
W
:
Wiper
The four R
W
pins are equivalent to the wiper
terminal of a mechanical potentiometer.
DEVICE OPERATION
The CAT5241 is four resistor arrays integrated with 2-
wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
). R
H
and R
L
are
symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (R
W
) by a
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
3
CAT5241
Document No. 2011, Rev. J
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55
C to +125
C
Storage Temperature ........................ -65
C to +150
C
Voltage on any Pin with
Respect to V
SS
(1)(2)
................ -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Wiper Current .................................................. +12mA
Notes:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device perfor-
mance and reliability.
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(5) n = 0, 1, 2, ..., 63
Recommended Operating Conditions:
V
CC
= +2.5V to +6.0V
Temperature
Min
Max
Industrial
-40
C
85
C
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
R
POT
Potentiometer Resistance (-00
)
100
k
R
POT
Potentiometer Resistance (-50
)
50
k
R
POT
Potentiometer Resistance (-10
)
10
k
R
POT
Potentiometer Resistance (-25
)
2.5
k
Potentiometer Resistance
+20
%
Tolerance
R
POT
Matching
1
%
Power Rating
25
C, each pot
50
mW
I
W
Wiper Current
+6
mA
R
W
Wiper Resistance
I
W
= +3mA @ V
CC
=3V
300
R
W
Wiper Resistance
I
W
= +3mA @ V
CC
= 5V
80
150
V
TERM
Voltage on any R
H
or R
L
Pin
V
SS
= 0V
GND
V
CC
V
V
N
Noise
(1)
TBD
nV/ Hz
Resolution
1.6
%
Absolute Linearity
(2)
R
w(n)(actual)
-R
(n)(expected)
(5)
+1
LSB
(4)
Relative Linearity
(3)
R
w(n+1)
-[R
w(n)+LSB
]
(5)
+0.2
LSB
(4)
TC
RPOT
Temperature Coefficient of R
POT
(1)
+300
ppm/
C
TC
RATIO
Ratiometric Temp. Coefficient
(1)
20
ppm/
C
C
H
/C
L
/C
W
Potentiometer Capacitances
(1)
10/10/25
pF
fc
Frequency Response
R
POT
= 50k
(1)
0.4
MHz
4
CAT5241
Document No. 2011, Rev. J
Symbol
Parameter
Min
Typ
Max
Units
f
SCL
Clock Frequency
400
kHz
T
I
(1)
Noise Suppression Time Constant at SCL, SDA Inputs
50
ns
t
AA
SLC Low to SDA Data Out and ACK Out
0.9
s
t
BUF
(1)
Time the Bus Must be Free Before a New
1.2
s
Transmission Can Start
t
HD:STA
Start Condition Hold Time
0.6
s
t
LOW
Clock Low Period
1.2
s
t
HIGH
Clock High Period
0.6
s
t
SU:STA
Start Condition SetupTime (For a Repeated Start Condition)
0.6
s
t
HD:DAT
Data in Hold Time
0
ns
t
SU:DAT
Data in Setup Time
100
ns
t
R
(1)
SDA and SCL Rise Time
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
0.6
s
t
DH
Data Out Hold Time
50
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAPACITANCE
T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
Conditions
Min
Typ
Max
Units
C
I/O
(1)
Input/Output Capacitance (SDA)
V
I/O
= 0V
8
pF
C
IN
(1)
Input Capacitance (A0, A1, A2, A3, SCL)
V
IN
= 0V
6
pF
POWER UP TIMING
(1)
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current
f
SCL
= 400kHz
1
mA
I
SB
Standby Current (V
CC
= 5.0V)
V
IN
= GND or V
CC;
SDA Open
1
A
I
LI
Input Leakage Current
V
IN
= GND to V
CC
10
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
10
A
V
IL
Input Low Voltage
-1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 1.0
V
V
OL1
Output Low Voltage (V
CC
= 3.0V)
I
OL
= 3 mA
0.4
V
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
5
CAT5241
Document No. 2011, Rev. J
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 1. Bus Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
Figure 2. Write Cycle Timing
START BIT
SDA
STOP BIT
SCL
Figure 3. Start/Stop Timing
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
t
WR
Write Cycle Time
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
N
END
(1)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR
(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH
(1)(2)
Latch-Up
JEDEC Standard 17
100
mA
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