2004 California Micro Devices Corp. All rights reserved.
06/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846 www.calmicro.com
1
PACS1284
IEEE 1284 ECP/EPP Termination Network
Features
Single chip IEEE 1284 parallel port termination
28-pin QSOP package, smallest physical
solution
17 terminating lines in a single package
In-system ESD protection to
8KV, HBM
In-system ESD protection to
4KV per
IEC 61000-4-2
Protects downstream devices to 30V
Lead-free version available
Applications
ECP/EPP Parallel Port termination
PC Peripherals
Notebook and Desktop computers
Engineering Workstations and Servers
Product Description
California Micro Devices' PACS1284 Parallel Port Ter-
mination Network provides a complete integrated solu-
tion for the entire IEEE 1284 interface in a single
QSOP package.
To support the bi-directional transfer data rates of
enhanced high-speed parallel ports, the IEEE 1284
Standard recommends a combined termination/pull-up
filter network between the driver/receiver and the cable
at both ends of the parallel port interface. In addition,
government EMC compatibility requirements impose
strict filtering requirements on the parallel port. The
California Micro Devices PACS1284
addresses all
these requirements by providing a seventeen-line IEEE
1284-compliant network in a thin film integrated circuit.
The device provides a complete parallel port termina-
tion solution for space critical applications by integrat-
ing a total of 60 discrete components. In addition, all
the I/O pins are ESD protected for contact discharges
up to
4KV per the Human Body Model (HBM), with the
output pins having the highest probability of ESD pulse
exposure protected to
8KV (HBM), thereby providing
the necessary robustness for the port's application
environment.
The PACS1284 is manufactured in a 28-pin QSOP
package and is available with optional lead-free finish-
ing.
Electrical Schematic
PACS1284-02:
R1 = 2.2k
R2 = 33
C = 220pF
PACS1284-04:
R1 = 4.7k
R2 = 33
C = 180pF
C
R1
C
R1
C
R3
C
R1
1
2
28
27
C
R1
3
26
R2
C
R1
4
25
R2
C
R1
5
24
R2
C
R1
6
23
R2
C
R1
7
21
R2
22
C
R3
8
C
R1
9
19
R2
20
C
R3
10
C
R1
11
18
R2
C
R3
12
C
R1
13
17
R2
C
R1
14
16
R2
C
R3
15
R3 = 2.2k
R3 = 4.7k
2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846 www.calmicro.com
06/07/04
PACS1284
Ordering Information
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
PIN DESCRIPTIONS
PINS
PIN NAME
DESCRIPTION
1, 2, 27
Cap-filtered;
R1 Pull-up
IEEE 1284 signals which require no series termination; pull-up is R1 value.
8, 10, 12,
15, 28
Cap-filtered;
R3 Pull-up
IEEE 1284 signals which require no series termination; pull-up is R3 value.
3-7,
9,11,
13,14
SuperChip Side
Series-terminated
IEEE 1284 signals on the Super I/O Chip side which require series termination.
16-19,
21,
23-26
Connector Side
Series-terminated
IEEE 1284 signals on the Parallel Port Connector side which require series termination.
20
V
CC
Supply rail for the device
22
GND
Ground reference for the device
PACKAGE / PINOUT DIAGRAM
Note: This drawing is not to scale.
28-pin QSOP
1
2
3
4
5
6
7
8
20
19
18
17
21
22
9
10
24
23
25
26
11
12
27
28
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
CAP-FILTERED; R1 PULL-UP
CAP-FILTERED; R1 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R1 PULL-UP
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
GND
CONNECTOR SIDE SERIES-TERMINATED
V
CC
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
13
14
16
15
CONNECTOR SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
STANDARD VALUES
Product
R1 (
)
R2 (
)
R3 (
)
C (pF)
PACS1284-02
2.2k
33
2.2k
220
PACS1284-04
4.7k
33
4.7k
180
PART NUMBERING INFORMATION
Pins
Package
Standard FInish
Lead-free Finish
Ordering Part
Number
1
Part Marking
Ordering Part
Number
1
Part Marking
28
QSOP
PACS1284-02Q
PACS128402Q
PACS1284-02QR
PACS128402QR
28
QSOP
PACS1284-04Q
PACS128404Q
PACS1284-04QR
PACS128404QR
2004 California Micro Devices Corp. All rights reserved.
06/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
PACS1284
Specifications
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
Note 2: Guaranteed by design.
Note 3: ESD contact discharge between pin 22 (GND) and pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, & 28 (one
at a time, all other I/O pins open),
pin 20=5V; pin 22=GND
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
V
CC
Voltage
6.0
V
Input Voltage Range, no clamping
-6.0 to 6.0
V
Storage Temperature Range
-65 to +150
C
Power Dissipation per Resistor
100
mW
Package Power Dissipation
1.00
W
STANDARD OPERATING CONDITIONS
PARAMETER
RATING
UNITS
V
CC
Voltage
5.0
V
Operating Temperature
0 to +70
C
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TOL
R
Absolute Resistance Tolerance
(R1, R2, R3)
Measured at T
A
=25C
10
%
TOL
C
Absolute Capacitance Tolerance
Measured at 1MHz, 2.5VDC, T
A
=25C
20
%
I
LEAK
Leakage current to GND
Measured at 5.0VDC, T
A
=25C
1
A
V
ESD
Peak Discharge Voltage at any I/O Per MIL-STD-883, Method 3015
(HBM); C
Discharge
=100pF;
R
Discharge
=1.5K
; Notes 2,3
4
kV
V
ESD
In-System ESD Protection
Per MIL-STD-883, Method 3015
(HBM); C
Discharge
=100pF;
R
Discharge
=1.5K
; Notes 2,3
8
kV
V
ESD
In-System ESD Protection
Per IEC 61000-4-2 Level 2;
C
Discharge
=150pF; R
Discharge
=330
;
Notes 2,3
4
kV
V
CL
Clamping voltage under ESD
discharge
ESD applied to connector pin, mea-
sured at corresponding input pin; +8kV
discharge, Human Body Model
Note 2
30
V
2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846 www.calmicro.com
06/07/04
PACS1284
Performance Information
Filter Capacitors
Figure 1
shows typical insertion loss graphs for the
PACS1284, for Data and Strobe signals. The curves
are dependent on the physical location of the filter ele-
ments with respect to the ground and V
CC
terminals of
the device.
These graphs are measured in a 50 Ohm environment.
The signal is introduced at the series resistor input and
the output is measured at the corresponding filter
capacitor.
The three plotted lines in
Figure 1
depict the following
measurements:
Line labeled "A" is measured between pin 14
(input) and pin 16 (output).
Line labeled "B" is measured between pin 3 (input)
and pin 26 (output).
Line labeled "C" is measured between pin 6 (input)
and pin 23 (output).
The "A" graph depicts "worst case" filter performance,
while "C" represents a "best case" situation. Graphs of
all other filter elements will fall between these two. (The
filter insertion loss was measured using a Hewlett
Packard HP8753C Analyzer.)
Figure 1. Typical Filter Insertion Loss for PACS1284 (S
21
in dB, T
A
=25C)
0
-10
-20
-30
-40
-50
S
in dB
A
B
C
12
300
450
(FREQUENCY, MHz)
600
750
900
1050
1200
S
21
2004 California Micro Devices Corp. All rights reserved.
06/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
PACS1284
Application Information
Termination Considerations
The IEEE 1284 specification requires both termination
and EMI filtering on a total of 17 signal lines. Control
and Status lines (8 in total) only require a pull-up resis-
tor and a filter capacitor. The Data lines and Strobe
also require a series termination resistor in addition to
the pull-up resistors and filter capacitors. See
Table 1
,
in conjunction with the schematic diagram on page 1.
Interfacing to IEEE 1284 Connectors
IEEE 1284 defines three interface connectors:
1284 A is a 25-pin DB series connector which is
the de facto PC standard for the host connection.
1284 B is a 36-pin, 0.085 inch centerline connector
used on the peripheral device.
1284 C is a new 36-pin, 0.050 inch centerline con-
nector which can be used for both host and periph-
eral.
Figure 2A
shows a possible hook-up between the
1284-A connector on a PC motherboard and the
PACS1284, illustrating how the pin configuration of the
PACS1284 allows for easy interconnect between the
two. The dotted I/O signals of the PACS1284 will
typically be connected to a Super I/O chip on the
motherboard.
Figure 2B
shows a possible hook-up between the
1284-B connector on a peripheral and the PACS1284.
Figure 2C
shows a possible hook-up between the
1284-C connector and the PACS1284.
Figure 2. Example Connections of IEEE 1284 Connectors with PACS1284
Table 1: IEEE 1284 Termination Requirements
SIGNAL TERMINATION REQUIREMENTS
Signal Name
Series Termination
Data1 - Data8
Yes
Strobe
Yes
Init
Not Required
AutoFeedXT
Not Required
Selectin
Not Required
ACK
Not Required
Busy
Not Required
Paper Empty
Not Required
Select
Not Required
Fault
Not Required
1
14
1
19
1
1
1
1
2
20
= FLOW
THROUGH
SIGNALS
= GND
= V
CC
SUPER 1284
SUPER 1284
SUPER 1284
1284-A Connector
Host
1284-B Connector
Peripheral
1284-C Connector
Host/Peripheral
25
13
36
18
36
18
19
Figure 2A:
Figure 2B:
Figure 2C:
= GND
= V
CC
PACS1284
PACS1284
PACS1284
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