ChipFind - документация

Электронный компонент: PAC121GTL

Скачать:  PDF   ZIP
2000 California Micro Devices Corp. All rights reserved.
7/31/2000
1
PAC560GTL
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
High Performance GTL Termination Network for Socket 370 Processors
Features
24 terminations in a single package
5 chip solution for all 119 GTL terminations
High speed termination network
Center ground pin placement reduces ground
bounce and eases board layout
Very low cross-talk
Saves board space and reduces assembly cost
Application Information
High speed microprocessors demand unique, high
speed bus termination. The PACGTL Termination
Network provides 24 terminations per package and
meets the requirements for high speed terminations.
The termination resistor values are 56 or 120 ohms
each. Five devices provide the necessary terminations
for the 32-bit address bus, 64-bit data bus, and the
control of status signals. Potential board layout solutions
are included in this datasheet.
This termination network provides high performance,
high reliability, and low cost through manufacturing
Applications
High Performance Servers
High Performance Desk Top Systems
Intel CeleronTM and PentiumTM CPUs
C0970500
STANDARD CONFIGURATION
efficiency. The termination resistor elements are
fabricated using state-of-the-art thin film manufacturing.
This integrated solution is silicon-based and has the
same reliability characteristics of today's microprocessor
products. The thin film resistors have very high stability
over temperature, over applied voltage, and over life. In
addition, the QSOP (SSOP) industry standard packag-
ing is easy to handle in manufacturing and yields high
reliability similar to other semiconductor components.
All trademarks are the property of their respective holders. P/Active
is a registered trademark and PACTM is a trademark of California Micro Devices.
N
O
I
T
A
M
R
O
F
N
I
G
N
I
R
E
D
R
O
T
R
A
P
D
R
A
D
N
A
T
S
e
g
a
k
c
a
P
r
e
b
m
u
N
t
r
a
P
g
n
i
r
e
d
r
O
s
n
i
P
e
l
y
t
S
g
n
i
k
r
a
M
t
r
a
P
8
2
P
O
S
Q
L
T
G
0
6
5
C
A
P
8
2
P
O
S
Q
L
T
G
1
2
1
C
A
P
When placing an order please specify desired shipping: Tubes or Tage & Reel.
2000 California Micro Devices Corp. All rights reserved.
7/31/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
PAC560GTL
CALIFORNIA MICRO DEVICES
S
E
U
L
A
V
D
R
A
D
N
A
T
S
)
R
(
r
o
t
s
i
s
e
R
6
5
0
2
1
r
o
)
R
(
e
c
n
a
r
e
l
o
T
e
t
u
l
o
s
b
A
%
5
R
C
T
M
p
p
0
5
1
e
g
n
a
R
e
r
u
t
a
r
e
p
m
e
T
g
n
i
t
a
r
e
p
O
C
0
7
o
t
C
0
)
C
0
7
(
g
n
i
t
a
R
r
e
w
o
P
e
g
a
k
c
a
P
x
a
M
W
1
e
c
n
a
t
s
i
s
e
R
n
o
i
t
a
l
u
s
n
I
m
u
m
i
n
i
M
M
0
0
0
,
0
1
*
k
l
a
t
-
s
s
o
r
C
%
4
(
R
)
e
d
o
C
/
g
n
i
t
a
R
r
e
w
o
P
r
o
t
s
i
s
e
R
6
5
0
6
5
W
m
0
0
1
0
2
1
1
2
1
W
m
0
4
RECOMMENDED LAYOUT FOR SOCKET 370 (OPTION A) FOR CELERONTM
AND MENDOCINOTM CPUs
11-mil track pitch, single layer
Note: This option requires 1 metal layer in board routing for all 119 GTL termination lines.
2000 California Micro Devices Corp. All rights reserved.
7/31/2000
3
PAC560GTL
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
RECOMMENDED LAYOUT FOR SOCKET 370 (OPTION B) FOR CELERONTM
AND MENDOCINOTM CPUs
Note: This option requires 2 metal layers in board routing for all 119 GTL termination lines. Please note that the second layer only uses 6
short traces, minimizing potencial interference with other traces, and also minimizing the number of vias.