DDC112

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DDC112

Dual Current Input 20-Bit

ANALOG-TO-DIGITAL CONVERTER

FEATURES

MONOLITHIC CHARGE MEASUREMENT ADC

DIGITAL FILTER NOISE REDUCTION:
3.2ppm, rms

INTEGRAL LINEARITY:

0.005% Reading

0.5ppm FSR

HIGH PRECISION, TRUE INTEGRATING
FUNCTION

PROGRAMMABLE FULL SCALE

SINGLE SUPPLY

CASCADABLE OUTPUT

APPLICATIONS

DIRECT PHOTOSENSOR DIGITIZATION

CT SCANNER DAS

INFRARED PYROMETER

PRECISION PROCESS CONTROL

LIQUID/GAS CHROMATOGRAPHY

BLOOD ANALYSIS

DESCRIPTION

The DDC112 is a dual input, wide dynamic range,
charge-digitizing analog-to-digital converter (ADC) with
20-bit resolution. Low level current output devices,
such as photosensors, can be directly connected to its
inputs. Charge integration is continuous as each input
uses two integrators; while one is being digitized, the
other is integrating.

For each of its two inputs, the DDC112 combines
current-to-voltage conversion, continuous integration,
programmable full-scale range, A/D conversion, and
digital filtering to achieve a precision, wide dynamic
range digital result. In addition to the internal program-
mable full-scale ranges, external integrating capacitors
allow an additional user-settable full-scale range of up
to 1000pC.

To provide single-supply operation, the internal ADC
utilizes a differential input, with the positive input tied
to V

REF

. When the integration capacitor is reset at the

beginning of each integration cycle, the capacitor
charges to V

REF

. This charge is removed in proportion

to the input current. At the end of the integration cycle,
the remaining voltage is compared to V

REF

The high-speed serial shift register which holds the
result of the last conversion can be configured to allow
multiple DDC112 units to be cascaded, minimizing
interconnections. The DDC112 is available in a SO-28
package and is offered in two performance grades.

Protected by US Patent #5841310

Dual

Switched

Integrator

Dual

Switched

Integrator

Modulator

Digital

Filter

Control

Digital

Input/Output

DVALID
DXMIT
DOUT
DIN

DCLK

RANGE2
RANGE1
RANGE0

TEST

CONV

CLK

CAP1A
CAP1A

CAP1B
CAP1B

CAP2A
CAP2A

CAP2B
CAP2B

IN2

IN1

REF

DGND

AGND

CHANNEL 1

CHANNEL 2

1997 Burr-Brown Corporation

PDS-1421D

Printed in U.S.A. January, 2000

For most current data sheet and other product

information, visit www.burr-brown.com

DDC112

SPECIFICATIONS

At T

= +25

C, AV

= DV

= +5V, DDC112U: T

INT

= 500

s, CLK = 10MHz, DDC112UK: T

INT

= 333.3

s, CLK = 15MHz, V

REF

= +4.096V, continuous mode

operation, and internal integration capacitors, unless otherwise noted.

NOTES: (1) Input is less than 1% of full scale. (2) C

SENSOR

is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range.

(4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which
is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing T

INT

(see text). (9) Data format

is Straight Binary with a small offset (see text). (10) Guaranteed but not tested.

DDC112U

DDC112UK

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ANALOG INPUTS
External, Positive Full-Scale

Range 0

EXT

= 250pF

1000

Internal, Positive Full-Scale

Range 1

47.5

52.5

Range 2

100

105

Range 3

142.5

150

157.5

Range 4

190

200

210

Range 5

237.5

250

262.5

Range 6

285

300

315

Range 7

332.5

350

367.5

Negative Full-Scale Input

0.4% of Positive FS

DYNAMIC CHARACTERISTICS
Conversion Rate

kHz

Integration Time, T

INT

Continuous Mode

500

1,000,000

333.3

Integration Time, T

INT

Non-continuous Mode

System Clock Input (CLK)

MHz

Data Clock (DCLK)

MHz

ACCURACY
Noise, Low Level Current Input

(1)

SENSOR

(2)

= 0pF, Range 5 (250pC)

3.2

ppm of FSR

(3)

, rms

SENSOR

= 25pF, Range 5 (250pC)

3.8

ppm of FSR, rms

SENSOR

= 50pF, Range 5 (250pC)

4.2

6.0

ppm of FSR, rms

Differential Linearity Error

0.005% Reading

0.5ppm

FSR, max

Integral Linearity Error

(4)

0.005% Reading

0.5ppm

FSR, typ

0.025% Reading

1.0ppm

FSR, max

No Missing Codes

Bits

Input Bias Current

= +25

0.1

Range Error

Range 5 (250pC)

% of FSR

Range Error Match

(5)

All Ranges

0.1

0.5

% of FSR

Range Sensitivity to V

REF

= 4.096

0.1V

1:1

Offset Error

Range 5, (250pC)

200

600

ppm of FSR

Offset Error Match

(5)

100

ppm of FSR

DC Bias Voltage

(6)

(Input V

)

0.05

Power Supply Rejection Ratio

200

ppm of FSR/V

Internal Test Signal

Internal Test Accuracy

PERFORMANCE OVER TEMPERATURE
Offset Drift

0.5

(10)

ppm of FSR/

Offset Drift Stability

0.2

0.7

(10)

ppm of FSR/minute

DC Bias Voltage Drift

Applied to Sensor Input

Input Bias Current Drift

+25

C to +45

0.01

(10)

pA/

Input Bias Current

= +75

(10)

Range Drift

(7)

Range 5 (250pC)

(10)

ppm/

Range Drift Match

(5)

Range 5 (250pC)

0.05

ppm/

REFERENCE
Voltage

4.000

4.096

4.200

Input Current

(8)

INT

= 500

150

225

275

DIGITAL INPUT/OUTPUT
Logic Levels

4.0

+ 0.3

0.3

+0.8

= 500

4.5

= 500

0.4

Input Current, I

+10

Data Format

(9)

Straight Binary

POWER SUPPLY REQUIREMENTS
Power Supply Voltage

and DV

4.75

5.25

Supply Current

Analog Current

= +5V

14.8

15.2

Digital Current

= +5V

1.2

1.8

Total Power Dissipation

100

130

TEMPERATURE RANGE
Specified Performance

+85

+70

Storage

+100

DDC112

PIN DESCRIPTIONS

PIN

LABEL

DESCRIPTION

IN1

Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.

AGND

Analog Ground.

CAP1B

External Capacitor for Integrator 1B.

CAP1B

External Capacitor for Integrator 1B.

CAP1A

External Capacitor for Integrator 1A.

CAP1A

External Capacitor for Integrator 1A.

Analog Supply, +5V nominal.

TEST

Test Control Input. When HIGH, a test charge is
applied to the A or B integrators on the next CONV
transition.

CONV

Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH

side A is

integrating, CONV LOW

side B is integrating.

CONV must be synchronized with CLK (see text).

CLK

System Clock Input, 10MHz nominal.

DCLK

Serial Data Clock Input. This input operates the
serial I/O shift register.

DXMIT

Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.

DIN

Serial Digital Input. Used to cascade multiple
DDC112s.

Digital Supply, +5V nominal.

DGND

Digital Ground.

DOUT

Serial Data Output, Hi-Z when DXMIT is HIGH.

DVALID

Data Valid Output. A LOW value indicates valid data
is available in the serial I/O register.

RANGE0

Range Control Input 0 (least significant bit).

RANGE1

Range Control Input 1.

RANGE2

Range Control Input 2 (most significant bit).

AGND

Analog Ground.

REF

External Reference Input, +4.096V nominal.

CAP2A

External Capacitor for Integrator 2A.

CAP2A

External Capacitor for Integrator 2A.

CAP2B

External Capacitor for Integrator 2B.

CAP2B

External Capacitor for Integrator 2B.

AGND

Analog Ground.

IN2

Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.

The information provided herein is believed to be reliable; however, BURR-BROWN
assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be
entirely at the user's own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or
granted to any third party. BURR-BROWN does not authorize or warrant any BURR-
BROWN product for use in life support devices and/or systems.

to DV

....................................................................... 0.3V to +6V

to AGND ..................................................................... 0.3V to +6V

to DGND ..................................................................... 0.3V to +6V

AGND to DGND ...............................................................................

0.3V

REF

Voltage to AGND ............................................ 0.3V to AV

+0.3V

Digital Input Voltage to DGND ................................ 0.3V to DV

+0.3V

Digital Output Voltage to DGND ............................. 0.3V to DV

+0.3V

Package Power Dissipation ............................................. (T

JMAX

Maximum Junction Temperature (T

JMAX

) ...................................... +150

Thermal Resistance,

............................................................. 150

C/W

Lead Temperature (soldering, 10s) ............................................... +300

NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maxi-
mum conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

PIN CONFIGURATION

Top View

IN2

AGND

CAP2B

CAP2A

REF

AGND

RANGE2 (MSB)

RANGE1

RANGE0 (LSB)

DVALID

DOUT

DGND

IN1

AGND

CAP1B

CAP1A

TEST

CONV

CLK

DCLK

DXMIT

DIN

DDC112

PACKAGE/ORDERING INFORMATION

MAXIMUM

SPECIFICATION

PACKAGE

INTEGRAL

TEMPERATURE

DRAWING

ORDERING

TRANSPORT

PRODUCT

LINEARITY ERROR

RANGE

PACKAGE

NUMBER

(1)

MEDIA

DDC112U

0.025% Reading

1.0ppm% FSR

C to +85

SO-28

217

DDC112U

Rails

DDC112U/1K

Tape and Reel

DDC112UK

0.025% Reading

1.0ppm% FSR

C to +70

SO-28

217

DDC112UK

Rails

DDC112UK/1K

Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of "DDC112U/1K" will get a single 1000-piece Tape and Reel.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

DDC112

NOISE vs T

INT

1000

0.1

100

INT

(ms)

Noise (ppm of FSR, rms)

SENSOR

= 50pF

SENSOR

= 0pF

Range 5

TYPICAL PERFORMANCE CURVES

At T

= +25

C, characterization done with Range 5 (250pC), T

INT

= 500

s, V

REF

= +4.096, AV

= DV

= +5V, and CLK = 10MHz, unless otherwise noted.

NOISE vs C

SENSOR

200

800

1000

600

400

SENSOR

(pF)

Noise (ppm of FSR, rms)

Range 7

Range 2

Range 1

Range 0

EXT

= 250pF)

NOISE vs INPUT LEVEL

100

Input Level (% of Full-Scale)

Noise (ppm of FSR, rms)

4.5

3.5

2.5

1.5

0.5

SENSOR

= 50pF

SENSOR

= 0pF

Range 5

NOISE vs TEMPERATURE

Temperature (

Noise (ppm of FSR, rms)

Range 1

Range 2

Range 7

Range 3

SENSOR

= 0pF

RANGE DRIFT vs TEMPERATURE

Temperature (

Range Drift (ppm)

Ranges 1 - 7

(Internal Integration Capacitor)

2000

1500

1000

500

1000

1500

vs TEMPERATURE

Temperature (°C)

(pA)

All Ranges

0.1

0.01

DDC112

THEORY OF OPERATION

The basic operation of the DDC112 is illustrated in Figure 1.
The device contains two identical input channels where each
performs the function of current-to-voltage integration fol-
lowed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma converter via a
four input multiplexer. With the DDC112 in the continuous
integration mode, the output of the integrators from one side
of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D con-
version process is controlled by the system clock, CLK.
With a 10MHz system clock, the integrator combined with
the delta-sigma converter accomplishes a single 20-bit con-
version in approximately 220

s. The results from side A and

side B of each signal input are stored in a serial output shift

The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data
pin (DVALID), a serial data output pin (DOUT), and a serial
data input pin (DIN). The DDC112 contains only one A/D
converter, so the conversion process is interleaved between
the two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on T

INT

, CLK, and DCLK, it

is possible to daisy chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital
outputs in those cases where a large number of converters
are needed.

Dual

Switched

Integrator

Dual

Switched

Integrator

Modulator

Digital

Filter

Control

Digital

Input/Output

DVALID
DXMIT
DOUT
DIN

DCLK

RANGE2

RANGE1

RANGE0

TEST

CONV

CLK

CAP1A

CAP1B

CAP2A

CAP2B
CAP2B

IN2

IN1

REF

DGND

AGND

Input 1

Input 2

IN1, Integrator A

IN1, Integrator B

IN2, Integrator A

IN2, Integrator B

Conversion in Progress

DVALID

IN1B

IN2B

IN1A

Integrate

IN2A

IN1B

IN2B

IN1A

IN2A

FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).

FIGURE 1. DDC112 Block Diagram.

DDC112

DEVICE OPERATION

Basic Integration Cycle

The fundamental topology of the front end of the DDC112
is a classical analog integrator as shown in Figure 3. In this
diagram, only Input 1 is shown. This representation of the
input stage consists of an operational amplifier, a selectable
feedback capacitor network (C

), and several switches that

implement the integration cycle. The timing relationships of
all of the switches shown in Figure 3 are illustrated in Figure
4. Figure 4 is used to conceptualize the operation of the
integrator input stage of the DDC112 and should not be used
as an exact timing tool for design. Block diagrams of the
reset, integrate, converter and wait states of the integrator
section of the DDC112 are shown in Figure 5. This internal
switching network is controlled externally with the convert
command (CONV), range selection pins (RANGE0-
RANGE2), and the system clock (CLK). For the best noise
performance, CONV must be synchronized with the rising
edge of CLK. It is recommended CONV toggle within

10ns of the rising edge of CLK.

The non-inverting inputs of the integrators are internally
referenced to ground. Consequently, the DDC112 analog
ground should be as clean as possible. The range switches,
along with the internal and external capacitors (C

) are

shown in parallel between the inverting input and output of
the operational amplifier. Table I shows the value of the
integration capacitor (C

) for each range. At the beginning

of a conversion, the switches S

A/D

, S

INTA

, S

INTB

, S

REF1

REF2

, and S

RESET

are set (see Figure 4).

At the completion of an A/D conversion, the charge on the
integration capacitor (C

) is reset with S

REF1

and

INPUT RANGE

RANGE2

RANGE1

RANGE0

(pF, typ)

(pC, typ)

External

Up to 1000

12.5 to 250

12.5

0.2 to 50

0.4 to 100

37.5

0.6 to 150

0.8 to 200

62.5

0.1 to 250

1.2 to 300

87.5

1.4 to 350

TABLE I. Range Selection of the DDC112.

FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (C

= 62.5pF) Input Range.

RESET

(see Figures 4 and 5a). This is done during the reset

time. In this manner, the selected capacitor is charged to the
reference voltage, V

REF

. Once the integration capacitor is

charged, S

REF1

, and S

RESET

are switched so that V

REF

is no

longer connected to the amplifier circuit while it waits to
begin integrating (see Figure 5b). With the rising edge on
CONV, S

INTA

closes which begins the integration of Chan-

nel A. This puts the integrator stage into its integrate mode
(see Figure 5c).

Charge from the input signal is collected on the integration
capacitor causing the voltage output of the amplifier to
decrease. A falling edge CONV stops the integration by
switching the input signal from side A to side B (S

INTA

and

INTB

). Prior to the falling edge of CONV, the signal on side

B was converted by the A/D converter and reset during the
time that side A was integrating. With the falling edge of
CONV, side B starts integrating the input signal. Now the
output voltage of side A's operational amplifier is presented
to the input of the

A/D converter (see Figure 5d).

50pF

CAP1A

25pF

12.5pF

REF

RANGE2

RANGE1

RANGE0

To Converter

RESET

REF2

A/D1A

INTA

REF1

INTB

IN1

ESD

Protection

Diode

Input

Current

Integrator A

Integrator B (same as A)

Photodiode

DDC112

Determining the Integration Capacitor (C

) Value

The value of the integrator's feedback capacitor, the integra-
tion period, and the reference voltage determine the positive
full-scale (+FS) value of the DDC112. The approximate
positive full-scale value of the DDC112 is given by the
following equations:

The "0.96" factor allows the front end integraters to reach
full scale without having to completely swing to ground.
The negative full-scale (FS) range is approximately 0.4%
of the positive full-scale range. For example, Range 5 has a
nominal +FS range of 250pC. The FS range is then ap-
proximately 1pC. This relationship holds for external ca-
pacitors as well and is independent of V

REF

(for V

REF

within

the allowable range, see the Specification table).

Integration Capacitors

There are seven different capacitors available on chip for
each side of each channel in the DDC112. These internal
capacitors are trimmed in production to achieve the speci-
fied performance for range error of the DDC112. The range
control pins (RANGE0-RANGE2) change the capacitor
value for all four integrators. Consequently, both inputs and
both sides of each input will always have the same full scale
range unless external capacitors are used.

External integration capacitors may be used instead of the
internal capacitors values by setting RANGE2-RANGE0
= 000. The external capacitor pin connections are sum-
marized in Table II. Usually, all four external capacitors
are equal in value, however, it is possible to have differ-
ing pairs of external capacitors between Input 1 and
Input 2 of the DDC112. Regardless of the selected value
of the capacitor, it is strongly recommended that the
capacitors for sides A and B be the same.

INTEGRATOR

EXTERNAL CAPACITOR PINS

ON THE DDC112

Channel

Side

5 and 6

3 and 4

23 and 24

25 and 26

TABLE II. External Capacitor Connections with Range Con-

figuration of RANGE2-RANGE0 = 000.

Since the range accuracy depends on the characteristics of
the integration capacitor, they must be carefully selected. An
external integration capacitor should have low voltage coef-
ficient, temperature coefficient, memory, and leakage cur-
rent. The optimum selection depends on the requirements of
the specific application. Suitable types include COG ce-
ramic, polycarbonate, polystyrene, and silver mica.

Voltage Reference

The external voltage reference is used to reset the integration
capacitors before an integration cycle begins. It is also used
by the

converter while the converter is measuring the

voltage stored on the integrators after an integration cycle
ends. During this sampling, the external reference must
supply charge needed by the

converter. For an integra-

tion time of 500

s, this charge translates to an average V

REF

current of approximately 150

A. The amount of charge

needed by the

converter is independent of the integration

time, therefore, increasing the integration time lowers the
average current. For example, an integration time of 1000

lowers to average V

REF

current to 75

It is critical that V

REF

be stable during the different modes of

operation shown in Figure 5. The

converter measures the

voltage on the integrator with respect to V

REF

. Since the

integrator's capacitors are initially reset to V

REF

, any droop

in V

REF

from the time the capacitors are reset to the time

when the converter measures the integrator's output will
introduce an offset. It is also important that V

REF

be stable

over longer periods of time as changes in V

REF

correspond

directly to changes in the full-scale range. Finally, V

REF

should introduce as little additional noise as possible.

For reasons mentioned above, it is strongly recommended
that the external reference source be buffered with an
operational amplifier, as shown in Figure 6. In this circuit,
the voltage reference is generated by a 4.096V reference.

FIGURE 6. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DDC112.

0.10

+5V

4.99k

10k

LM404-4.1

0.10

0.1

OPA350

To V

REF

Pin 22 of

the DDC112

INT

REF

INT

REF

=
=

(

)

(

)

( .

)

0 96

DDC112

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Setup Time for Test Mode Enable

100

Setup Time for Test Mode Disable

100

Hold Time for Test Mode Enable

100

From Rising Edge of TEST to the Edge of CONV

5.4

3.6

while Test Mode Enabled

Rising Edge to Rising Edge of TEST

5.4

3.6

A low-pass filter to reduce noise connects it to an opera-
tional amplifier configured as a buffer. This amplifier
should have a unity gain bandwidth greater than 4MHz,
low noise, and input/output common-mode ranges that
support V

REF

. Following the buffer are capacitors placed

close to the DDC112's V

REF

pin. Even though the circuit in

Figure 6 might appear to be unstable due to the large output
capacitors, it works well for most operational amplifiers. It
is NOT recommended that series resistance be placed in the
output lead to improve stability since this can cause droop
in V

REF

which produces large offsets.

FIGURE 8. Timing Diagram of the Test Mode of the DDC112.

TABLE III. Timing for the DDC112 in the Test Mode.

DDC112 Frequency Response

The frequency response of the DDC112 is set by the front end
integrators and is that of a traditional continuous time integra-
tor, as shown in Figure 7. By adjusting T

INT

, the user can

change the 3dB bandwidth and the location of the notches in
the response. The frequency response of the

converter that

follows the front end integrator is of no consequence because
the converter samples a held signal from the integrators. That
is, the input to the

converter is always a DC signal. Since

the output of the front end integrators are sampled, aliasing can
occur. Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will "fold" back down
to lower frequencies.

Test Mode

When TEST is used, pins IN1 and IN2 are grounded and
"packets" of approximately 13pC charge are transferred to
the integration capacitors of both Input 1 and Input 2. This
fixed charge can be transferred to the integration capacitors
either once during an integration cycle or multiple times. In
the case where multiple packets are transferred during one
integration period, the 13pC charge is additive. This mode
can be used in both the continuous and non-continuous
mode timing. The timing diagrams for test mode are shown
in Figure 8. The top three lines in Figure 8 define the timing
when one packet of 13pC is sent to the integration capaci-
tors. The bottom three lines define the timing when multiple
packets are sent to the integration capacitors.

FIGURE 7. Frequency Response of the DDC112.

0.1

INT

100

INT

Frequency

Gain (dB)

Integrate B

Action

CONV

TEST

Action

CONV

TEST

Integrate A

Test Mode Disabled

13pC into B

13pC into A

13pC into B

13pC into A

Test Mode Disabled

Test Mode Enabled

Integrate B

Integrate A

Integrate B

Integrate A

Test Mode Disabled

13pC into B

26pC into A

39pC into B

52pC into A

Test Mode Disabled

Test Mode Enabled

Integrate B

Integrate A

DDC112

TEST and CONV work together to implement this feature.
The test mode is entered when TEST is HIGH prior to a
CONV edge. At that point, a CONV edge triggers the
grounding of the analog inputs and the switching of 13pC
packets of charge onto the integration capacitors. If TEST is
kept HIGH through at least two conversions (i.e., a rise and
fall of CONV), all four integrators will be charged with a
13pC packet. At the end of each conversion, the voltage at
the output of the integrators is digitized as discussed in the
"Continuous Mode" and "Non-Continuous Mode" section
of this data sheet. The test mode is exited when TEST is
LOW and a CONV edge occurs.

Once the test mode is entered as described above, TEST can
cycle as many times as desired. When this is done, additional
13pC packets are added on the rising edge of TEST to the
existing charge on the integrator capacitors. Multiple charge
packets can be added in this way as long as the TEST pin is
not LOW when CONV toggles.

DIGITAL ISSUES

The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data
pin (DVALID), a serial data output pin (DOUT), and a serial
data input pin (DIN). The DDC112 contains only one A/D
converter, so the conversion process is interleaved between
the two inputs (see Figure 2). The integration and conversion
process is fundamentally independent of the data retrieval
process. Consequently, the CLK frequency and DCLK fre-
quencies need not be the same. DIN is used when multiple
converters are cascaded. Cascading or "daisy chaining"
greatly simplifies the interconnection and routing of the
digital outputs in cases where a large number of converters
are needed. Refer to "Cascading Multiple Converters" section
of this data sheet for more detail.

The conversion rate of the DDC112 is set by a combination
of the integration time (determined by the user) and the speed
of the A/D conversion process. The A/D conversion time is
primarily a function of the system clock (CLK) speed. One
A/D conversion cycle encompasses the conversion of two
signals (one from each input of the DDC112) and reset time
for each of the integrators involved in the two conversions. In
most situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC112 will
operate in the continuous mode. When the DDC112 is in the
continuous mode, the sensor output is continuously integrated
by one of the two sides of each input.

In the event that the A/D conversion takes longer than the
integration time, the DDC112 will switch into a non-con-
tinuous mode. In non-continuous mode, the A/D converter is
not able to keep pace with the speed of the integration
process. Consequently, the integration process is periodi-
cally halted until the digitizing process catches up. These
two basic modes of operation for the DDC112--continuous
and non-continuous modes--are described below.

Continuous and Non-Continuous
Operational Modes

The state diagram of the DDC112 is shown in Figure 9. In
all, there are 8 states. Table IV provides a brief explanation
of each of the states.

STATE

MODE

DESCRIPTION

Ncont

Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.

Ncont

Prepare side A for integration.

Cont

Integrate on side A.

Cont

Integrate on side B; m/r/az on side A.

Cont

Integrate on side A; m/r/az on side B.

Cont

Integrate on side B.

Ncont

Prepare side B for integration.

Ncont

Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.

TABLE IV. State Descriptions.

Int A/Meas B

Cont

CONV · mbsy

CONV

Int B/Meas A

Cont

Ncont

Int A
Cont

Ncont

Int B
Cont

CONV

mbsy

FIGURE 9. State Diagram.

Four signals are used to control progression around the state
diagram: CONV and mbsy and their complements. The state
machine uses the level as opposed to the edges of CONV to
control the progression. mbsy is an internally generated
signal not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in progress.

DDC112

TABLE V. Timing Specifications Generalized in CLK Periods.

SYMBOL

DESCRIPTION

VALUE (CLK periods)

Cont mode m/r/az cycle

4794

Cont mode data ready

4212

INT

> 4794)

4212

INT

= 4794)

1st ncont mode data ready

4212

2nd ncont mode data ready

4548

Ncont mode m/r/az cycle

9108

Prepare side for integration

240

Integrate B

Integrate A

Integrate B

m/r/az A

m/r/az B

m/r/az A

CONV

State

mbsy

m/r/az

Status

Integration

Status

DVALID

t = 0

Power-Up

Side A

Data

Side B

Data

Side A

Data

FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).

SYMBOL

DESCRIPTION

VALUE (CLK = 10MHz)

VALUE (CLK = 15MHz)

Cont mode m/r/az cycle

479.4

316.4

Cont mode data ready

421.2

INT

> 479.4

280.5

INT

> 316.4

421.2

0.3

INT

= 479.4

280.5

0.2

INT

= 316.4

During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration.
Consequently, keeping track of the current status of CONV
is all that is needed to know the current state. Cont mode
operation corresponds to states 3-6. Two of the states, 3 and
6, only perform an integration (no m/r/az cycle).

mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integra-
tion. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.

One interesting observation from the state diagram is that
the integrations always alternate between sides A and B.
This relationship holds for any CONV pattern and is inde-
pendent of the mode. States 2 and 7 insure this relationship
during the ncont mode.

When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the begin-
ning state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6 and 4-5. Inverting
CONV results in the states progressing through their sym-
metrical match.

TIMING EXAMPLES

Cont Mode

A few timing diagrams will now be discussed to help
illustrate the operation of the state machine. These are
shown in Figures 10 through 19. Table V gives generalized
timing specifications in units of CLK periods. Values in

for Table V can be easily found for a given CLK. For
example, if CLK = 10MHz, then a CLK period = 0.1

s. t

in Table V would then be 479.4

Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates
the current state in the state diagram. The following two
traces show when integrations and measurement cycles are
underway. The internal signal mbsy is shown next. Finally,
DVALID is given. As described in the data sheet, DVALID
goes active LOW when data is ready to be retrieved from the
DDC112. It stays LOW until DXMIT is taken LOW by the
user. In Figure 10 and the following timing diagrams, it is
assumed that DXMIT it taken LOW soon after DVALID
goes LOW. The text below the DVALID pulse indicates the
side of the data and arrows help match the data to the
corresponding integration. The signals shown in Figures 10
through 19 are drawn at approximately the same scale.

In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first
two states, cont mode operation is reached and the states
begin toggling between 4 and 5. From now on, the input is
being continuously integrated, either by side A or side B.

DDC112

The time needed for the m/r/az cycle, t

, is the same time that

determines the boundary between the cont and ncont modes
described earlier in the Overview section. DVALID goes
LOW after CONV toggles in time t

, indicating that data is

ready to be retrieved. As shown in Figure 10, there are two
values for t

, depending on T

INT

. The reason for this will be

discussed in the Special Considerations section.

Figure 11 shows the result of inverting the logic level of
CONV. The only difference is in the first three states.
Afterwards, the states toggle between 4 and 5 just as in the
previous example. Figure 12 shows the timing diagram of
the internal operations occurring during continuous mode
operation.

FIGURE 11. Continuous Mode Timing (CONV LOW at power-up).

Integrate A

Integrate B

Integrate A

m/r/az B

m/r/az A

m/r/az B

CONV

State

Integration

Status

m/r/az
Status

mbsy

DVALID

t = 0

Power-Up

Side B

Data

Side A

Data

Side B

Data

FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112.

INT

End Integration Side A

Start Integration Side B

Side A

Data Ready

Side B

Data Ready

Side B

Side A

Side B

Side A

End Integration Side B

Start Integration Side A

End Integration Side A

Start Integration Side B

CONV

DVALID

A/D Conversion

Input 1 (Internal)

A/D Conversion

Input 2 (Internal)

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

INT

Integration Period (continuous mode)

500

1,000,000

333

1,000,000

A/D Conversion Time (internally controlled)

202.2

134.66

A/D Conversion Reset Time (internally controlled)

13.2

8.8

Integrator and A/D Conversion Reset Time

61.8

41.2

(internally controlled)

TABLE VI. Timing for the Internal Operation in the Continuous Mode.

DDC112

FIGURE 13. Non-Continuous Mode Timing.

Ncont Mode

Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (i.e., sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being mea-
sured, reset and auto-zeroed. Before the DDC112 can ad-
vance to states 3 or 6, both sides A and B must be finished
with the m/r/az cycle which takes time t

. When the m/r/az

cycles are completed, time t

is needed to prepare the next

side for integration. This time is required for the ncont
mode because the m/r/az cycle of the ncont mode is slightly
different from that of the cont mode. After the first integra-
tion ends, DVALID goes LOW in time t

. This is the same

time as in the cont mode. The second data will be ready in
time t

after the first data is ready. One result of the naming

convention used in this application bulletin is that when the
DDC112 is operating in the "ncont mode", it passes through
both "ncont mode states" and "cont mode states". For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states. "Ncont mode"
by definition means that for some portion of the time,
neither side A nor B is integrating. States that perform an
integration are labeled "cont mode states" while those that
do not are called "ncont mode states". Since integrations are
performed in the ncont mode, just not continuously, some
cont mode states must be used in a ncont mode state pattern.

SYMBOL

DESCRIPTION

VALUE (CLK = 10MHz)

VALUE (CLK = 15MHz)

1st ncont mode data ready

421.2

0.3

280.5

0.2

2nd ncont mode data ready

4548.0

3028.9

Ncont mode m/r/az cycle

910.8

601.1

Prepare side for integration

24.0

Int B

Int A

Int B

Int A

m/r/az B

m/r/az A

m/r/az B

CONV

State

mbsy

m/r/az

Status

Integration

Status

DVALID

Side A

Data

Side B

Data

Side A

Data

Side B

Data

DDC112

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

INT

Integration Time (non-continuous mode)

1,000,000

A/D Conversion Time (internally controlled)

202.2

134.6

A/D Conversion Reset Time (internally controlled)

13.2

8.8

Integrator and A/D Conversion Reset Time

37.8

25.2

(internally controlled)

Total A/D Conversion and Rest Time

910.8

606.6

(internally controlled)

Release Time

FIGURE 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A Integrated First.

INT

Release

State

End Integration Side A
Start Integration Side B

End Integration Side B

Wait State

Side A

Data Ready

Side B

Data Ready

Start Integration Side A

CONV

A/D Conversion

Input 1

A/D Conversion

Input 2

DVALID

INT

CONV

A/D Conversion

Input 1

A/D Conversion

Input 2

DVALID

Release

State

End Integration Side B
Start Integration Side A

End Integration Side A

Wait State

Side B

Data Ready

Side A

Data Ready

Start Integration Side B

FIGURE 15. Internal Operation Timing Diagram of the Non-Continuous Mode with Side B Integrated First.

TABLE VII. Internal Timing for the DDC112 in the Non-Continuous Mode.

DDC112

FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.

FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.

CONV1

CONV2

State

mbsy

CONV

DVALID

State

Integration

Status

mbsy

Int B

Int A

Int B

Side A

Data

Side B

Data

Side A

Data

Int A

Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC112 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does
allow flexibility in generating ncont mode CONV patterns.
For example, the DDC112 Evaluation Fixture operates in
the ncont mode by generating a square wave with pulse
width < t

. Figure 17 illustrates operation in the ncont mode

using a 50% duty cycle CONV signal with T

INT

= 1620

CLK periods. Care must be exercised when using a square
wave to generate CONV. There are certain integration
times that must be avoided since they produce very short
intervals for state 2 (or state 7 if CONV is inverted). As seen
in the state diagram, the state progresses from 2 to 3 as soon
as CONV is HIGH. The state machine does not insure that
the duration of state 2 is long enough to properly prepare the
next side for integration (t

). This must be done by the user

with proper timing of CONV. For example, if CONV is a
square wave with T

INT

= 3042 CLK periods, state 2 will

only be 18 CLK periods long, therefore, t

will not be met.

DDC112

CONV

Non-Continuous

Continuous

State

mbsy

m/r/az
Status

Integration

Status

m/r/az A

m/r/az B

m/r/az A

Int B

Int A

Integrate A

Integrate B

FIGURE 18. Changing from Continuous Mode to Non-Continuous Mode.

FIGURE 19. Changing from Non-Continuous Mode to Continuous Mode.

CONV

Continuous

Non-Continuous

State

Integration

Status

m/r/az

Status

mbsy

m/r/az B

m/r/az A

m/r/az B

m/r/az A

m/r/az B

Integrate A

Integrate B

Int A

Int B

Changing Between Modes

Changing from the cont to ncont mode occurs whenever
T

INT

< t

. Figure 18 shows an example of this transition.

In this figure, the cont mode is entered when the integration
on side A is completed before the m/r/az cycle on side B is
complete. The DDC112 completes the measurement on sides
B and A during states 8 and 7 with the input signal shorted
to ground. Ncont integration begins with state 6.

Changing from the ncont to cont mode occurs when T

INT

increased so that T

INT

is always

(see Figure 14). With a

longer T

INT

, the m/r/az cycle has enough time to finish

before the next integration begins and continuous integra-
tion of the input signal is possible. For the special case of the
very first integration when changing to the cont mode, T

INT

can be < t

. This is allowed because there is no simultaneous

m/r/az cycle on the side B during state 3--there is no need
to wait for it to finish before ending the integration on side A.

DDC112

SPECIAL CONSIDERATIONS

NCONT MODE INTEGRATION TIME

The DDC112 uses a relatively fast clock. For CLK = 10MHz,
this allows T

INT

to be adjusted in steps of 100ns since CONV

should be synchronized to CLK. However, for the internal
measurement, reset and auto-zero operations, a slower clock
is more efficient. The DDC112 divides CLK by six and uses
this slower clock with a period of 600ns to run the m/r/az
cycle and data ready logic.

Because of the divider, it is possible for the integration time
to be a non-integer number of slow clock periods. For
example, if T

INT

= 5000 CLK periods (500

s for CLK = 10MHz),

there will be 833 1/3 slow clocks in an integration period.
This non-integer relationship between T

INT

and the slow

clock period causes the number of rising and falling slow
clock edges within an integration period to change from
integration to integration. The digital coupling of these
edges to the integrators will in turn change from integration
to integration which produces noise. The change in the clock
edges is not random, but will repeat every 3 integrations.
The coupling noise on the integrators appears as a tone with
a frequency equal to the rate at which the coupling repeats.

To avoid this problem in cont mode, the internal slow clock
is shut down after the m/r/az cycle is complete when it is no
longer needed. It starts up again just after the next integra-
tion begins. Since the slow clock is always off when CONV
toggles, the same number of slow clock edges fall within an
integration period regardless of its length. Therefore,
T

INT

4794 CLK periods will not produce the coupling

problem described above.

For the ncont mode however, the slow clock must always be
left running. The m/r/az cycle is not completed before an
integration ends. It is then possible to have digital coupling
to the integrators. The digital coupling noise depends heavily
on the layout of the printed circuit board used for the
DDC112. For solid grounds and power supplies with good
bypassing, it is possible to greatly reduce the coupling.
However, for guaranteeing the best performance in the ncont
mode, the integration time should be chosen to be an integer
multiple of 1/(2f

SLOWCLOCK

). For CLK = 10MHz, the inte-

gration time should be an integer multiple of 300ns--
T

INT

= 100

s is not. A better choice would be T

INT

= 99

DATA READY

The DVALID signal which indicates that data is ready is
generated using the internal slow clock. The phase relation-
ship between this clock and CLK is set when power is first
applied and is random. Since CONV is synchronized with
CLK, it will have a random phase relationship with respect
to the slow clock. When T

INT

> t

, the slow clock will

temporarily shut down as described above. This shutdown
process synchronizes the internal clock with CONV so that
the time between when CONV toggles to when DVALID
goes LOW (t

and t

) is fixed.

For T

INT

, the internal slow clock, is not allowed to shut

down and the synchronization never occurs. Therefore, the
time between CONV toggling and DVALID indicating data
is ready has uncertainty due to the random phase relation-
ship between CONV and the slow clock. This variation is

1/(2f

SLOWCLOCK

) or

3/f

CLK

. The timing to the second

DVALID in the ncont mode will not have a variation since
it is triggered off the first data ready (t

) and both are

derived from the slow clock.

Polling DVALID to determine when data is ready eliminates
any concern about the variation in timing since the readback
is automatically adjusted as needed. If the data readback is
triggered off the toggling of CONV directly (instead of
polling), then waiting the maximum value of t

or t

insures

that data will always be ready before readback occurs.

Data Retrieval

In the continuous and non-continuous modes of operation,
the data from the last conversion is available for retrieval
with the falling edge of DVALID (see Figure 22). The
falling edge of DXMIT in combination with the data clock
(DCLK) will initiate the serial transmission of the data from
the DDC112. Typically, data is retrieved from the DDC112
as soon as DVALID falls and completed before the next
CONV transition from HIGH to LOW or LOW to HIGH
occurs. If this is not the case, care should be taken to stop
activity on DCLK and consequently DOUT by at least 10

around a CONV transition. If this caution is ignored it is
possible that the integration that is being initiated by CONV
will have additional noise introduced.

The serial output data at DOUT is transmitted in Straight
Binary Code per Table VIII. An output offset has been built
into the DDC112 to allow for the measurement of input
signals near and below zero. Board leakage up to

0.4%

of the positive full scale can be tolerated before the digital
output clips to all zeroes.

Cascading Multiple Converters

Multiple DDC112 units can be connected in serial or parallel
configurations, as illustrated in Figures 20 and 21.

DOUT can be used with DIN to "daisy chain" several
DDC112 devices together to minimize wiring. In this mode
of operation, the serial data output is shifted through mul-
tiple DDC112s, as illustrated in Figure 20.

PULLUP

prevents DIN from floating when DXMIT is HIGH.

Care should be taken to keep the capacitive load on DOUT
as low as possible when running CLK=15MHz.

CODE

INPUT SIGNAL

1111 1111 1111 1111 1111

1111 1111 1111 1111 1110

FS 1LSB

0000 0001 0000 0000 0001

+1LSB

0000 0001 0000 0000 0000

Zero

0000 0000 0000 0000 0000

0.4% FS

TABLE VIII. Straight Binary Code Table.

DDC112

FIGURE 20. Daisy-Chained DDC112's.

IN1

IN2

DCLK

DXMIT

DIN

DVALID

DOUT

DDC112

"F" "E"

Sensor "F"

Sensor "E"

IN1

IN2

DCLK

DXMIT

DIN

DVALID

DOUT

DDC112

"D" "C"

Sensor "D"

Sensor "C"

IN1

IN2

DCLK

DXMIT

DIN

DVALID

DOUT

Data Retrieval

Outputs

DDC112

"B" "A"

Sensor "B"

Sensor "A"

Data Retrievel

Inputs

40 Bits

FIGURE 21. DDC112 in Parallel Operation.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Propagation Delay from Rising Edge of CLK to DVALID LOW

Propagation Delay from DXMIT LOW to DVALID HIGH

Setup Time from DCLK LOW TO DXMIT LOW

Propagation Delay from DXMIT LOW to Valid DOUT

Hold Time that DOUT is Valid After Falling Edge of DCLK

Propagation Delay from DXMIT HIGH to DOUT Disabled

22A

(1)

Propagaton Delay from Falling Edge of DCLK to Valid DOUT

22B

(2)

Propagation Delay from Falling Edge of DCLK to Valid DOUT

NOTES: (1) Applies to DDC112UK only, with a maximum load of one DDC112UK DIN (4pF typical) with an additional load of (5pF

100k

). (2)

Applies to

DDC112U only, with a maximum load of one DDC112U DIN (4pF typical) with an additional load of (5pF

100k

FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112.

TABLE IX. Timing for the DDC112 Data Retrieval.

DIN

DOUT

DXMIT

DDC112

Data Output

DDC112

Enable

DOUT

DXMIT

DOUT

DXMIT

Input 2

Bit 1

Input 2

Bit 20

Input 1

Bit 1

Input 1

Bit 20

MSB

LSB

MSB

Output Disabled

Output Enabled

Output Disabled

LSB

CLK

DVALID

DXMIT

DCLK

(1)

DOUT

NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.

DDC112

RETRIEVAL

BEFORE CONV TOGGLES

(CONTINUOUS MODE)

This is the most straightforward method. Data retrieval
begins soon after DVALID goes LO and finishes before
CONV toggles, see Figure 24. For best performance, data
retrieval must stop t

before CONV toggles. This method is

the most appropriate for longer integration times. The maxi-
mum time available for readback is T

INT

For DCLK and CLK = 10MHz, the maximum number of
DDC112s that can be daisy-chained together is:

Where

DCLK

is the period of the data clock. For example, if

TINT = 100

s and DCLK = 10MHz, the maximum number

of DDC112s is:

RETRIEVAL

AFTER CONV TOGGLES

(CONTINUOUS MODE)

For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t

after CONV

toggles before beginning. Figure 25 shows an example of
this. The maximum time available for retrieval is t

(421.2

s 10

s 2

s for CLK = 10MHz), regardless of

TINT. The maximum number of DDC112s that can be
daisy-chained together is:

For DCLK = 10MHz, the maximum number of DDC112s is
102.

FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.

INT

DCLK

431 2

1000

431 2

40 100

142 2

142

112

µ =

DDC

(

)(

)

409 2

DCLK

Output Disabled

Output Enabled

Output Disabled

CLK

DVALID

DXMIT

DCLK

(1)

DIN

Input A

Bit 1

Input E

Bit 20

Input F

Bit 1

Input F

Bit 20

MSB

Output Disabled

Output Enabled

LSB

Output Disabled

MSB

DOUT

NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH.

22A,

22B

TABLE X. Timing for the DDC112 Data Retrieval Using DIN.

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Set-Up Time From DIN to Rising Edge of DCLK

Hold Time For DIN After Rising Edge of DCLK

Hold Time for DXMIT HIGH Before Falling

1.33

Edge of DVALID

DDC112

RETRIEVAL

BEFORE AND AFTER CONV

TOGGLES (CONTINUOUS MODE)

For the absolute maximum time for data retrieval, data can
be retrieved before and after CONV toggles. Nearly all of
T

INT

is available for data retrieval. Figure 26 illustrates how

this is done by combining the two previous methods. You
must pause the retrieval during CONV's toggling to prevent
digital noise, as discussed previously, and finish before the

next data is ready. The maximum number of DDC112s that
can be daisy-chained together is:

For T

INT

= 500

s and DCLK = 10MHz, the maximum

number of DDC112s is 119.

· · ·

DCLK

DXMIT

DVALID

CONV

DOUT

Side B

Data

Side A

Data

INT

FIGURE 26. Readback Before and After CONV Toggles.

INT

DCLK

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Hold Time for DXMIT HIGH Before Falling

1.33

Edge of DVALID

Data Retrieval Shutdown Before Edge of CONV

Data Retrieval Start-Up After Edge of CONV

DDC112

RETRIEVAL: NONCONTINUOUS MODE

Retrieving in noncontinuous mode is slightly different as
compared with the continuous mode. As shown in Figure 27
and described in detail in Application Bulletin AB-131,
DVALID goes LOW in time t

after the first integration

completes. If T

INT

is shorter than this time, all of t

available to retrieve data before the other side's data is
ready. For T

INT

> t

, the first integration's data is ready

before the second integration completes. Data retrieval must
be delayed until the second integration completes leaving
less time available for retrieval. The time available is
t

INT

). The second integration's data must be

retrieved before the next round of integrations begin. This

time is highly dependent on the pattern used to generate
CONV. As with the continuous mode, data retrieval must
halt before and after CONV toggles (t

, t

) and be com-

pleted before new data is ready (t

POWER-UP SEQUENCING

Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed AV

or DV

. The level of CONV at power-

up is used to determine which side (A or B) will be
integrated first. Before integrations can begin though, CONV
must toggle, as shown in Figure 28.

· · ·

INT

Side A

Data

Side B

Data

CONV

DVALID

DXMIT

DCLK

DOUT

FIGURE 27. Readback in Noncontinuous Mode.

FIGURE 28. Timing Diagram at Power-Up of the DDC112.

Integrate Side A

Integrate Side B

Power-Up

Initialization

Release State

Start

Integration

CONV

(HIGH at power-up)

CONV

(LOW at power-up)

Power Supplies

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Power-On Initialization Period

From Release Edge to Integration Start

TABLE XI. Timing for the DDC112 Power-Up Sequence.

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

1st Ncont Mode Data Ready (see AB-131)

421.2

0.3

280.5

0.2

2nd Ncont Mode Data Ready (see AB-131)

454.8

302.9

DDC112

FIGURE 30. Recommended Shield for DDC112 Layout

Design.

FIGURE 29. Power Supply Connection Options.

DDC112

0.1

< 10

One +5V Supply

DDC112

0.1

Separate +5V Supplies

LAYOUT

Power Supplies and Grounding

Both AV

and DV

should be as quiet as possible. It is

particularly important to eliminate noise from AV

that is

non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies
for AV

and DV

. In this case, each +5V supply of the

DDC112 should be bypassed with 10

F solid tantalum

capacitors and 0.1

F ceramic capacitors. The second case

shows the DV

power supply derived from the AV

supply with a < 10

isolation resistor. In both cases, the

0.1

F capacitors should be placed as close to the DDC112

package as possible.

Shielding Analog Signal Paths

As with any precision circuit, careful printed circuit layout
will ensure the best performance. It is essential to make
short, direct interconnections and avoid stray wiring capaci-
tance--particularly at the analog input pins. Digital signals

should be kept as far from the analog input signals as
possible on the PC board.

Input shielding practices should be taken into consideration
when designing the circuit layout for the DDC112. The
inputs to the DDC112 are high impedance and extremely
sensitive to extraneous noise. Leakage currents between the
PCB traces can exceed the input bias current of the DDC112
if shielding is not implemented. Figure 30 illustrates an
acceptable approach to this problem. A PC ground plane is
placed around the inputs of the DDC112 (pins 1 and 28).
This shield helps minimize coupled noise into the input pins.
Additionally, the pins that are used for the external integra-
tion capacitors (pins 3, 4, 5, 6, 23, 24, 25 and 26) should be
guarded by a ground plane when the external capacitors are
used.

The approach above reduces leakage affects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather than
into the analog input stage of the DDC112.

DDC112

Digital I/O

and

Digital Power

Digital I/O

and

Digital Power

Shield

external

caps when

used

Analog
Ground

Analog

Power

Shield

external

caps when

used

Analog

Ground

Analog

Ground

IN1

IN2

Analog

Ground

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