1
DAC7641
16-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
DAC7641
DESCRIPTION
The DAC7641 is a 16-bit, voltage output digital-to-
analog converter (DAC) with guaranteed 15-bit mono-
tonic performance over the specified temperature range.
It accepts 16-bit parallel input data, has double-buffered
DAC input logic (allowing asynchronous update), and
provides a readback mode of the internal input registers.
Programmable asynchronous reset clears all registers to
a mid-scale code of 8000
H
or to a zero-scale of 0000
H
.
The DAC7641 can operate from a single +5V supply or
from +5V and 5V supplies.
Low power and small size per DAC make the DAC7641
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-
loop servo-control. The DAC7641 is available in a
TQFP-32 package, and offers guaranteed specifica-
tions over the 40
C to +85
C temperature range.
FEATURES
q
LOW POWER: 2.5mW
q
UNIPOLAR OR BIPOLAR OPERATION
q
SETTLING TIME: 10
s to 0.003%
q
15-BIT LINEARITY AND MONOTONICITY:
40
C to +85
C
q
PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
q
DATA READBACK
q
DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
q
PROCESS CONTROL
q
ATE PIN ELECTRONICS
q
CLOSED-LOOP SERVO-CONTROL
q
MOTOR CONTROL
q
DATA ACQUISITION SYSTEMS
q
DAC-PER-PIN PROGRAMMERS
2000 Burr-Brown Corporation
PDS-1532A
Printed in U.S.A. June, 2000
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
DAC
DAC
Register
Input
Register
I/O
Buffer
Control
Logic
V
REF
L
V
REF
H
V
REF
H
Sense
V
REF
L
Sense
V
OUT
RST
LDAC
CS
R/W
DATA I/O
16
RSTSEL
AGND
DGND
V
OUT
Sense
DAC7641
V
CC
V
SS
V
DD
For most current data sheet and other product
information, visit www.burr-brown.com
DAC7641
2
DAC7641
DAC7641Y
DAC7641YB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error
3
4
2
3
LSB
Differential Linearity Error
2
3
1
2
LSB
Monotonicity, T
MIN
to T
MAX
14
15
Bits
Bipolar Zero Error
1
3
T
T
mV
Bipolar Zero Error Drift
5
10
T
T
ppm/
C
Full-Scale Error
1
3
T
T
mV
Full-Scale Error Drift
5
10
T
T
ppm/
C
Power Supply Rejection Ratio (PSRR)
At Full Scale
10
100
T
T
ppm/V
ANALOG OUTPUT
Voltage Output
V
REF
= 2.5V, R
L
= 10k
, V
SS
= 5V
V
REF
L
V
REF
H
T
T
V
Output Current
1.25
+1.25
T
T
mA
Maximum Load Capacitance
No Oscillation
500
T
pF
Short-Circuit Current
10, +30
T
mA
Short-Circuit Duration
GND or V
CC
or V
SS
Indefinite
T
REFERENCE INPUT
Ref High Input Voltage Range
V
REF
L + 1.25
+2.5
T
T
V
Ref Low Input Voltage Range
2.5
V
REF
H 1.25
T
T
V
Ref High Input Current
500
T
A
Ref Low Input Current
500
T
A
DYNAMIC PERFORMANCE
Settling Time
To
0.003%, 5V Output Step
8
10
T
T
s
Digital Feedthrough
2
T
nV-s
Output Noise Voltage
f = 10kHz
60
T
nV/
Hz
DAC Glitch
7FFF
H
to 8000
H
or 8000
H
to 7FFF
H
40
T
nV-s
DIGITAL INPUT
V
IH
0.7 V
DD
T
V
V
IL
0.3 V
DD
T
V
I
IH
10
T
A
I
IL
10
T
A
DIGITAL OUTPUT
V
OH
I
OH
= 0.8mA
3.6
4.5
T
T
V
V
OL
I
OL
= 1.2mA
0.3
0.4
T
T
V
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
T
T
T
V
V
CC
+4.75
+5.0
+5.25
T
T
T
V
V
SS
5.25
5.0
4.75
T
T
T
V
I
CC
0.4
0.5
T
T
mA
I
DD
15
T
A
I
SS
0.6
0.5
0.4
T
T
mA
Power
4
5.5
T
T
mW
TEMPERATURE RANGE
Specified Performance
40
+85
T
T
C
T
Specifications same as DAC7641Y.
SPECIFICATIONS
(Dual Supply)
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= +5V, V
SS
= 5V, V
REF
H = +2.5V, and V
REF
L = 2.5V, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
DAC7641
DAC7641Y
DAC7641YB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error
(1)
3
4
2
3
LSB
Differential Linearity Error
2
3
1
2
LSB
Monotonicity, T
MIN
to T
MAX
14
15
Bits
Zero Scale Error
1
3
T
T
mV
Zero Scale Error Drift
5
10
T
T
ppm/
C
Full-Scale Error
1
3
T
T
mV
Full-Scale Error Drift
5
10
T
T
ppm/
C
Power Supply Rejection Ratio (PSRR)
At Full Scale
10
100
T
T
ppm/V
ANALOG OUTPUT
Voltage Output
V
REF
L = 0V, V
SS
= 0V, R
L
= 10k
0
V
REF
H
T
T
V
Output Current
1.25
+1.25
T
T
mA
Maximum Load Capacitance
No Oscillation
500
T
pF
Short-Circuit Current
30
T
mA
Short-Circuit Duration
GND or V
CC
Indefinite
T
REFERENCE INPUT
Ref High Input Voltage Range
V
REF
L + 1.25
+2.5
T
T
V
Ref Low Input Voltage Range
0
V
REF
H 1.25
T
T
V
Ref High Input Current
250
T
A
Ref Low Input Current
250
T
A
DYNAMIC PERFORMANCE
Settling Time
To
0.003%, 2.5V Output Step
8
10
T
T
s
Digital Feedthrough
2
T
nV-s
Output Noise Voltage, f = 10kHz
60
T
nV/
Hz
DAC Glitch
7FFF
H
to 8000
H
or 8000
H
to 7FFF
H
40
T
nV-s
DIGITAL INPUT
V
IH
0.7 V
DD
T
V
V
IL
0.3 V
DD
T
V
I
IH
10
T
A
I
IL
10
T
A
DIGITAL OUTPUT
V
OH
I
OH
= 0.8mA
3.6
4.5
T
T
V
V
OL
I
OL
= 1.2mA
0.3
0.4
T
T
V
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
T
T
T
V
V
CC
+4.75
+5.0
+5.25
T
T
T
V
V
SS
0
0
0
T
T
T
V
I
CC
0.4
0.5
T
T
mA
I
DD
15
T
A
Power
1.8
2.5
T
T
mW
TEMPERATURE RANGE
Specified Performance
40
+85
T
T
C
T
Specifications same as DAC7641Y.
NOTE: (1) If V
SS
= 0V specification applies at Code 0040
H
and above due to possible negative zero-scale error.
SPECIFICATIONS
(Single Supply)
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= +5V, V
SS
= 0V, V
REF
H = +2.5V, and V
REF
L = 0V, unless otherwise noted.
4
DAC7641
ABSOLUTE MAXIMUM RATINGS
(1)
V
SS
to V
SS
............................................................................. 0.3V to 11V
V
DD
to GND .......................................................................... 0.3V to 5.5V
V
REFL
to GND ............................................................ 0.3V to (V
SS
V
CC
)
V
REFH
to GND ........................................................... 0.3V to (V
SS
V
CC
)
V
REFH
to V
REFL
.................................................................... 0.3V to +11V
Digital Input Voltage to GND ................................... 0.3V to V
DD
+ 0.3V
Digital Output Voltage to GND ................................. 0.3V to V
DD
+ 0.3V
Maximum Junction Temperature ................................................... +150
C
Operating Temperature Range ........................................ 40
C to +85
C
Storage Temperature Range ......................................... 65
C to +150
C
Lead Temperature (soldering, 10s) ............................................... +300
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
DIFFERENTIAL
PACKAGE
SPECIFICATION
ACCURACY
NONLINEARITY
DRAWING
TEMPERATURE
ORDERING
TRANSPORT
PRODUCT
(LSB)
(LSB)
PACKAGE
NUMBER
RANGE
NUMBER
(1)
MEDIA
DAC7641Y
4
3
TQFP-32
351
40
C to +85
C
DAC7641Y/250
Tape and Reel
"
"
"
"
"
"
DAC7641Y/2K
Tape and Reel
DAC7641YB
3
2
TQFP-32
351
40
C to +85
C
DAC7641YB/250
Tape and Reel
"
"
"
"
"
"
DAC7641YB/2K
Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of "DAC7641Y/2K" will get a single 2000-piece Tape and Reel.
5
DAC7641
19
LDAC
DAC Load Strobe, rising-edge triggered.
20
RST
Reset, rising-edge triggered. Depending on the state
of RSTSEL, the DAC registers are set to either mid-
scale or zero.
21
RSTSEL
Reset Select. Determines the action of RST. If
HIGH, a RST command will set the DAC registers to
mid-scale. If LOW, a RST command will set the DAC
registers to zero.
22
V
OUT
DAC Voltage Output
23
V
OUT
Sense
DAC Output Amplifier Inverting Input. Used to close
the feedback loop at the load.
24
V
SS
Negative Power Supply
25
AGND
Analog Ground
26
V
CC
Positive Power Supply
27
V
REFH
Sense
DAC Reference High Sense Input
28
V
REFH
DAC Reference High Input
29
V
REFL
Sense
DAC Reference Low Sense Input
30
V
REFL
DAC Reference Low Input
31
DGND
Digital Ground
32
V
DD
Positive Power Supply
PIN
NAME
DESCRIPTION
1
DB15
Data Bit 15, MSB
2
DB14
Data Bit 14
3
DB13
Data Bit 13
4
DB12
Data Bit 12
5
DB11
Data Bit 11
6
DB10
Data Bit 10
7
DB9
Data Bit 9
8
DB8
Data Bit 8
9
DB7
Data Bit 7
10
DB6
Data Bit 6
11
DB5
Data Bit 5
12
DB4
Data Bit 4
13
DB3
Data Bit 3
14
DB2
Data Bit 2
15
DB1
Data Bit 1
16
DB0
Data Bit 0, LSB
17
CS
Chip Select, active low.
18
R/W
Enabled by CS, controls data read and write from the
input register.
PIN DESCRIPTIONS
PIN CONFIGURATION
PIN
NAME
DESCRIPTION
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
V
SS
V
OUT
Sense
V
OUT
RSTSEL
RST
LDAC
R/W
CS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DAC7641
V
DD
DGND
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
32
31
30
29
28
27
26
25
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
9
10
11
12
13
14
15
16
6
DAC7641
TYPICAL PERFORMANCE CURVES: V
SS
= 0V
At T
A
= +25
C, V
DD
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
3.0
2.0
1.0
0
1.0
2.0
3.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
3.0
2.0
1.0
0
1.0
2.0
3.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+85
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
3.0
2.0
1.0
0
1.0
2.0
3.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(40
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2
1.5
1
0.5
0
0.5
1
1.5
2
Temperature (
C)
40 30 20 10 0
10 20 30 40 50 60 70 80
90
ZERO-SCALE ERROR vs TEMPERATURE
UPO (mV)
Code (0040
H
)
2
1.5
1
0.5
0
0.5
1
1.5
2
Temperature (
C)
40 30 20 10 0
10 20 30 40 50 60 70 80
90
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
Positive Full-Scale Error (mV)
Code (FFFF
H
)
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
V
REFH
CURRENT vs CODE
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
7
DAC7641
TYPICAL PERFORMANCE CURVES: V
SS
= 0V
(Cont.)
At T
A
= +25
C, V
DD
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
V
REFL
CURRENT vs CODE
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
+5V
LDAC
0
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +2.5V)
Output Voltage
Large-Signal Settling Time: 0.5V/div
Small-Signal Settling Time: 4LSB/div
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to 2mV)
Output Voltage
+5V
LDAC
0
Large-Signal Settling Time: 0.5V/div
Small-Signal Settling Time: 4LSB/div
Time (1
s/div)
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
+5V
LDAC
0
7FFF
H
to 8000
H
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Digital Input Code
0000
H
0200
H
0400
H
0800
H
1000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
I
CC
I
CC
(mA)
1.0
0.8
0.6
0.4
0.2
0.0
0.2
0.4
0.6
0.8
1.0
Temperature (
C)
40 30 20 10 0
10 20
30 40
50 60 70
80
90
POWER SUPPLY CURRENT vs TEMPERATURE
Quiescent Current (mA)
Data = FFFF
H
No Load
I
CC
8
DAC7641
TYPICAL PERFORMANCE CURVES: V
SS
= 0V
(Cont.)
At T
A
= +25
C, V
DD
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
Time (1
s/div)
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
+5V
LDAC
0
8000
H
to 7FFF
H
BROADBAND NOISE
Time (10ms/div)
Noise Voltage (50
V/div)
BW = 10kHz
Code = 8000
H
1000
100
10
Frequency (Hz)
10
100
1000
10000
100000
1000000
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV/
Hz)
5
4
3
2
1
0
R
LOAD
(k
)
0.01
0.1
1
10
100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Source
Sink
12
10
8
6
4
2
0
Logic Input Level for Data Bits (V)
0
1
2
3
4
5
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DATA BITS
Logic Supply Current (mA)
9
DAC7641
TYPICAL PERFORMANCE CURVES: V
SS
= 5V
At T
A
= +25
C, V
DD
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
3.0
2.0
1.0
0
1.0
2.0
3.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
3.0
2.0
1.0
0
1.0
2.0
3.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+85
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
3.0
2.0
1.0
0
1.0
2.0
3.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(40
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0.30
0.25
0.20
0.15
0.10
0.05
0.00
V
REFH
CURRENT vs CODE
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0.00
0.05
0.10
0.15
0.20
0.25
0.30
V
REFL
CURRENT vs CODE
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2
1.5
1
0.5
0
0.5
1
1.5
2
Temperature (
C)
ZERO-SCALE ERROR vs TEMPERATURE
(Code 8000
H
)
Zero-Scale Error (mV)
40 30 20 10 0
10 20 30 40 50 60 70 80
90
10
DAC7641
TYPICAL PERFORMANCE CURVES: V
SS
= 5V
(Cont.)
At T
A
= +25
C, V
DD
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
5
4
3
2
1
0
1
2
3
4
5
R
LOAD
(k
)
0.01
0.1
1
10
100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Source
Sink
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
I
CC
(mA)
Digital Input Code
0000
H
0200
H
0400
H
0800
H
1000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
I
CC
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(2.5V to +2.5V)
Output Voltage
+5V
LDAC
0
Large-Signal Settling Time: 1V/div
Small-Signal Settling Time: 2LSB/div
2
1.5
1
0.5
0
0.5
1
1.5
2
Temperature (
C)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFF
H
)
Positive Full-Scale Error (mV)
40 30 20 10 0
10 20 30 40 50 60 70 80
90
2
1.5
1
0.5
0
0.5
1
1.5
2
Temperature (
C)
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 0000
H
)
Negative Full-Scale Error (mV)
40 30 20 10 0
10 20 30 40 50 60 70 80
90
POWER SUPPLY CURRENT
vs TEMPERATURE
Quiescent Current (mA)
I
SS
Data = FFFF
H
No Load
1.0
0.8
0.6
0.4
0.2
0.0
0.2
0.4
0.6
0.8
1.0
Temperature (
C)
40 30 20 10 0
10 20
30 40
50 60 70
80
90
I
CC
11
DAC7641
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to 2.5V)
Output Voltage
Large-Signal Settling Time: 1V/div
Small-Signal Settling Time:
2LSB/div
+5V
LDAC
0
TYPICAL PERFORMANCE CURVES: V
SS
= 5V
(Cont.)
At T
A
= +25
C, V
DD
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
THEORY OF OPERATION
The DAC7641 is a voltage output, 16-bit digital-to-analog
converter (DAC). The architecture is an R-2R ladder con-
figuration with the three MSBs segmented, followed by an
operational amplifier that serves as a buffer (see Figure 1).
The minimum voltage output (zero-scale) and maximum
voltage output (full-scale) are set by the external voltage
references V
REF
L and V
REF
H, respectively. The digital input
is a 16-bit parallel word and the DAC input register offers a
readback capability. The converters can be powered from
either a single +5V supply or a dual
5V supply. The device
offers a reset function which immediately sets all DAC
output voltages and DAC registers to mid-scale code 8000
H
or to zero-scale code 0000
H
. See Figures 2 and 3 for the
basic operation of the DAC7641.
R
2R
R
F
2R
2R
2R
2R
2R
2R
2R
2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
FIGURE 1. DAC7641 Architecture.
12
DAC7641
FIGURE 2. Single-Supply Operation.
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
V
SS
V
OUT
Sense
V
OUT
RSTSEL
RST
LDAC
R/W
CS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DAC7641
9
10
11
12
13
14
15
16
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CHIP SELECT
32
DGND
31
30
29
28
0V
+2.5000V
27
26
25
V
DD
DGND
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
READ/WRITE STROBE
DAC LOAD STROBE
DAC RESET
DAC RESET MODE SELECT
0V to +2.5V
0.1
F
1
F
AGND
+5V
+
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
V
SS
V
OUT
Sense
V
OUT
RSTSEL
RST
LDAC
R/W
CS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DAC7641
9
10
11
12
13
14
15
16
CHIP SELECT
32
DGND
31
30
29
28
2.500V +2.500V
27
26
25
V
DD
DGND
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
READ/WRITE STROBE
DAC LOAD STROBE
DAC RESET
DAC RESET MODE SELECT
2.5V to +2.5V
0.1
F
1
F
+5V
+
0.1
F
1
F
AGND
+
5V
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FIGURE 3. Dual-Supply Operation.
13
DAC7641
ANALOG OUTPUTS
When V
SS
= 5V (dual supply operation), the output ampli-
fier can swing to within 2.25V of the supply rails, guaran-
teed over the 40
C to +85
C temperature range. With V
SS
= 0V (single-supply operation), and with R
LOAD
also con-
nected to ground, the output can swing to ground. Care must
be taken when measuring the zero-scale error with V
SS
= 0V.
Since the output voltage cannot swing below ground, the
output voltage may not change for the first few digital input
codes (0000
H
, 0001
H
, 0002
H
, etc.) if the output amplifier has
a negative offset. At the negative limit of 2mV, the first
specified output starts at code 0040
H
.
Due to the high accuracy of these D/A converters, system
design problems such as grounding and contact resistance
become very important. A 16-bit converter with a 2.5V full-
scale range has a 1LSB value of 38
V. With a load current
of 1mA, series wiring and connector resistance (see Figure
4) of only 40m
(R
W2
) will cause a voltage drop of 40
V.
To understand what this means in terms of a system layout,
the resistivity of a typical 1 ounce copper-clad printed circuit
board is 1/2 m
per square. For a 1mA load, a 10 milli-inch
wide printed circuit conductor 600 milli-inches long will
result in a voltage drop of 30
V.
The DAC7641 offers a force and sense output configuration
for the high open-loop gain output amplifier. This feature
allows the loop around the output amplifier to be closed at the
load (see Figure 4), thus ensuring an accurate output voltage.
REFERENCE INPUTS
The reference inputs, V
REF
L and V
REF
H, can be any voltage
between V
SS
+ 2.5V and V
CC
2.5V provided that V
REF
H is
at least 1.25V greater than V
REF
L. The minimum output of
each DAC is equal to V
REF
L
plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to V
REF
H plus a similar offset voltage. Note
that V
SS
(the negative power supply) must either be
FIGURE 4. Analog Output Closed-Loop Configuration. R
W
represents wiring resistances.
connected to ground or must be in the range of 4.75V to
5.25V. The voltage on V
SS
sets several bias points within
the converter. If V
SS
is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not guaranteed.
The current into the V
REF
H input and out of V
REF
L depends
on the DAC output voltages and can vary from a few
microamps to approximately 0.5mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. The DAC7641 features a reference drive and
sense connection such that the internal errors caused by the
changing reference current and the circuit impedances can
be minimized. Figures 5 through 13 show different reference
configurations and the effect on the linearity and differential
linearity.
FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance Curves.
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
R
W1
R
W2
V
OUT
Sense
V
OUT
V
SS
24
23
22
+2.5V
+V
V
OUT
500pF
OPA2234
500pF
+2.5V
+V
2.5V
V
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
V
OUT
14
DAC7641
FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV.
1000pF
2200pF
OPA2350
100
1000pF
NOTE: V
REFL
has been chosen to be 50mV to allow for current sinking voltage
drops across the 100
resistor and the output stage of the buffer op amp.
2200pF
98k
0.05V
2k
+2.5V
100
+V
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
V
OUT
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
FIGURE 7. Integral Linearity and Differential Linearity
Error Curves for Figure 6.
FIGURE 8. Integral Linearity and Differential Linearity
Error Curves for Figure 9.
15
DAC7641
1000pF
2200pF
OPA2350
100
1000pF
2200pF
100
+2.5V
+V
+1.25V
+V
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
V
OUT
FIGURE 9. Single-Supply Buffered Reference with V
REF
L = +1.25V and V
REF
H = +2.5V.
FIGURE 10. Single-Supply Buffered V
REF
H.
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
1000pF
100
+2.5V
OPA350
+V
2200pF
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
V
OUT
16
DAC7641
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7641. Note
that the internal register is edge triggered and not level
triggered. When the LDAC signal is transitioned to HIGH,
the digital word currently in the register is latched.
The double-buffered architecture is designed so that the
DAC input register can be written to at any time.
FIGURE 12. Low Cost Single-Supply Configuration.
DIGITAL TIMING
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7641.
DIGITAL INPUT CODING
The DAC7641 input data is in Straight Binary format. The
output voltage is given by Equation 1.
INPUT
R/W
CS
RST RSTSEL LDAC REGISTER
REGISTER
MODE
L
L
H
X
X
Write
Hold
Write Input
H
L
H
X
X
Read
Hold
Read Input
X
H
H
X
Hold
Write
Update
X
H
H
X
H
Hold
Hold
Hold
X
X
L
X
Reset to Zero
Reset to Zero
X
X
H
X
Reset to Midscale Reset to Midscale
TABLE I. DAC7641 Logic Truth Table.
(1)
V
V
L
V
H
V
L
N
OUT
REF
REF
REF
=
+
(
)
,
65 536
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
+2.5V
+V
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
V
OUT
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
17
DAC7641
t
RCS
CS
t
RDS
t
RDH
t
CSD
t
DZ
R/W
Data Out
Data Valid
t
WCS
CS
t
WS
t
WH
R/W
t
LS
t
LWD
t
LH
t
S
0.003% of FSR
Error Band
0.003% of FSR
Error Band
t
LX
LDAC
t
DS
t
DH
Data In
V
OUT
Data Read Timing
Data Write Timing
t
RSH
RST
V
OUT
, RSTSEL LOW
+FS
FS
t
SS
t
SH
RSTSEL
V
OUT
, RSTSEL HIGH
MS
+FS
FS
DAC7641 Reset Timing
t
RSS
FIGURE 14. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
RCS
CS LOW for Read
150
ns
t
RDS
R/W HIGH to CS LOW
10
ns
t
RDH
R/W HIGH after CS HIGH
10
ns
t
DZ
CS HIGH to Data Bus in High Impedance
10
100
ns
t
CSD
CS LOW to Data Bus Valid
100
150
ns
t
WCS
CS LOW for Write
40
ns
t
WS
R/W LOW to CS LOW
0
ns
t
WH
R/W LOW after CS HIGH
10
ns
t
LS
CS LOW to LDAC HIGH
30
ns
t
LH
CS LOW after LDAC HIGH
100
ns
t
LX
LDAC HIGH
100
ns
t
DS
Data Valid to CS LOW
0
ns
t
DH
Data Valid after CS HIGH
10
ns
t
LWD
LDAC LOW
100
ns
t
SS
RSTSEL Valid Before RESET HIGH
0
ns
t
SH
RSTSEL Valid After RESET HIGH
200
ns
t
RSS
RESET LOW Before RESET HIGH
10
ns
t
RSH
RESET LOW After RESET HIGH
10
ns
t
S
Settling Time
10
s
TABLE II. Timing Specifications (T
A
= 40
C to +85
C).
18
DAC7641
FIGURE 15. 4-to-20mA Digitally Controlled Current Source.
1000pF
2200pF
OPA2350
100
1000pF
2200pF
80k
20k
+0.50v
100
+2.5V
+V
V
REFL
V
REFL
Sense
V
REFH
V
REFH
Sense
V
CC
AGND
30
29
28
27
26
25
DAC7641
V
OUT
Sense
V
OUT
V
SS
24
23
22
I
OUT
V
PROGRAMMED
R
SENSE
125
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
The DAC7641 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7641 offers
both a differential reference input as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows transistor
to be placed within the loop to implement a digitally-
programmable, uni-directional current source. The availabil-
ity of a differential reference also allows programmability
for both the full-scale and zero-scale currents. The output
current is calculated as:
Figure 15 shows a DAC7641 in a 4mA to 20mA current
output configuration. The output current can be determined
by Equation 3:
At full-scale, the output current is 16mA plus the 4mA for
the zero current. At zero scale the output current is the offset
current of 4mA (0.5V/125
).
(2)
(3)
I
V
H
V
L
R
N Value
V
L R
OUT
REF
REF
SENSE
REF
SENSE
=
+
(
)
,
/
65 536
I
V
V
N Value
V
OUT
=
+
2 5
0 5
125
65 536
0 5
125
.
.
,
.
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