1999 Burr-Brown Corporation
PDS-1501A
Printed in U.S.A. June, 1999
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
DAC7612
Dual, 12-Bit Serial Input
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
The DAC7612 is a dual, 12-bit digital-to-analog con-
verter (DAC) with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It
requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and
high speed rail-to-rail output amplifiers. For a full-
scale step, each output will settle to 1 LSB within 7
s
while only consuming 3.7mW.
The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), Serial Data In (SDI), Chip Select (CS) and
Load DACs (LOADDACS) comprise the serial inter-
face.
The DAC7612 is available in an 8-lead SOIC package
and is fully specified over the industrial temperature
range of 40
C to +85
C.
FEATURES
q
LOW POWER: 3.7mW
q
FAST SETTLING: 7
s to 1 LSB
q
1mV LSB WITH 4.095V FULL-SCALE
RANGE
q
COMPLETE WITH REFERENCE
q
12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
q
3-WIRE INTERFACE: Up to 20MHz Clock
q
SMALL PACKAGE: 8-Lead SOIC
APPLICATIONS
q
PROCESS CONTROL
q
DATA ACQUISITION SYSTEMS
q
CLOSED-LOOP SERVO-CONTROL
q
PC PERIPHERALS
q
PORTABLE INSTRUMENTATION
DAC7612
12-Bit DAC A
DAC Register A
14-Bit Serial Shift Register
12
12
DAC Register B
Ref
12
12
LOADDACS
CS
CLK
SDI
V
DD
GND
V
OUTA
DAC7612
12-Bit DAC B
V
OUTB
2
DAC7612
SPECIFICATIONS
At T
A
= 40
C to +85
C, and V
DD
= +5V, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC7612U
DAC7612UB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
12
T
Bits
ACCURACY
Relative Accuracy
(1)
2
1/2
+2
1
1/4
+1
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
1/2
+1
1
1/4
+1
LSB
Zero-Scale Error
Code 000
H
1
+1
+3
T
T
T
LSB
Zero Scale Match
Code 000
H
1/2
1/2
2
LSB
Full-Scale Voltage
Code FFF
H
4.079
4.095
4.111
4.087
4.095
4.103
V
Full-Scale Match
Code FFF
H
1/2
1/2
2
LSB
ANALOG OUTPUT
Output Current
Code 800
H
5
7
T
T
mA
Load Regulation
R
LOAD
402
, Code 800
H
1
3
T
T
LSB
Capacitive Load
No Oscillation
500
T
pF
Short-Circuit Current
15
T
mA
Short-Circuit Duration
GND or V
DD
Indefinite
T
DIGITAL INPUT
Data Format
Serial
T
Data Coding
Straight Binary
T
Logic Family
CMOS
T
Logic Levels
V
IH
0.7 V
DD
T
V
V
IL
0.3 V
DD
T
V
I
IH
10
T
A
I
IL
10
T
A
DYNAMIC PERFORMANCE
Settling Time
(2)
(t
S
)
To
1 LSB of Final Value
7
T
s
DAC Glitch
2.5
T
nV-s
Digital Feedthrough
0.5
T
nV-s
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
T
T
T
V
I
DD
V
IH
= 5V, V
IL
= 0V, No Load, at Code 000
H
0.75
1.5
T
T
mA
Power Dissipation
V
IH
= 5V, V
IL
= 0V, No Load
3.5
7.5
T
T
mW
Power Supply Sensitivity
V
DD
=
5%
0.0025
0.002
T
T
%/%
TEMPERATURE RANGE
Specified Performance
40
+85
T
T
C
T
Same specification as for DAC7612U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
3
DAC7612
PIN CONFIGURATION
Top View
SO-8
V
DD
to GND .......................................................................... 0.3V to 6V
Digital Inputs to GND .............................................. 0.3V to V
DD
+ 0.3V
V
OUT
to GND ........................................................... 0.3V to V
DD
+ 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance,
JA
........................................................... 150
C/W
Maximum Junction Temperature .................................................. +150
C
Operating Temperature Range ...................................... 40
C to +85
C
Storage Temperature Range ....................................... 65
C to +150
C
Lead Temperature (soldering, 10s) .............................................. +300
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
SDI
Serial Data Input. Data is clocked into the internal
serial register on the rising edge of CLK.
2
CLK
Synchronous Clock for the Serial Data Input.
3
LOADDACS
Loads the internal DAC registers. All DAC registers
are transparent latches and are transparent when
LOADDACS is LOW (regardless of the state of CS
or CLK).
4
CS
Chip Select. Active LOW.
5
V
OUTB
DAC B Output Voltage
6
GND
Ground
7
V
DD
Positive Power Supply
8
V
OUTA
DAC A Output Voltage
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
DIFFERENTIAL
SPECIFICATION
PACKAGE
ACCURACY
NONLINEARITY
TEMPERATURE
DRAWING
ORDERING
TRANSPORT
PRODUCT
(LSB)
(LSB)
RANGE
PACKAGE
NUMBER
(1)
NUMBER
(2)
MEDIA
DAC7612U
2
1
40
C to +85
C
SO-8
182
DAC7612U
Rails
"
"
"
"
"
"
DAC7612U/2K5
Tape and Reel
DAC7612UB
1
1
40
C to +85
C
SO-8
182
DAC7612UB
Rails
"
"
"
"
"
"
DAC7612UB/2K5
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "DAC7612U/2K5" will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
1
2
3
4
8
7
6
5
SDI
CLK
LOADDACS
CS
V
OUTA
V
DD
GND
V
OUTB
DAC7612U
4
DAC7612
EQUIVALENT INPUT LOGIC
Serial Shift Register
DAC B Register
DAC A Register
DAC Switches
Data
DAC Switches
12
12
12
12
ESD protection
diodes to V
DD
and GND
LOADDACS
SDI
CS
CLK
5
DAC7612
TIMING DIAGRAMS
LOGIC TRUTH TABLE
TIMING SPECIFICATIONS
T
A
= 40
C to +85
C and V
DD
= +5V.
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
t
CH
Clock Width HIGH
30
ns
t
CL
Clock Width LOW
30
ns
t
LDW
Load Pulse Width
20
ns
t
DS
Data Setup
15
ns
t
DH
Data Hold
15
ns
t
LD1
Load Setup
15
ns
t
LD2
Load Hold
10
ns
t
CSS
Select
30
ns
t
CSH
Deselect
20
ns
NOTE: All input control signals are specified with t
R
= t
F
= 5ns (10% to 90%
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
SDI
CLK
t
CL
t
CH
t
DH
t
DS
SERIAL SHIFT
DAC
DAC
A1
A0
CLK
CS
LOADDACS
REGISTER
REGISTER A
REGISTER B
X
X
X
H
H
No Change
No Change
No Change
X
X
L
H
Shifts One Bit
No Change
No Change
L
X
X
H
(1)
L
No Change
Loads Serial
Loads Serial
Data Word
Data Word
H
L
X
H
L
No Change
Loads Serial
No Change
Data Word
H
H
X
H
L
No Change
No Change
Loads Serial
Data Word
Positive Logic Transition; X = Don't Care.
NOTE: (1) A HIGH value is suggested in order to avoid to "false clock" from
advancing the shift register and changing the DAC voltage.
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12 B13
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA INPUT TABLE
A1
(MSB)
(LSB)
SDI
CLK
CS
LOADDACS
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
CSS
t
LD1
t
LD2
t
CSH
LOADDACS
FS
ZS
V
OUT
t
LDW
t
S
1 LSB
Error Band
6
DAC7612
TYPICAL PERFORMANCE CURVES
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
5.0
4.8
4.6
4.4
4.2
4.0
MINIMUM SUPPLY VOLTAGE vs LOAD
V
DD
Minimum (V)
Output Load Current (mA)
0.01
0.1
1
10
5
4
3
2
1
0
OUTPUT SWING vs LOAD
Output Voltage (V)
Load Resistance (
)
10
100
1k
10k
100k
R
L
tied to V
DD
Data = 000
H
R
L
tied to GND
Data = FFF
H
70
60
50
40
30
20
10
0
POWER SUPPLY REJECTION vs FREQUENCY
PSR (dB)
Frequency (Hz)
10
100
1k
10k
100k
1M
Data = FFF
H
V
DD
= 5V
200mV AC
Time (2ms/div)
Code = FFF
H
, BW = 1MHz
BROADBAND NOISE
Noise Voltage (500
V/div)
1k
100
10
1
0.1
0.01
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
Delta V
OUT
(mV)
Current (mA)
0.001
0.01
0.1
1
10
100
+85
C
Data = 000
H
40
C
+25
C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
Supply Current (mA)
Logic Voltage (V)
0
1
2
3
4
5
7
DAC7612
RISE TIME DETAIL
V
OUT
(1mV/div)
Time (10
s/div)
LOADDACS
C
L
= 100pF
R
L
= No Load
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
20
15
10
5
0
5
10
15
20
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
Output Current (mA)
Output Voltage (V)
0
1
4
2
3
5
6
Positive
Current
Limit
Data = 800
H
Output tied to I
SOURCE
Negative
Current
Limit
MIDSCALE GLITCH PERFORMANCE
V
OUT
(5mV/div)
Time (500ns/div)
7FF
H
to 800
H
LOADDACS
MIDSCALE GLITCH PERFORMANCE
V
OUT
(5mV/div)
Time (500ns/div)
800
H
to 7FF
H
LOADDACS
LARGE-SIGNAL SETTLING TIME
V
OUT
(1V/div)
Time (20
s/div)
C
L
= 100pF
R
L
= No Load
LOADDACS
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
SUPPLY CURRENT vs TEMPERATURE
Supply Current (mA)
Temperature (
C)
50
30
10
10
30
50
70
90
110
130
V
LOGIC
= 3.5V
Data = FFF
H
No Load
V
DD
= 4.75V
At worst-case digital inputs.
V
DD
= 5.25V
V
DD
= 5.0V
8
DAC7612
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
10.000
1.000
0.100
0.010
OUTPUT VOLTAGE NOISE vs FREQUENCY
Noise (
V/
Hz)
Frequency (Hz)
10
100
1k
10k
100k
Data = FFF
H
5
4
3
2
1
0
1
2
3
4
5
LONG-TERM DRIFT ACCELERATED BY BURN-IN
Output Voltage Change at FS (mV)
Hours of Operation at +150
C
0
168
336
504
672
840
1008
Max
Avg
Min
4.111
4.103
4.095
4.087
4.079
FULL-SCALE VOLTAGE vs TEMPERATURE
Full-Scale Output (V)
Temperature (
C)
40
15
10
35
60
85
Avg + 3
Avg 3
Avg
35
30
25
20
15
10
5
0
12 10
8
6
4
2
0
2
8
4
6
10
12
T.U.E =
(INL + Z
SE
+ FSE)
Sample Size = 200 Units
T
A
= +25
C
Number of Units
TOTAL UNADJUSTED ERROR HISTOGRAM
FALL TIME DETAIL
V
OUT
(1mV/div)
Time (10
s/div)
C
L
= 100pF
R
L
= No Load
LOADDACS
3
2
1
0
1
ZERO-SCALE VOLTAGE vs TEMPERATURE
Zero-Scale Output (mV)
Temperature (
C)
40
15
10
35
60
85
Avg 3
Avg
Avg + 3
9
DAC7612
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LINEARITY ERROR vs DIGITAL CODE
(DAC A at +85
C)
Linearity Error (LSBs)
Code
0
512
1024
1536
2048
2560
3072
3584
4096
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LINEARITY ERROR vs DIGITAL CODE
(DAC B at +85
C)
Linearity Error (LSBs)
Code
0
512
1024
1536
2048
2560
3072
3584
4096
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LINEARITY ERROR vs DIGITAL CODE
(DAC A at +25
C)
Linearity Error (LSBs)
Code
0
512
1024
1536
2048
2560
3072
3584
4096
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LINEARITY ERROR vs DIGITAL CODE
(DAC B at +25
C)
Linearity Error (LSBs)
Code
0
512
1024
1536
2048
2560
3072
3584
4096
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LINEARITY ERROR vs DIGITAL CODE
(DAC A at 40
C)
Linearity Error (LSBs)
Code
0
512
1024
1536
2048
2560
3072
3584
4096
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LINEARITY ERROR vs DIGITAL CODE
(DAC B at 40
C)
Linearity Error (LSBs)
Code
0
512
1024
1536
2048
2560
3072
3584
4096
10
DAC7612
next 12 bits are the code (MSB-first) sent to the DAC. The
data format is Straight Binary and is loaded MSB-first into
the shift registers after loading the address bits. Table I shows
the relationship between input code and output voltage.
The digital data into the DAC7612 is double-buffered. This
means that new data can be entered into the chosen DAC
without disturbing the old data and the analog output of the
converter. At some point after the data has been entered into
the serial shift register, this data can be transferred into the
DAC registers. This transfer is accomplished with a HIGH
to LOW transition of the LOADDACS pin. The LOADDACS
pin makes the DAC registers transparent. If new data is
shifted into the shift register while LOADDACS is LOW,
the DAC output voltages will change as each new bit is
entered. To prevent this, LOADDACS must be returned
HIGH prior to shifting in new serial data.
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal ref-
erence voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. Each DAC output is internally connected to a
rail-to-rail output operational amplifier.
OUTPUT AMPLIFIER
A precision, low-power amplifier buffers the output of each
DAC section and provides additional gain to achieve a 0V to
4.095V range. Each amplifier has low offset voltage, low
OPERATION
The DAC7612 is a dual, 12-bit digital-to-analog converter
(DAC) complete with a serial-to-parallel shift register, DAC
registers, laser-trimmed 12-bit DACs, on-board reference,
and rail-to-rail output amplifiers. Figure 1 shows the basic
operation of the DAC7612.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7612. The interface consists of
a Serial Clock (CLK), Serial Data (SDI), and a Load DAC
signal (LOADDACS). In addition, a chip select (CS) input is
available to enable serial communication when there are
multiple serial devices. Loading either DAC A or DAC B is
done by shifting 14 serial bits in via the SDI input. The first
2 bits represent the address of the DAC to be updated and the
DAC7612 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE
ANALOG OUTPUT
STRAIGHT OFFSETBINARY
(V)
DESCRIPTION
FFF
H
+4.095
Full Scale
801
H
+2.049
Midscale + 1 LSB
800
H
+2.048
Midscale
7FF
H
+2.047
Midscale 1 LSB
000
H
0
Zero Scale
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
FIGURE 1. Basic Operation of the DAC7612.
1
2
3
4
8
7
6
5
SDI
CLK
LOADDACS
CS
V
OUTA
V
DD
GND
V
OUTB
DAC7612U
Serial Data
Serial Clock
Load DACs
Chip Select
0.1
F
0V to +4.095V
0V to +4.095V
10
F
+
11
DAC7612
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion of
the DAC7612.
The output amplifier has a 7
s typical settling time to
1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positive-
going signals.
The rail-to-rail output stage of the amplifier provides the full-
scale range of 0V to 4.095V while operating on a supply voltage
as low as 4.75V. In addition to its ability to drive resistive loads,
the amplifier will remain stable while driving capacitive loads
of up to 500pF. See Figure 3 for an equivalent circuit schematic
of the amplifier's output driver and the Typical Performance
Curves section for more information regarding settling time,
load driving capability, and output noise.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7612 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (SDI, CLK, CS,
LOADDACS) as close as possible to either V
DD
or ground.
This will keep the CMOS inputs (see "Supply Current vs
Logic Input Voltages" in the Typical Performance Curves)
from shunting current between V
DD
and ground.
The DAC7612 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1
F capacitor taking
priority in this regard. The "Power Supply Rejection vs
Frequency" graph in the Typical Performance Curves sec-
tion shows the PSRR performance of the DAC7612. This
should be taken into account when using switching power
supplies or DC/DC converters.
In addition to offering guaranteed performance with V
DD
in
the 4.75V to 5.25V range, the DAC7612 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
"V
DD
vs Load Current" graph in the Typical Performance
Curves section for more information.
FIGURE 2. Simplified Schematic of Analog Portion.
FIGURE 3. Simplified Driver Section of Output Amplifier.
N-Channel
P-Channel
V
DD
V
OUT
GND
2R
2R
2R
R
2R
2R
R
R
1
R
R
2
Output Amplifier
R-2R DAC
Bandgap
Reference
2.435V
Typical of DAC A or DAC B
Buffer
12
DAC7612
FIGURE 4. Suggested Power and Ground Connections for a DAC7612 Sharing a +5V Supply with a Digital System.
APPLICATIONS
POWER AND GROUNDING
The DAC7612 can be used in a wide variety of situations--
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some appli-
cations require better performance than others, or are par-
ticularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
A precision analog component requires careful layout, ad-
equate bypassing, and a clean, well-regulated power supply.
As the DAC7612 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal proces-
sors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
Because the DAC7612 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through this pin. The GND pin is also the ground
reference point for the internal bandgap reference. Ideally,
GND would be connected directly to an analog ground
plane. This plane would be separate from the ground con-
nection for the digital components until they are connected
at the power entry point of the system (see Figure 4).
The power applied to V
DD
should be well regulated and low-
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between V
DD
and V
OUT
.
As with the GND connection, V
DD
should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10
F and 0.1
F capaci-
tors shown in Figure 4 are strongly recommended and
should be installed as close to V
DD
and ground as possible.
In some situations, additional bypassing may be required
such as a 100
F electrolytic capacitor or even a "Pi" filter
made up of inductors and capacitors--all designed to essen-
tially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
+
+5V
GND
100
F
Digital Circuits
+5V
GND
+5V
Power
Supply
Other
Analog
Components
V
DD
GND
DAC7612
+
10
F
0.1
F
Optional
PDF 
ZIP