8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
with FLASH Memory
FEATURES
q
24 BITS NO MISSING CODES
q
0.0015% INL
q
22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
q
4K BYTES OF FLASH MEMORY
PROGRAMMABLE FROM 2.7V TO 5.25V
q
PGA FROM 1 TO 128
q
SINGLE CYCLE SETTLING MODE
q
PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
q
PRECISION ON-CHIP 1.25V/2.5V REFERENCE:
ACCURACY: 0.2%
DRIFT: 5ppm/
C
q
EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 2.5V
q
ON-CHIP CALIBRATION
q
PIN COMPATIBLE WITH ADS1216
q
SPITM COMPATIBLE
q
2.7V TO 5.25V
q
< 1mW POWER CONSUMPTION
DESCRIPTION
The ADS1218 is a precision, wide dynamic range, delta-sigma, Analog-to-
Digital (A/D) converter with 24-bit resolution and FLASH memory operating
from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to
24 bits of no missing code performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal buffering can be selected
to provide a very high input impedance for direct connection to transducers
or low-level voltage signals. Burn out current sources are provided that allow
for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/
A) converter provides an offset correction with a range of 50% of the FSR
(Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to
128 with an effective resolution of 19 bits at a gain of 128. The A/D
conversion is accomplished with a second-order delta-sigma modulator and
programmable sinc filter. The reference input is differential and can be used
for ratiometric conversion. The on-board current DACs (Digital-to-Analog
Converters) operate independently with the maximum current set by an
external resistor.
The serial interface is SPI compatible. Eight bits of digital I/O are also provided
that can be used for input or output. The ADS1218 is designed for high-resolution
measurement applications in smart transmitters, industrial process control, weight
scales, chromatography, and portable instrumentation.
APPLICATIONS
q
INDUSTRIAL PROCESS CONTROL
q
LIQUID /GAS CHROMATOGRAPHY
q
BLOOD ANALYSIS
q
SMART TRANSMITTERS
q
PORTABLE INSTRUMENTATION
q
WEIGHT SCALES
q
PRESSURE TRANSDUCERS
ADS1218
SPI is a registered trademark of Motorola.
ADS1218
SBAS187 SEPTEMBER 2001
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
BUF
PGA
A = 1:128
+
1.25V or
2.5V
Reference
Clock Generator
Registers
Serial Interface
2nd-Order
Modulator
RAM
4K Bytes
FLASH
AGND
AV
DD
IN+
IN
R
DAC
V
REFOUT
V
RCAP
V
REF+
V
REF
X
IN
X
OUT
DSYNC
PDWN
RESET
DRDY
BUFEN
DGND
DV
DD
WREN
Digital I/O
Interface
D7
...
D0
SCLK
POL
D
IN
D
OUT
CS
MUX
A
IN
0
A
IN
1
A
IN
2
A
IN
3
A
IN
4
A
IN
5
A
IN
6
A
IN
7
A
INCOM
IDAC1
Controller
Program-
mable
Digital
Filter
2
A
AV
DD
8-Bit
IDAC
IDAC2
8-Bit
IDAC
Offset
DAC
AGND
2
A
ADS1218
2
SBAS187
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS1218Y
TQFP-48
PFB
40
C to +85
C
ADS1218Y
ADS1218Y/250
Tape and Reel, 250
"
"
"
"
"
ADS1218Y/2K
Tape and Reel, 2000
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., / 2K indicates 2000 devices per reel). Ordering 2000 pieces
of "ADS1218Y/2K" will get a single 2000-piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Texas Instruments
recommends that all integrated circuits be handled and stored using
appropriate ESD protection methods.
AV
DD
to AGND ...................................................................... 0.3V to +6V
DV
DD
to DGND ...................................................................... 0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
IN
................................................................... GND 0.5V to AV
DD
+ 0.5V
AV
DD
to DV
DD
........................................................................... 6V to +6V
AGND to DGND ................................................................. 0.3V to +0.3V
Digital Input Voltage to GND .................................... 0.3V to DV
DD
+ 0.3V
Digital Output Voltage to GND ................................. 0.3V to DV
DD
+ 0.3V
Maximum Junction Temperature ................................................... +150
C
Operating Temperature Range ......................................... 40
C to +85
C
Storage Temperature Range .......................................... 60
C to +100
C
Lead Temperature (soldering, 10s) .............................................. +300
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
PACKAGE/ORDERING INFORMATION
ELECTRICAL CHARACTERISTICS: AV
DD
= 5V
All specifications T
MIN
to T
MAX
, AV
DD
= +5V, DV
DD
= +2.7V to 5.25V, f
MOD
= 19.2kHz, f
OSC
= 2.4576MHz, PGA = 1, Buffer ON, R
DAC
= 150k
, f
DATA
= 10Hz,
V
REF
(REF IN+) (REF IN) = +2.5V, unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (A
IN
0 A
IN
7, A
INCOM
)
Analog Input Range
Buffer OFF
AGND 0.1
AV
DD
+ 0.1
V
Buffer ON
AGND + 0.05
AV
DD
1.5
V
Full-Scale Input Voltage Range
(In+) (In), See Block Diagram
V
REF
/PGA
V
Differential Input Impedance
Buffer OFF
5/PGA
M
Input Current
Buffer ON
0.5
nA
Bandwidth
Fast Settling Filter
3dB
0.469 f
DATA
Hz
Sinc
2
Filter
3dB
0.318 f
DATA
Hz
Sinc
3
Filter
3dB
0.262 f
DATA
Hz
Programmable Gain Amplifier
User Selectable Gain Ranges
1
128
Input Capacitance
9
pF
Input Leakage Current
Modulator OFF, T = 25
C
5
pA
Burnout Current Sources
2
A
OFFSET DAC
Offset DAC Range
V
REF
/(2 PGA)
V
Offset DAC Monotonicity
8
Bits
Offset DAC Gain Error
10
%
Offset DAC Gain Error Drift
1
ppm/
C
SYSTEM PERFORMANCE
Resolution
24
Bits
No Missing Codes
sinc
3
24
Bits
Integral Non-Linearity
End Point Fit
0.0015
% of FS
Offset Error
(1)
Before Calibration
7.5
ppm of FS
Offset Drift
(1)
0.02
ppm of FS/
C
Gain Error
After Calibration
0.005
%
Gain Error Drift
(1)
0.5
ppm/
C
Common-Mode Rejection
at DC
100
dB
f
CM
= 60Hz, f
DATA
= 10Hz
130
dB
f
CM
= 50Hz, f
DATA
= 50Hz
120
dB
f
CM
= 60Hz, f
DATA
= 60Hz
120
dB
Normal-Mode Rejection
f
SIG
= 50Hz, f
DATA
= 50Hz
100
dB
f
SIG
= 60Hz, f
DATA
= 60Hz
100
dB
Output Noise
See Typical Characteristics
Power-Supply Rejection
at DC, dB = 20 log(
V
OUT
/
V
DD
)
(2)
80
95
dB
3
ADS1218
SBAS187
ELECTRICAL CHARACTERISTICS: AV
DD
= 5V
(Cont.)
All specifications T
MIN
to T
MAX
, AV
DD
= +5V, DV
DD
= +2.7V to 5.25V, f
MOD
= 19.2kHz, f
OSC
= 2.4576MHz, PGA = 1, Buffer ON, R
DAC
= 150k
, f
DATA
=10Hz,
V
REF
(REF IN+) (REF IN) = +2.5V, unless otherwise specified.
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN
0
AV
DD
V
V
REF
V
REF
(REF IN+) (REF IN)
0.1
2.5
2.6
V
Common-Mode Rejection
at DC
120
dB
Common-Mode Rejection
f
VREFCM
= 60Hz, f
DATA
= 60Hz
120
dB
Bias Current
(3)
V
REF
= 2.5V
1.3
A
ON-CHIP VOLTAGE REFERENCE
Output Voltage
REF HI = 1 at 25
C
2.495
2.50
2.505
V
REF HI = 0
1.25
V
Short-Circuit Current Source
8
mA
Short-Circuit Current Sink
50
A
Short-Circuit Duration
Sink or Source
Indefinite
Drift
5
ppm/
C
Noise
BW = 0.1Hz to 100Hz
10
Vp-p
Output Impedance
Sourcing 100
A
3
Startup Time
50
s
IDAC
Full-Scale Output Current
R
DAC
= 150k
, Range = 1
0.5
mA
R
DAC
= 150k
, Range = 2
1
mA
R
DAC
= 150k
, Range = 3
2
mA
R
DAC
= 15k
, Range = 3
20
mA
Maximum Short-Circuit Current Duration
R
DAC
= 10k
Indefinite
R
DAC
= 0
10
Minutes
Monotonicity
R
DAC
= 150k
8
Bits
Compliance Voltage
0
AV
DD
1
V
Output Impedance
see Typical Characteristics
PSRR
V
OUT
= AV
DD
/2
400
ppm/V
Absolute Error
Individual IDAC
5
%
Absolute Drift
Individual IDAC
75
ppm/
C
Mismatch Error
Between IDACs, Same Range and Code
0.25
%
Mismatch Drift
Between IDACs, Same Range and Code
15
ppm/
C
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AV
DD
4.75
5.25
V
Analog Current (I
ADC
+ I
VREF
+ I
DAC
)
PDWN = 0, or SLEEP
1
nA
ADC Current (I
ADC
)
PGA = 1, Buffer OFF
175
275
A
PGA = 128, Buffer OFF
500
750
A
PGA = 1, Buffer ON
250
350
A
PGA = 128, Buffer ON
900
1375
A
V
REF
Current (I
VREF
)
250
375
A
I
DAC
Current (I
DAC
)
Excludes Load Current
480
675
A
Digital Current
Normal Mode, DV
DD
= 5V
180
275
A
SLEEP Mode, DV
DD
= 5V
150
A
Read Data Continuous Mode, DV
DD
= 5V
230
A
PDWN= LOW
1
nA
Power Dissipation
PGA = 1, Buffer OFF, REFEN = 0,
1.8
2.8
mW
I
DACS
OFF, DV
DD
= 5V
TEMPERATURE RANGE
Operating
40
+85
C
Storage
60
+100
C
NOTES: (1) Calibration can minimize these errors. (2)
V
OUT
is change in digital result. (3) 12pF switched capacitor at f
SAMP
clock frequency.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADS1218
4
SBAS187
ELECTRICAL CHARACTERISTICS: AV
DD
= 3V
All specifications T
MIN
to T
MAX
, AV
DD
= +3V, DV
DD
= +2.7V to 5.25V, f
MOD
= 19.2kHz, f
OSC
= 2.4576MHz, PGA = 1, Buffer ON, R
DAC
= 75k
, f
DATA
=10Hz,
V
REF
(REF IN+) (REF IN) = +1.25V unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (A
IN
0 A
IN
7, A
INCOM
)
Analog Input Range
Buffer OFF
AGND 0.1
AV
DD
+ 0.1
V
Buffer ON
AGND + 0.05
AV
DD
1.5
V
Full-Scale Input Voltage Range
(In+) (In) See Block Diagram
V
REF
/PGA
V
Input Impedance
Buffer OFF
5/ PGA
M
Input Current
Buffer ON
0.5
nA
Bandwidth
Fast Settling Filter
3dB
0.469 f
DATA
Hz
Sinc
2
Filter
3dB
0.318 f
DATA
Hz
Sinc
3
Filter
3dB
0.262 f
DATA
Hz
Programmable Gain Amplifier
User Selectable Gain Ranges
1
128
Input Capacitance
9
pF
Input Leakage Current
Modulator OFF, T = 25
C
5
pA
Burnout Current Sources
2
A
OFFSET DAC
Offset DAC Range
V
REF
/(2 PGA)
V
Offset DAC Monotonicity
8
Bits
Offset DAC Gain Error
10
%
Offset DAC Gain Error Drift
2
ppm/
C
SYSTEM PERFORMANCE
Resolution
24
Bits
No Missing Codes
24
Bits
Integral Non-Linearity
End Point Fit
0.0015
% of FS
Offset Error
(1)
Before Calibration
15
ppm of FS
Offset Drift
(1)
0.04
ppm of FS/
C
Gain Error
After Calibration
0.010
%
Gain Error Drift
(1)
1.0
ppm/
C
Common-Mode Rejection
at DC
100
dB
f
CM
= 60Hz, f
DATA
= 10Hz
130
dB
f
CM
= 50Hz, f
DATA
= 50Hz
120
dB
f
CM
= 60Hz, f
DATA
= 60Hz
120
dB
Normal-Mode Rejection
f
SIG
= 50Hz, f
DATA
= 50Hz
100
dB
f
SIG
= 60Hz, f
DATA
= 60Hz
100
dB
Output Noise
see Typical Characteristics
Power-Supply Rejection
at DC, dB = 20 log(
V
OUT
/
V
DD
)
(2)
75
90
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN
0
AV
DD
V
V
REF
V
REF
(REF IN+) (REF IN)
0.1
1.25
V
Common-Mode Rejection
at DC
120
dB
Common-Mode Rejection
f
VREFCM
= 60Hz, f
DATA
= 60Hz
120
dB
Bias Current
(3)
V
REF
= 1.25V
0.65
A
ON-CHIP VOLTAGE REFERENCE
Output Voltage
REF HI = 0 at 25
C
1.245
1.25
1.255
V
Short-Circuit Current Source
3
mA
Short-Circuit Current Sink
50
A
Short-Circuit Duration
Sink or Source
Indefinite
Drift
5
ppm/
C
Noise
BW = 0.1Hz to 100Hz
10
Vp-p
Output Impedance
Sourcing 100
A
3
Startup Time
50
s
IDAC
Full-Scale Output Current
R
DAC
= 75k
, Range = 1
0.5
mA
R
DAC
= 75k
, Range = 2
1
mA
R
DAC
= 75k
, Range = 3
2
mA
R
DAC
= 15k
, Range = 3
20
mA
Maximum Short-Circuit Current Duration
R
DAC
= 10k
Indefinite
R
DAC
= 0
10
Minute
Monotonicity
R
DAC
= 75k
8
Bits
Compliance Voltage
0
AV
DD
1
V
Output Impedance
see Typical Characteristics
PSRR
V
OUT
= AV
DD
/2
600
ppm/V
Absolute Error
Individual IDAC
5
%
Absolute Drift
Individual IDAC
75
ppm/
C
Mismatch Error
Between IDACs, Same Range and Code
0.25
%
Mismatch Drift
Between IDACs, Same Range and Code
15
ppm/
C
5
ADS1218
SBAS187
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AV
DD
2.7
3.3
V
Analog Current (I
ADC
+ I
VREF
+ I
DAC
)
PDWN = 0, or SLEEP
1
nA
ADC Current (I
ADC
)
PGA = 1, Buffer OFF
160
250
A
PGA = 128, Buffer OFF
450
700
A
PGA = 1, Buffer ON
230
325
A
PGA = 128, Buffer ON
850
1325
A
V
REF
Current (I
VREF
)
250
375
A
I
DAC
Current (I
DAC
)
Excludes Load Current
480
675
A
Digital Current
Normal Mode, DV
DD
= 3V
90
200
A
SLEEP Mode, DV
DD
= 3V
75
A
Read Data Continuous Mode, DV
DD
= 3V
113
A
PDWN = 0
1
nA
Power Dissipation
PGA = 1, Buffer OFF, REFEN = 0,
0.8
1.4
mW
I
DACS
OFF, DV
DD
= 3V
TEMPERATURE RANGE
Operating
40
+85
C
Storage
60
+100
C
NOTES: (1) Calibration can minimize these errors. (2)
V
OUT
is change in digital result. (3) 12pF switched capacitor at f
SAMP
clock frequency.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ELECTRICAL CHARACTERISTICS: AV
DD
= 3V
(Cont.)
All specifications T
MIN
to T
MAX
, AV
DD
= +3V, DV
DD
= +2.7V to 5.25V, f
MOD
= 19.2kHz, f
OSC
= 2.4576MHz, PGA = 1, Buffer ON, R
DAC
= 75k
, f
DATA
=10Hz,
V
REF
(REF IN+) (REF IN) = +1.25V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Input/Output
Logic Family
CMOS
Logic Level: V
IH
0.8 DV
DD
DV
DD
V
V
IL
DGND
0.2 DV
DD
V
V
OH
I
OH
= 1mA
DV
DD
0.4
V
V
OL
I
OL
= 1mA
DGND
DGND + 0.4
V
Input Leakage: I
IH
V
I
= DV
DD
10
A
I
IL
V
I
= 0
10
A
Master Clock Rate: f
OSC
(1)
1
5
MHz
Master Clock Period: t
OSC
(1)
1/f
OSC
200
1000
ns
NOTE: (1) For FLASH E/W operations, the SPEED bit in the SETUP register must be set appropriately and the device operating frequency must be:
2.3MHz < F
OSC
< 4.13MHz.
DIGITAL CHARACTERISTICS: T
MIN
to T
MAX
, DV
DD
= 2.7V to 5.25V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Current
Page Write
DV
DD
= 5V, During WR2F Command
6.5
mA
DV
DD
= 3V, During WR2F Command
3.75
mA
Page Read
DV
DD
= 5V, During RF2R Command
4.0
mA
DV
DD
= 3V, During RF2R Command
1.2
mA
Endurance
100,000
E/W Cycles
Data Retention
at 25
C
100
Years
DV
DD
for Erase/Write
2.7
5.25
V
FLASH CHARACTERISTICS: T
MIN
to T
MAX
, DV
DD
= 2.7V to 5.25V, unless otherwise specified.
ADS1218
6
SBAS187
PIN CONFIGURATION (TQFP-48)
PIN
NUMBER
NAME
DESCRIPTION
1
AV
DD
Analog Power Supply
2
AGND
Analog Ground
3
A
IN
0
Analog Input 0
4
A
IN
1
Analog Input 1
5
A
IN
2
Analog Input 2
6
A
IN
3
Analog Input 3
7
A
IN
4
Analog Input 4
8
A
IN
5
Analog Input 5
9
A
IN
6
Analog Input 6
10
A
IN
7
Analog Input 7
11
A
INCOM
Analog Input Common
12
AGND
Analog Ground
13
AV
DD
Analog Power Supply
14
V
RCAP
V
REF
Bypass CAP
15
IDAC1
Current DAC1 Output
16
IDAC2
Current DAC2 Output
17
R
DAC
Current DAC Resistor
18
WREN
Active High, FLASH Write Enable
19-22
DGND
Digital Ground
23
BUFEN
Buffer Enable
PIN DESCRIPTIONS
PIN
NUMBER
NAME
DESCRIPTION
24
23
22
21
20
19
18
17
16
15
14
13
RESET
BUFEN
DGND
DGND
DGND
DGND
WREN
R
DAC
IDAC2
IDAC1
V
RCAP
AV
DD
D
OUT
D
IN
SCLK
CS
DRDY
DV
DD
DGND
DSYNC
POL
PDWN
X
OUT
X
IN
AV
DD
AGND
A
IN
0
A
IN
1
A
IN
2
A
IN
3
A
IN
4
A
IN
5
A
IN
6
A
IN
7
A
INCOM
AGND
37
38
39
40
41
42
43
44
45
46
47
48
D0
D1
D2
D3
D4
D5
D6
D7
AGND
V
REFOUT
V
REF+
V
REF
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
25
12
ADS1218
24
RESET
Active LOW, resets the entire chip.
25
X
IN
Clock Input
26
X
OUT
Clock Output, used with crystal or resonator.
27
PDWN
Active LOW. Power Down. The power down
function shuts down the analog and digital
circuits.
28
POL
Serial Clock Polarity
29
DSYNC
Active LOW, Synchronization Control
30
DGND
Digital Ground
31
DV
DD
Digital Power Supply
32
DRDY
Active LOW, Data Ready
33
CS
Active LOW, Chip Select
34
SCLK
Serial Clock, Schmitt Trigger
35
D
IN
Serial Data Input, Schmitt Trigger
36
D
OUT
Serial Data Output
37-44
D0-D7
Digital I/O 0-7
45
AGND
Analog Ground
46
V
REFOUT
Voltage Reference Output
47
V
REF+
Positive Differential Reference Input
48
V
REF
Negative Differential Reference Input
7
ADS1218
SBAS187
SPEC
DESCRIPTION
MIN
MAX
UNITS
t
1
SCLK Period
4
t
OSC
Periods
3
DRDY Periods
t
2
SCLK Pulse Width, HIGH and LOW
200
ns
t
3
CS LOW to first SCLK Edge; Setup Time
0
ns
t
4
D
IN
Valid to SCLK Edge; Setup Time
50
ns
t
5
Valid D
IN
to SCLK Edge; Hold Time
50
ns
t
6
Delay between last SCLK edge for D
IN
and first SCLK
edge for D
OUT
:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM
50
t
OSC
Periods
CSREG, CSRAMX, CSRAM
200
t
OSC
Periods
CHKARAM, CHKARAMX
1100
t
OSC
Periods
t
7
(1)
SCLK Edge to Valid New D
OUT
50
ns
t
8
(1)
SCLK Edge to D
OUT
, Hold Time
0
ns
t
9
Last SCLK Edge to D
OUT
Tri-State
6
10
t
OSC
Periods
NOTE: D
OUT
goes tri-state immediately when CS goes HIGH.
t
10
CS LOW time after final SCLK edge
0
ns
t
11
Final SCLK edge of one op code until first edge SCLK
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, SLEEP,
RDATA, RDATAC, STOPC
4
t
OSC
Periods
DSYNC, RESET
16
t
OSC
Periods
CSFL
33,000
t
OSC
Periods
CREG, CRAM
220
t
OSC
Periods
RF2R
1090
t
OSC
Periods
CREGA
1600
t
OSC
Periods
WR2F
76,850 (SPEED = 0)
t
OSC
Periods
101,050 (SPEED = 1)
4
t
OSC
Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
7
DRDY Periods
SELFCAL
14
DRDY Periods
RESET (Command, SCLK, or Pin)
16
t
OSC
Periods
t
12
SCLK Reset, First HIGH Pulse
300
500
t
OSC
Periods
t
13
SCLK Reset, LOW Pulse
5
t
OSC
Periods
t
14
SCLK Reset, Second HIGH Pulse
550
750
t
OSC
Periods
t
15
SCLK Reset, Third HIGH Pulse
1050
1250
t
OSC
Periods
t
16
Pulse Width
4
t
OSC
Periods
t
17
DOR Data Not Valid
4
t
OSC
Periods
NOTE: (1) Load = 20pF
10k
to DGND.
TIMING SPECIFICATIONS
TIMING SPECIFICATION TABLES
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit Order = 0.
t
7
MSB
(1)
LSB
(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL = 1)
SCLK Reset Waveform
DDR Update Timing
t
12
t
14
t
15
t
13
t
13
SCLK
t
17
DRDY
t
16
RESET, DSYNC, PDWN
ADS1218
Resets On
Falling Edge
ADS1218
8
SBAS187
TYPICAL CHARACTERISTICS
AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k
, f
DATA
= 10Hz, V
REF
(REF IN+) (REF IN) = +2.5V, unless otherwise specified.
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
Decimation Ratio =
f
MOD
f
DATA
0
500
1000
1500
2000
PGA4
ENOB (rms)
PGA1
PGA2
PGA16
PGA8
PGA32
PGA64
PGA128
Sinc
3
Filter, V
REF
= 1.25V, Buffer OFF
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
0
500
1000
1500
2000
ENOB (rms)
PGA4
PGA8
PGA1 PGA2
PGA16
PGA32
PGA64
PGA128
Decimation Ratio =
f
MOD
f
DATA
Sinc
3
Filter, V
REF
= 1.25V, Buffer ON
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
Decimation Ratio =
f
MOD
f
DATA
0
500
1000
1500
2000
PGA4
ENOB (rms)
PGA1
PGA2
PGA16
PGA8
PGA32
PGA64
PGA128
Sinc
2
Filter
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
Decimation Ratio =
f
MOD
f
DATA
0
500
1000
1500
2000
PGA4
ENOB (rms)
PGA1
PGA2
PGA16
PGA8
PGA32
PGA64
PGA128
Sinc
3
Filter
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
0
500
1000
1500
2000
ENOB (rms)
PGA4
PGA8
PGA1 PGA2
PGA16
PGA32
PGA64
PGA128
Decimation Ratio =
f
MOD
f
DATA
Sinc
3
Filter, Buffer ON
22
21
20
19
18
17
16
15
14
13
12
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
0
500
1000
1500
2000
ENOB (rms)
1500
Decimation Ratio =
f
MOD
f
DATA
Fast Settling Filter
9
ADS1218
SBAS187
TYPICAL CHARACTERISTICS
(Cont.)
AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k
, f
DATA
= 10Hz, V
REF
(REF IN+) (REF IN) = +2.5V, unless otherwise specified.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
NOISE vs INPUT SIGNAL
V
IN
(V)
2.5
1.5
0.5
0.5
1.5
2.5
Noise (rms, ppm of FS)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
CMRR vs FREQUENCY
Frequency of CM Signal (Hz)
1
10
100
1k
10k
100k
CMRR (dB)
120
110
100
90
80
70
60
50
40
30
20
10
0
PSRR vs FREQUENCY
Frequency of Power Supply (Hz)
1
10
1k
100
10k
100k
PSRR (dB)
50
0
50
100
150
200
OFFSET vs TEMPERATURE
Offset (ppm of FS)
PGA1
PGA128
PGA64
Temperature (
C)
50
30
10
10
30
50
70
90
PGA16
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
GAIN vs TEMPERATURE
Temperature (
C)
50
30
10
10
30
50
70
90
Gain (Normalized)
10
8
6
4
2
0
2
4
6
8
10
INTEGRAL NON-LINEARITY vs INPUT SIGNAL
V
IN
(V)
2.5
2
1
0.5
1.5
0
0.5
1
1.5
2
2.5
INL (ppm of FS)
40
C
+25
C
+85
C
ADS1218
10
SBAS187
TYPICAL CHARACTERISTICS
(Cont.)
AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k
, f
DATA
= 10Hz, V
REF
(REF IN+) (REF IN) = +2.5V, unless otherwise specified.
250
200
150
100
50
0
CURRENT vs TEMPERATURE
Current (
A)
I
ANALOG
I
ANALOG
I
DIGITAL
I
DIGITAL
Temperature (
C)
50
30
10
10
30
50
70
90
900
800
700
600
500
400
300
200
100
0
ADC CURRENT vs PGA
PGA Setting
0
1
8
2
4
32
16
128
64
I
ADC
(
A)
AV
DD
= 5V, Buffer = ON
AV
DD
= 3V, Buffer = ON
Buffer = OFF
Buffer = OFF
400
350
300
250
200
150
100
50
0
DIGITAL CURRENT
V
DD
(V)
3.0
4.0
5.0
Current (
A)
Normal
f
OSC
= 4.91MHz
SLEEP
f
OSC
= 4.91MHz
SPEED = 0
SLEEP
f
OSC
= 2.45MHz
Power
Down
Normal
f
OSC
= 2.45MHz
4500
4000
3500
3000
2500
2000
1500
1000
500
0
HISTOGRAM OF OUTPUT DATA
ppm of FS
2
Number of Occurrences
1.5
1
0.5
0
0.5
1
1.5
2
2.55
2.50
2.45
V
REFOUT
vs LOAD CURRENT
V
REFOUT
Current Load (mA)
0.5
0
0.5
1.0
1.5
2.0
2.5
V
REFOUT
(V)
200
170
140
110
80
50
20
10
40
70
100
OFFSET DAC - OFFSET vs TEMPERATURE
Offset (ppm of FSR)
Temperature (
C)
50
30
10
10
30
50
70
90
11
ADS1218
SBAS187
TYPICAL CHARACTERISTICS
(Cont.)
AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k
, f
DATA
= 10Hz, V
REF
(REF IN+) (REF IN) = +2.5V, unless otherwise specified.
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
OFFSET DAC - GAIN vs TEMPERATURE
Normalized Gain
Temperature (
C)
50
30
10
10
30
50
70
90
1.000
1.000
0.999
0.999
0.998
IDAC
R
OUT
vs V
OUT
V
DD
V
OUT
(V)
0
1
2
3
4
5
I
OUT
(Normalized)
+85
C
40
C
+25
C
1.01
1.005
1
0.995
0.99
0.985
IDAC NORMALIZED vs TEMPERATURE
I
OUT
(Normalized)
Temperature (
C)
50
30
10
10
30
50
70
90
3000
2000
1000
0
1000
2000
3000
4000
5000
6000
IDAC MATCHING vs TEMPERATURE
IDAC Match (ppm)
Temperature (
C)
50
30
10
10
30
50
70
90
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
IDAC DIFFERENTIAL NON-LINEARITY
RANGE = 1, R
DAC
= 150k
, V
REF
= 2.5V
IDAC Code
0
255
32
64
96
128
160
192
224
DNL (LSB)
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
IDAC INTEGRAL NON-LINEARITY
RANGE = 1, R
DAC
= 150k
, V
REF
= 2.5V
IDAC Code
0
255
32
64
96
128
160
192
224
INL (LSB)
ADS1218
12
SBAS187
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of
differential inputs to be selected on any of the input chan-
nels, as shown in Figure 1. For example, if channel 1 is
selected as the positive differential input channel, any other
channel can be selected as the negative differential input
channel. With this method, it is possible to have up to eight
fully differential input channels.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the input pins.
BURNOUT CURRENT SOURCES
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2
A of current.
The current source on the negative input channel sinks ap-
proximately 2
A. This allows for the detection of an open
circuit (full-scale reading) or short circuit (0V differential
reading) on the selected input differential pair.
INPUT BUFFER
The input impedance of the ADS1218 without the buffer
is 5M
/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the BUFEN pin
with the state of the BUFFER bit in the ACR register.
IDAC1 AND IDAC2
The ADS1218 has two 8-bit current output DACs that can be
controlled independently. The output current is set with
R
DAC
, the range select bits in the ACR register, and the 8-bit
digital value in the IDAC register. The output current
= V
REF
/(8 R
DAC
)(2
RANGE1
)(DAC CODE). With V
REFOUT
= 2.5V and R
DAC
= 150k
to AGND the full-scale output
can be selected to be 0.5, 1, or 2mA. The compliance voltage
range is 0 to within 1V of AV
DD
. When the internal voltage
reference of the ADS1218 is used, it is the reference for the
IDAC. An external reference may be used for the IDACs by
disabling the internal reference and tying the external refer-
ence input to the V
REFOUT
pin.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually
improve the effective resolution of the A/D converter. For
instance, with a PGA of 1 on a 5V full-scale range, the A/D
converter can resolve to 1
V. With a PGA of 128, on a 40mV
full-scale range, the A/D converter can resolve to 75nV. With
a PGA of 1 on a 5V full-scale range, it would require a 26-bit
A/D converter to resolve 75nV.
PGA OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign
and the seven LSBs provide the magnitude of the offset. Using
the ODAC register does not reduce the performance of the
A/D converter.
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (f
MOD
) that is derived from
the external clock (f
OSC
). The frequency division is deter-
mined by the SPEED bit in the SETUP register.
A
IN
3
A
IN
4
A
IN
5
A
IN
6
A
IN
0
A
IN
1
A
IN
2
A
IN
7
A
INCOM
Burnout Current Source On
Burnout Current Source On
IDAC1
AGND
AV
DD
FIGURE 1. Input Multiplexer Configuration.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to
all 1s, the diode is connected to the input of the A/D
converter. All other channels are open. The anode of the
diode is connected to the positive input of the A/D converter,
and the cathode of the diode is connected to negative input
of the A/D converter. The output of IDAC1 is connected to
the anode to bias the diode and the cathode of the diode is
also connected to ground to complete the circuit.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode.
SPEED BIT
f
MOD
0
f
OSC
/ 128
1
f
OSC
/ 256
13
ADS1218
SBAS187
CALIBRATION
The offset and gain errors in the ADS1218, or the complete
system, can be reduced with calibration. Internal calibration of
the ADS1218 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven t
DATA
periods to complete. Therefore, it takes 14 t
DATA
periods to complete both an offset and gain calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
"zero" differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive "full-scale" differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven t
DATA
periods to complete.
Calibration should be performed after power on, a change in
temperature, a change in decimation ratio, or a change in the
PGA. Calibration will remove the offset in the ODAC register.
Therefore, changes to the ODAC register must be done after
calibration.
At the completion of calibration, the DRDY signal will go
LOW to indicate that calibration is complete and valid data is
available.
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc
2
, or sinc
3
filter, as shown in Figure 2. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the fast
FIGURE 3. Filter Frequency Responses.
FIGURE 2. Filter Step Responses.
SETTLING TIME
FILTER
(Conversion Cycles)
Sinc
3
3
(1)
Sinc
2
2
(1)
Fast
1
(1)
NOTE: (1) With Synchronized Channel Changes.
CONVERSION CYCLE
1
2
3
4+
Discard
Fast
Sinc
2
Sinc
3
AUTO MODE FILTER SELECTION
FILTER SETTLING TIME
Adjustable Digital Filter
Data Out
Modulator
Output
Fast Settling
Sinc
2
Sinc
3
SINC
3
FILTER RESPONSE
(3dB = 0.262 f
DATA
= 15.76Hz)
Frequency (Hz)
0
20
40
60
80
100
120
0
30
120
60
90
150
180
210
240
270
300
Gain (dB)
SINC
2
FILTER RESPONSE
(3dB = 0.318 f
DATA
= 19.11Hz)
Frequency (Hz)
0
20
40
60
80
100
120
0
30
120
60
90
150
180
210
240
270
300
Gain (dB)
FAST SETTLING FILTER RESPONSE
(3dB = 0.469 f
DATA
= 28.125Hz)
Frequency (Hz)
0
20
40
60
80
100
120
0
NOTE: f
DATA
= 60Hz.
30
120
60
90
150
180
210
240
270
300
Gain (dB)
settling filter for the next two conversions, the first of which
should be discarded. It will then use the sinc
2
followed by the
sinc
3
filter to improve noise performance. This combines the
low-noise advantage of the sinc
3
filter with the quick response
of the fast settling time filter. The frequency response of each
filter is shown in Figure 3.
ADS1218
14
SBAS187
VOLTAGE REFERENCE
The voltage reference used for the ADS1218 can either be
internal or external. The power-up configuration for the
voltage reference is 2.5V internal. The selection for the
voltage reference is made through the status configuration
register.
The internal voltage reference is selectable as either 1.25V
or 2.5V (AV
DD
= 5V only). The V
REFOUT
pin should have a
0.1
F capacitor to AGND.
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +V
REF
and V
REF
. The absolute voltage on either pin (+V
REF
and
V
REF
) can range from AGND to AV
DD
, however, the
differential voltage must not exceed 2.5V. The differential
voltage reference provides easy means of performing
ratiometric measurement.
V
RCAP
PIN
This pin provides a bypass cap for noise filtering on internal
V
REF
circuitry only. The recommended capacitor is a 0.001
F
ceramic cap. If an external V
REF
is used, this pin can be left
unconnected.
CLOCK GENERATOR
The clock source for the ADS1218 can be provided from a
crystal, ceramic resonator, oscillator, or external clock. When
the clock source is a crystal or ceramic resonator, external
capacitors must be provided to ensure start-up and a stable
clock frequency. This is shown in Figure 4 and Table I.
DIGITAL I/O INTERFACE
The ADS1218 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as
inputs. All of the digital I/O pins are individually configurable
as inputs or outputs. They are configured through the DIR
control register. The DIR register defines whether the pin is an
input or output, and the DIO register defines the state of the
digital output. When the digital I/O are configured as inputs,
DIO is used to read the state of the pin.
SERIAL INTERFACE
The serial interface is standard four-wire SPI compatible (D
IN
,
D
OUT
, SCLK, and CS). The ADS1218 also offers the flexibil-
ity to select the polarity of the serial clock through the POL
pin. The serial interface can be clocked up to f
OSC
/4. If CS
goes HIGH, the serial interface is reset. When CS goes LOW,
a new command is expected.
The serial interface operates independently of DRDY. DRDY
is used to indicate availability of data in the DOR. In order to
ensure the validity of the data being read, DOR timing
requirements must be met.
DSYNC OPERATION
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the DSYNC pin or the DSYNC
command. When the DSYNC pin is used, the filter counter
is reset on the falling edge of DSYNC. The modulator is held
in reset until DSYNC is taken HIGH. Synchronization
occurs on the next rising edge of the system clock after
DSYNC is taken HIGH.
When the DSYNC command is sent, the filter counter is
reset after the last SCLK on the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command.
POWER-UP--SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally. The POR issues the RESET command as described
below.
RESET
There are three methods of reset. The RESET pin, the
RESET command, and the SCLK Reset pattern. They all
perform the same function. After a reset, the FLASH data
values from Page 0 are loaded into RAM, subsequently data
values from Bank 0 of RAM are loaded into the configura-
tion registers.
FIGURE 4. Crystal or Ceramic Resonator Connection.
CLOCK
PART
SOURCE
FREQUENCY
C
1
C
2
NUMBER
Crystal
2.4576
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSL 4.91
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSD 4.91
Crystal
4.9152
0-20pF
0-20pF
CTS, MP 042 4M9182
TABLE I. Typical Clock Sources.
C
1
Crystal
or
Ceramic Resonator
X
IN
X
OUT
C
2
15
ADS1218
SBAS187
MEMORY
Three types of memory are used on the ADS1218: registers,
RAM, and FLASH. 16 registers directly control the various
functions (PGA, DAC value, Decimation Ratio, etc.) and can
be directly read or written to. Collectively, the registers contain
all the information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio, etc.
Additional registers, such as conversion data, are accessed
through dedicated instructions.
The on-chip FLASH can be used to store non-volatile data. The
FLASH data is separate from the configuration registers and
therefore can be used for any purpose, in addition to device
configuration. The FLASH page data is read and written in 128
byte blocks through the RAM banks, i.e. all RAM banks map
to a single page of FLASH, as shown in Figure 5.
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
RAM
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers,
i.e.: the RAM can be used as general-purpose RAM.
The ADS1218 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations--one per input channel. In order
to facilitate this type of usage, eight separate register banks are
available. Therefore, each configuration could be written once
and recalled as needed without having to serially retransmit all
the configuration data. Checksum commands are also in-
cluded, which can be used to verify the integrity of RAM.
The RAM provides eight "banks", with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00
H
SETUP
ID
ID
ID
SPEED
REF EN
REF HI
BUF EN
BIT ORDER
01
H
MUX
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
02
H
ACR
BOCS
IDAC2R1
IDAC2R0
IDAC1R1
IDAC1R0
PGA2
PGA1
PGA0
03
H
IDAC1
IDAC1_7
IDAC1_6
IDAC1_5
IDAC1_4
IDAC1_3
IDAC1_2
IDAC1_1
IDAC1_0
04
H
IDAC2
IDAC2_7
IDAC2_6
IDAC2_5
IDAC2_4
IDAC2_3
IDAC2_2
IDAC2_1
IDAC2_0
05
H
ODAC
SIGN
OSET_6
OSET_5
OSET_4
OSET_3
OSET_2
OSET_1
OSET_0
06
H
DIO
DIO_7
DIO_6
DIO_5
DIO_4
DIO_3
DIO_2
DIO_1
DIO_0
07
H
DIR
DIR_7
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
08
H
DEC0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
09
H
M/DEC1
DRDY
U/B
SMODE1
SMODE0
WREN
DEC10
DEC09
DEC08
0A
H
OCR0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
0B
H
OCR1
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
0C
H
OCR2
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
0D
H
FSR0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
0E
H
FSR1
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
0F
H
FSR2
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
TABLE II. Registers.
FIGURE 5. Memory Organization.
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
Configuration
Register Bank
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128 Bytes
Bank 2
16 bytes
Bank 7
16 bytes
Bank 0
16 bytes
FLASH
4k Bytes
Page 0
128 bytes
Page 31
128 bytes
ADS1218
16
SBAS187
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively without
having to address each bank individually. For example, if
you were currently accessing bank 0 at offset 0xF (the last
location of bank 0), the next access would be bank 1 and
offset 0x0. Any access after bank 7 and offset 0xF will wrap
around to bank 0 and Offset 0x0.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of bank
and offset addressing. Looking at linear and bank addressing
syntax, we have the following comparison: in the linear
memory map, the address 0x14 is equivalent to bank 1 and
offset 0x4. Simply stated, the most significant four bits
represent the bank, and the least significant four bits repre-
sent the offset. The offset is equivalent to the register
address for that bank of memory.
FLASH
Reads and Writes to FLASH occur on a Page basis.
Therefore, the entire contents of RAM is used for both
Read and Write operations. The FLASH is independent of
the Registers, i.e., the FLASH can be used as general-
purpose FLASH.
Upon power-up or reset, the contents of FLASH Page 0 are
loaded into RAM subsequently the contents of RAM Bank
0 are loaded into the configuration register. Therefore, the
user can customize the power-up configuration for the de-
vice. Care should be taken to ensure that data for FLASH
Page 0 is written correctly, in order to prevent unexpected
operation upon power-up.
The ADS1218 supports any combination of eight analog
inputs and the FLASH memory supports up to 32 unique Page
configurations. With this flexibility, the device could support
32 unique configurations for each of the eight analog input
channels. For instance, the on-chip temperature sensor could
be used to monitor temperature then different calibration
coefficients could be recalled for each of the eight analog
input channels based on the change in temperature. This
would enable the user to recall calibration coefficients for
every 4
C change in temperature over the industrial tempera-
ture range which could be used to correct for drift errors.
Checksum commands are also included, which can be used to
verify the integrity of FLASH.
The following two commands can be used to manipulate the
FLASH. First, the contents of FLASH can be written to with
the WR2F (write RAM to FLASH) command. This com-
mand first erases the designated FLASH page and then
writes the entire content of RAM (all banks) into the desig-
nated FLASH page. Second, the contents of FLASH can be
read with the RF2R (read FLASH to RAM) command. This
command reads the designated FLASH page into the entire
contents of RAM (all banks). In order to ensure maximum
endurance and data retention, the SPEED bit in the SETUP
register must be set for the appropriate f
OSC
frequency.
Writing to or erasing FLASH can be disabled either through
the WREN pin or the WREN register bit. If the WREN pin
is LOW OR the WREN bit is cleared, then the WR2F
command has no effect. This protects the integrity of the
FLASH data from being inadvertently corrupted.
Accessing the FLASH data either through read, write, or
erase may effect the accuracy of the conversion result.
Therefore, the conversion result should be discarded when
accesses to FLASH are done.
17
ADS1218
SBAS187
ACR (Address 02
H
) Analog Control Register
Reset Value = 00
H
bit 7
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
IDAC Current =
bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for
IDAC2
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for
IDAC1
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Ampli-
fier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
IDAC1 (Address 03
H
) Current DAC 1
Reset Value = 00
H
The DAC code bits set the output of DAC1 from 0 to full-
scale. The value of the full-scale current is set by this Byte,
V
REF
, R
DAC
, and the DAC1 range bits in the ACR register.
IDAC2 (Address 04
H
) Current DAC 2
Reset Value = 00
H
The DAC code bits set the output of DAC2 from 0 to full-
scale. The value of the full-scale current is set by this Byte,
V
REF
, R
DAC
, and the DAC2 range bits in the ACR register.
DETAILED REGISTER DEFINITIONS
SETUP (Address 00
H
) Setup Register
Reset Value = iii01110
bit 7-5 Factory Programmed Bits
bit 4
SPEED: FLASH Access Clock Speed
0 : 2.30MHz > f
OSC
> 3.12MHz (default)
1 : 3.12MHz > f
OSC
> 4.13MHz
bit 3
REF EN: Internal Voltage Reference Enable
0 = Internal Voltage Reference Disabled
1 = Internal Voltage Reference Enabled (default)
bit 2
REF HI: Internal Reference Voltage Select
0 = Internal Reference Voltage = 1.25V
1 = Internal Reference Voltage = 2.5V (default)
bit 1
BUF EN: Buffer Enable
0 = Buffer Disabled
1 = Buffer Enabled (default)
bit 0
BIT ORDER: Set Order Bits are Transmitted
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted into the part most significant
bit first. Data is always shifted out of the part most
significant byte first. This configuration bit only
controls the bit order within the byte of data that is
shifted out.
MUX (Address 01
H
) Multiplexer Control Register
Reset Value = 01
H
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1's)
1111 = Temperature Sensor Diode Anode
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Chan-
nel Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1's)
1111 = Temperature Sensor Diode Cathode Analog GND
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ID
ID
ID
SPEED
REF EN
REF HI
BUF EN BIT ORDER
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BOCS
IDAC2R1 IDAC2R0 IDAC1R1
IDAC1R0
PGA2
PGA1
PGA0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IDAC1_7
IDAC1_6
IDAC1_5 IDAC1_4
IDAC1_3 IDAC1_2
IDAC1_1
IDAC1_0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IDAC2_7
IDAC2_6
IDAC2_5 IDAC2_4
IDAC1_3 IDAC1_2
IDAC1_1
IDAC1_0
V
R
DAC Code
REF
DAC
RANGE
8
2
1
(
)
(
)
-
ADS1218
18
SBAS187
ODAC (Address 05
H
) Offset DAC Setting
Reset Value = 00
H
bit 7
Offset Sign
0 = Positive
1 = Negative
bit 6-0 Offset =
NOTE: Calibration will cancel the value in the ODAC register. Therefore, writing
to the ODAC register should be done after calibration.
DIO (Address 06
H
) Digital I/O
Reset Value = 00
H
A value written to this register will appear on the digital
I/O pins if the pin is configured as an output in the DIR
register. Reading this register will return the value of the
digital I/O pins.
DIR (Address 07
H
) Direction control for digital I/O
Reset Value = FF
H
Each bit controls whether the Digital I/O pin is an output
(= 0) or input (= 1). The default power-up state is as inputs.
DEC0 (Address 08
H
) Decimation Register
(Least Significant 8 bits)
Reset Value = 80
H
The decimation value is defined with 11 bits for a range of
20 to 2047. This register is the least significant 8 bits. The
3 most significant bits are contained in the M/DEC1 register.
The default data rate is 10Hz with a 2.4576MHz crystal.
M/DEC1 (Address 09
H
) Mode and Decimation Register
Reset Value = 07
H
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
bit 5-4 SMODE1: SMODE0: Settling Mode
00 = Auto (default)
01 = Fast Settling filter
10 = Sinc
2
filter
11 = Sinc
3
Flash filter
bit 3
WREN: Write Enable
0 = Flash Writing Disabled (default)
1 = Flash Writing Enabled
This bit is AND'd with the WREN pin to enable or
disable Flash Writing and Erasing
bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of
the Decimation Value
OCR0 (Address 0A
H
) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00
H
OCR1 (Address 0B
H
) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00
H
OCR2 (Address 0C
H
) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00
H
FSR0 (Address 0D
H
) Full-Scale Register
(Least Significant Byte)
Reset Value =
24
H
FSR1 (Address 0E
H
) Full-Scale Register
(Middle Byte)
Reset Value = 90
H
FSR2 (Address 0F
H
) Full-Scale Register
(Most Significant Byte)
Reset Value = 67
H
V
PGA
Code
REF
2
127
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SMODE1 SMODE0
WREN
DEC10
DEC09
DEC08
U/B
ANALOG INPUT
DIGITAL OUTPUT
+FSR
0x7FFFFF
0
Zero
0x000000
FSR
0x800000
+FSR
0xFFFFFF
1
Zero
0x000000
FSR
0x000000
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR011
FSR10
FSR09
FSR08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR019
FSR18
FSR17
FSR16
19
ADS1218
SBAS187
RDATA
Read Data
Description: Read a single data value from the Data Output
Register (DOR) which is the most recent conversion result.
This is a 24-bit value.
Operands:
None
Bytes:
1
Encoding:
0000 0001
Data Transfer Sequence:
COMMANDS
DESCRIPTION
COMMAND BYTE
2ND COMMAND BYTE
RDATA
Read Data
0000 0001 (01
H
)
--
RDATAC
Read Data Continuously
0000 0011 (03
H
)
--
STOPC
Stop Read Data Continuously
0000 1111 (0F
H
)
--
RREG
Read from REG Bank "rrrr"
0001 r r r r (1x
H
)
xxxx_nnnn (# of reg-1)
RRAM
Read from RAM Bank "aaa"
0010 0aaa (2x
H
)
xnnn_nnnn (# of bytes-1)
CREG
Copy REGs to RAM Bank "aaa"
0100 0aaa (4x
H
)
--
CREGA
Copy REGS to all RAM Banks
0100 1000 (48
H
)
--
WREG
Write to REG "rrrr"
0101 r r r r (5x
H
)
xxxx_nnnn (# of reg-1)
WRAM
Write to RAM Bank "aaa"
0110 0aaa (6x
H
)
xnnn_nnnn (# of bytes-1)
RF2R
Read FLASH page to RAM
100f f f f f (8, 9x
H
)
--
WR2F
Write RAM to FLASH page
101f f f f f (A, Bx
H
)
--
CRAM
Copy RAM Bank "aaa" to REG
1100 0aaa (Cx
H
)
--
CSRAMX
Calc RAM Bank "aaa" Checksum
1101 0aaa (Dx
H
)
--
CSARAMX
Calc all RAM Bank Checksum
1101 1000 (D8
H
)
--
CSREG
Calc REG Checksum
1101 1111 (DF
H
)
--
CSRAM
Calc RAM Bank "aaa" Checksum
1110 0aaa (Ex
H
)
--
CSARAM
Calc all RAM Banks Checksum
1110 1000 (E8
H
)
--
CSFL
Calc FLASH Checksum
1110 1100 (EC
H
)
--
SELFCAL
Self Cal Offset and Gain
1111 0000 (F0
H
)
--
SELFOCAL
Self Cal Offset
1111 0001 (F1
H
)
--
SELFGCAL
Self Cal Gain
1111 0010 (F2
H
)
--
SYSOCAL
Sys Cal Offset
1111 0011 (F3
H
)
--
SYSGCAL
Sys Cal Gain
1111 0100 (F4
H
)
--
DSYNC
Sync DRDY
1111 1100 (FC
H
)
--
SLEEP
Put in SLEEP Mode
1111 1101 (FD
H
)
--
RESET
Reset to Power-Up Values
1111 1110 (FE
H
)
--
NOTE: (1) The data received by the A/D is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATAC
Read Data Continuous
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands:
None
Bytes:
1
Encoding:
0000 0011
Data Transfer Sequence:
Command terminated when "uuuu uuuu" equals STOPC
or RESET.
COMMAND DEFINITIONS
The commands listed below control the operation of the
ADS1218. Some of the commands are stand-alone com-
mands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four f
OSC
cycles before the data is ready (e.g., RDATA).
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don't care
a = RAM bank address (0 to 7)
f = FLASH page address (0 to 31)
D
IN
0000 0001
(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
D
OUT
NOTE: (1) For wait time, refer to timing specification.
xxxx xxxx
(1)
MSB
Mid-Byte
LSB
D
IN
0000 0011
(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
D
OUT
xxxx xxxx
(1)
MSB
Mid-Byte
LSB
D
IN
xxxx
xxxx
D
OUT
MSB
Mid-Byte
xxxx
LSB
DRDY
NOTE: (1) For wait time, refer to timing specification.
ADS1218
20
SBAS187
STOPC
Stop Continuous
Description: Ends the continuous data output mode.
Operands:
None
Bytes:
1
Encoding:
0000 1111
Data Transfer Sequence:
RREG
Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte.
If the count exceeds the remaining registers, the addresses will
wrap back to the beginning.
Operands:
r, n
Bytes:
2
Encoding:
0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01
H
(MUX)
RRAM
Read from RAM
Description: Up to 128 bytes can be read from RAM starting
at the bank specified in the op code. All reads start at the
address for the beginning of the RAM bank. The number of
bytes to read will be one plus the value of the second byte.
Operands:
a, n
Bytes:
2
Encoding:
0010 0aaa xnnn nnnn
Data Transfer Sequence:
Read Two RAM Locations Starting from 20
H
CREG
Copy Registers to RAM Bank
Description: Copy the 16 control registers to the RAM bank
specified in the op code. Refer to timing specifications for
command execution time.
Operands:
a
Bytes:
1
Encoding:
0100 0aaa
Data Transfer Sequence:
Copy Register Values to RAM Bank 3
CREGA
Copy Registers to All RAM Banks
Description: Duplicate the 16 control registers to all the
RAM banks. Refer to timing specifications for command
execution time.
Operands:
None
Bytes:
1
Encoding:
0100 1000
Data Transfer Sequence:
WREG
Write to Register
Description: Write to the registers starting with the register
specified as part of the instruction. The number of registers
that will be written is one plus the value of the second byte.
Operands:
r, n
Bytes:
2
Encoding:
0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 06
H
(DIO)
D
IN
0000 1111
D
OUT
xxxx xxxx
D
IN
0001 0001
0000 0001
xxxx xxxx
xxxx xxxx
D
OUT
xxxx xxxx
xxxx xxxx
MUX
ACR
(1)
(1)
NOTE: (1) For wait time, refer to timing specification.
D
IN
0010 0010
x000 0001
xxxx xxxx
xxxx xxxx
D
OUT
xxxx xxxx
xxxx xxxx
RAM Data
20
H
RAM Data
21
H
(1)
(1)
NOTE: (1) For wait time, refer to timing specification.
D
IN
0100 0011
D
OUT
xxxx xxxx
D
IN
0100 1000
D
OUT
xxxx xxxx
0101 0110
xxxx 0001
Data for DIO
Data for DIR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
D
IN
D
OUT
21
ADS1218
SBAS187
WRAM
Write to RAM
Description: Write up to 128 RAM locations starting at the
beginning of the RAM bank specified as part of the instruc-
tion. The number of bytes written is RAM is one plus the value
of the second byte.
Operands:
a, n
Bytes:
2
Encoding:
0110 0aaa xnnn nnnn
Data Transfer Sequence:
Write to Two RAM Locations starting from 10
H
CRAM
Copy RAM Bank to Registers
Description: Copy the selected RAM Bank to the Configura-
tion Registers. This will overwrite all of the registers with the
data from the RAM bank.
Operands:
a
Bytes:
1
Encoding:
1100 0aaa
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
CSRAMX
Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. The ID, DRDY and DIO bits are
masked so they are not included in the checksum.
Operands:
a
Bytes:
1
Encoding:
1101 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
CSARAMX Calculate the Checksum
for all RAM Banks
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands:
None
Bytes:
1
Encoding:
1101 1000
Data Transfer Sequence:
0110 0001
x000 0001
Data for
10
H
Data for
11
H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
D
IN
D
OUT
D
IN
1100 0000
D
OUT
xxxx xxxx
D
IN
1101 0011
D
OUT
xxxx xxxx
D
IN
1101 1000
D
OUT
xxxx xxxx
RF2R Read FLASH Page to RAM
Description: Read the selected FLASH page to the RAM.
Operands:
f
Bytes:
1
Encoding:
100f ffff
Data Transfer Sequence:
Read FLASH Page 2 to RAM
D
IN
1000 0010
D
OUT
xxxx xxxx
WR2F Write RAM to FLASH
Description: Write the contents of RAM to the selected
FLASH page.
Operands:
f
Bytes:
1
Encoding:
101f ffff
Data Transfer Sequence:
Write RAM to FLASH page 31
D
IN
1011 1111
D
OUT
xxxx xxxx
ADS1218
22
SBAS187
SELFCAL
Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Control Register (OCR) and the Full-Scale Register (FSR) are
updated with new values after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0000
Data Transfer Sequence:
SELFOCAL Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Control Register (OCR) is updated after this
operation.
Operands:
None
Bytes:
1
Encoding:
1111 0001
Data Transfer Sequence:
D
IN
1111 0000
D
OUT
xxxx xxxx
D
IN
1111 0001
D
OUT
xxxx xxxx
CSARAM
Calculate Checksum for all
RAM Banks
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. All bits are included in the checksum calculation,
there is no masking of bits.
Operands:
None
Bytes:
1
Encoding:
1110 1000
Data Transfer Sequence:
D
IN
1110 1000
D
OUT
xxxx xxxx
CSRAM
Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. All bits are included in the checksum
calculation, there is no masking of bits.
Operands:
a
Bytes:
1
Encoding:
1110 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 2
D
IN
1110 0010
D
OUT
xxxx xxxx
CSREG
Calculate the Checksum of
Registers
Description: Calculate the checksum of all the registers. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands:
None
Bytes:
1
Encoding:
1101 1111
Data Transfer Sequence:
D
IN
1101 1111
D
OUT
xxxx xxxx
CSFL Calculate Checksum for all FLASH Pages
Description: Calculate the checksum for all FLASH pages.
The checksum is calculated as a sum of all the bytes with the
carry ignored. All bits are included in the checksum calcula-
tion, there is no masking of bits.
Operands:
None
Bytes:
1
Encoding:
1110 1100
Data Transfer Sequence:
D
IN
1110 1100
D
OUT
xxxx xxxx
23
ADS1218
SBAS187
SLEEP
Sleep Mode
Description: Puts the ADS1218 into a low power sleep mode.
To exit sleep mode strobe SCLK.
Operands:
None
Bytes:
1
Encoding:
1111 1101
Data Transfer Sequence:
RESET
Reset to Powerup Values
Description: Restore the registers to their power-up values.
This command will also stop the Read Continuous mode. It
does not affect the contents of RAM.
Operands:
None
Bytes:
1
Encoding:
1111 1110
Data Transfer Sequence:
D
IN
1111 1101
D
OUT
xxxx xxxx
D
IN
1111 1110
D
OUT
xxxx xxxx
DSYNC
Sync DRDY
Description: Synchronizes the ADS1218 to the serial clock
edge.
Operands:
None
Bytes:
1
Encoding:
1111 1100
Data Transfer Sequence:
D
IN
1111 1100
D
OUT
xxxx xxxx
SELFGCAL Gain Self Calibration
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values
after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0010
Data Transfer Sequence:
SYSOCAL
System Offset Calibration
Description: Starts the system offset calibration process. For
a system offset calibration the input should be set to 0V
differential, and the ADS1218 computes the OCR register
value that will compensate for offset errors. The Offset
Control Register (OCR) is updated after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0011
Data Transfer Sequence:
SYSGCAL
System Gain Calibration
Description: Starts the system gain calibration process. For a
system gain calibration, the differential input should be set to
the reference voltage and the ADS1218 computes the FSR
register value that will compensate for gain errors. The FSR is
updated after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0100
Data Transfer Sequence:
D
IN
1111 0010
D
OUT
xxxx xxxx
D
IN
1111 0011
D
OUT
xxxx xxxx
D
IN
1111 0100
D
OUT
xxxx xxxx
ADS1218
24
SBAS187
LSB
MSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
x
rdata
x
rdatac
x
x
x
x
x
x
x
x
x
x
x
stopc
0001
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
rreg
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0010
rram
rram
rram
rram
rram
rram
rram
rram
x
x
x
x
x
x
x
x
0
1
2
3
4
5
6
7
0011
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0100
creg
creg
creg
creg
creg
creg
creg
creg
crega
x
x
x
x
x
x
x
0
1
2
3
4
5
6
7
0101
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
wreg
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0110
wram
wram
wram
wram
wram
wram
wram
wram
x
x
x
x
x
x
x
x
0
1
2
3
4
5
6
7
0111
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1000
rf2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1001
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
r f2r
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1010
w r 2f
w r 2f
w r 2f
w r 2f
w r 2f
wr 2f
w r 2f
wr 2f
wr 2f
w r 2f
wr 2f
wr 2f
wr 2f
w r 2f
wr 2f
w r 2f
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1011
w r 2f
w r 2f
w r 2f
w r 2f
w r 2f
wr 2f
w r 2f
wr 2f
wr 2f
w r 2f
wr 2f
wr 2f
wr 2f
w r 2f
wr 2f
w r 2f
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1100
cram 0
cram 1
cram 2
cram 3
cram 4
cram 5
cram 6
cram 7
x
x
x
x
x
x
x
x
1101
x
x
x
x
x
x
csreg
csramx csramx
csramx
csramx csramx
csramx csramx
csramx
csramx
0
1
2
3
4
5
6
7
1110
x
x
x
csfl
x
x
x
csram 0 csram 1 csram2 csram 3 csram 4 csram 5 csram 6 csram 7
csram
1111
self
self
self
sys
sys
x
x
x
x
x
x
x
dsync
sleep
reset
x
cal
ocal
gcal
ocal
gcal
x = Reserved
TABLE IV. ADS1218 Command Map.
25
ADS1218
SBAS187
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI), allows a controller to
communicate synchronously with the ADS1218. The
ADS1218 operates in slave only mode.
SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted
and received. The SCLK signal synchronizes shifting and
sampling of the information on the two serial data lines: D
IN
and D
OUT
. The CS signal allows individual selection of an
ADS1218 device; an ADS1218 with CS HIGH is not active
on the bus.
Clock Phase and Polarity Controls (POL)
The clock polarity is specified by the POL pin, which selects
an active HIGH or active LOW clock, and has no effect on
the transfer format.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input to the ADS1218, is gener-
ated by the master device and synchronizes data transfer on
the D
IN
and D
OUT
lines. When transferring data to or from
the ADS1218, burst mode may be used i.e., multiple bits of
data may be transferred back-to-back with no delay in
SCLKs or toggling of CS.
Chip Select (CS)
The chip select (CS) input of the ADS1218 must be exter-
nally asserted before a master device can exchange data with
the ADS1218. CS must be LOW before data transactions
and must stay LOW for the duration of the transaction.
DIGITAL INTERFACE
The ADS1218's programmable functions are controlled
using a set of on-chip registers, as outlined previously. Data
is written to these registers via the part's serial interface and
read access to the on-chip registers is also provided by this
interface.
The ADS1218's serial interface consists of four signals: CS,
SCLK, D
IN
, and D
OUT
. The D
IN
line is used for transferring
data into the on-chip registers while the D
OUT
line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on
D
IN
or D
OUT
) take place with respect to this SCLK signal.
The DRDY line is used as a status signal to indicate when
data is ready to be read from the ADS1218's data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
CS is used to select the device. It can be used to decode the
ADS1218 in systems where a number of parts are connected
to the serial bus.
The timing specification shows the timing diagram for
interfacing to the ADS1218 with CS used to decode the part.
The ADS1218 serial interface can operate in three-wire
mode by tying the CS input LOW. In this case, the SCLK,
D
IN
, and D
OUT
lines are used to communicate with the
ADS1218 and the status of DRDY can be obtained by
interrogating bit 7 of the M/DEC1 register. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port pin.
DEFINITION OF TERMS
Analog Input Voltage--the voltage at any one analog input
relative to AGND.
Analog Input Differential Voltage--given by the following
equation: (IN+ IN). Thus, a positive digital output is pro-
duced whenever the analog input differential voltage is posi-
tive, while a negative digital output is produced whenever the
differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2.5V. The negative full-scale output is produced when
the differential is 2.5V. In each case, the actual input
voltages must remain within the AGND to AV
DD
range.
Conversion Cycle--the term "conversion cycle" usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the t
DATA
time period.
However, each digital output is actually based on the modu-
lator results from several t
DATA
time periods.
FILTER SETTING
MODULATOR RESULTS
fast settling
1 t
DATA
time period
sinc
2
2 t
DATA
time period
sinc
3
3 t
DATA
time period
Data Rate--The rate at which conversions are completed.
See definition for f
DATA
.
Decimation Ratio--defines the ratio between the output of
the modulator and the output Data Rate. Valid values for the
Decimation Ratio are from 20 to 2047. Larger Decimation
Ratios will have lower noise and vice-versa.
ADS1218
26
SBAS187
PGA SETTING
SAMPLING FREQUENCY
1, 2, 4, 8
16
32
64, 128
f
f
mfactor
SAMP
OSC
=
f
f
mfactor
SAMP
OSC
=
2
f
f
mfactor
SAMP
OSC
=
4
f
f
mfactor
SAMP
OSC
=
8
LSB Weight
Full Scale Range
N
=
-
2
BITS rms
BIPOLAR Vrms
UNIPOLAR Vrms
24
298nV
149nV
22
1.19
V
597nV
20
4.77
V
2.39
V
18
19.1
V
9.55
V
16
76.4
V
38.2
V
14
505
V
152.7
V
12
1.22mV
610
V
5V SUPPLY ANALOG INPUT
(1)
GENERAL EQUATIONS
DIFFERENTIAL
PGA OFFSET
FULL-SCALE
DIFFERENTIAL
PGA SHIFT
GAIN SETTING
FULL-SCALE RANGE
INPUT VOLTAGES
(2)
RANGE
RANGE
INPUT VOLTAGES
(2)
RANGE
1
5V
2.5V
1.25V
2
2.5V
1.25V
0.625V
4
1.25V
0.625V
312.5mV
8
0.625V
312.5mV
156.25mV
16
312.5mV
156.25mV
78.125mV
32
156.25mV
78.125mV
39.0625mV
64
78.125mV
39.0625mV
19.531mV
128
39.0625mV
19.531mV
9.766mV
NOTES: (1) With a 2.5V reference. (2) The ADS1218 allows common-mode voltage as long as the absolute input voltage on A
IN
P or A
IN
N does not go below
AGND or above AV
DD
.
SPEED = 0
SPEED = 1
mfactor
128
256
TABLE V. Full-Scale Range versus PGA Setting.
2
V
PGA
REF
V
PGA
REF
V
PGA
REF
2
f
f
Decimation Ratio
f
mfactor Decimation Ratio
DATA
MOD
OSC
=
=
2
10
6 02
20
.
V
PGA
REF
ER
V
PGA
REF
ER
10
6 02
20
.
f
f
mfactor
MOD
OSC
=
Effective Resolution--the effective resolution of the
ADS1218 in a particular configuration can be expressed in
two different units: bits rms (referenced to output) and Vrms
(referenced to input). Computed directly from the converter's
output data, each is a statistical calculation. The conversion
from one to the other is shown below.
Filter Selection--the ADS1218 uses a (sinx /x) filter or sinc
filter. Actually there are three different sinc filters that can
be selected. A fast settling filter will settle in one t
DATA
cycle. The sinc
2
filter will settle in two cycles and have
lower noise. The sinc
3
will achieve the lowest noise and
highest number of effective bits, but requires three cycles to
settle. The ADS1218 will operate with any one of these
filters, or it can operate in an auto mode, where it will select
the fast settling filter after a new channel is selected and will
then switch to sinc
2
followed by sinc
3
. This allows fast
settling response and still achieves low noise after the
necessary number of t
DATA
cycles.
f
OSC
--the frequency of the crystal oscillator or CMOS
compatible input signal at the X
IN
input of the ADS1218.
f
MOD
--the frequency or speed at which the modulator of the
ADS1218 is running. This depends on the SPEED bit as
given by the following equation:
f
SAMP
--the frequency, or switching speed, of the input
sampling capacitor. The value is given by one of the follow-
ing equations:
f
DATA
--the frequency of the digital output data produced by
the ADS1218, f
DATA
is also referred to as the Data Rate.
Full-Scale Range (FSR)--as with most A/D converters, the
full-scale range of the ADS1218 is defined as the "input",
which produces the positive full-scale digital output minus
the "input", which produces the negative full-scale digital
output. The full-scale range changes with gain setting as
shown in Table V.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus 1.25V (nega-
tive full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight--this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
where N is the number of bits in the digital output.
t
DATA
--the inverse of f
DATA
, or the period between each
data output.
27
ADS1218
SBAS187
TOPIC INDEX
TOPIC
PAGE
ABSOLUTE MAXIMUM RATINGS .......................................................................................................................... 2
PACKAGE AND ORDERING INFORMATION ........................................................................................................ 2
ELECTRICAL CHARACTERISTICS (AV
DD
= 5V) .................................................................................................. 2
ELECTRICAL CHARACTERISTICS (AV
DD
= 3V) .................................................................................................. 4
PIN CONFIGURATION ............................................................................................................................................ 6
TIMING SPECIFICATIONS ...................................................................................................................................... 7
TYPICAL CHARACTERISTICS ............................................................................................................................... 8
OVERVIEW ............................................................................................................................................................. 12
MEMORY ................................................................................................................................................................15
REGISTER BANK TOPOLOGY ............................................................................................................................ 15
DETAILED REGISTER DEFINITIONS ..................................................................................................................17
COMMAND DEFINITIONS .....................................................................................................................................19
ADS1218 COMMAND MAP ................................................................................................................................... 24
SERIAL PERIPHERAL INTERFACE ..................................................................................................................... 25
DIGITAL INTERFACE ............................................................................................................................................25
DEFINITION OF TERMS ........................................................................................................................................ 25
ADS1218
28
SBAS187
PACKAGE DRAWING
MTQF019A JANUARY 1995 REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
4073176 / B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX
0,08
0,50
M
0,08
0
7
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS1218Y/250
ACTIVE
TQFP
PFB
48
250
ADS1218Y/2K
ACTIVE
TQFP
PFB
48
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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