2129BHIREL12/04

Features

PowerPC

Single Issue Integer Core

Precise Exception Model

Extensive System Development Support

On-chip Watchpoints and Breakpoints
Program Flow Tracking
On-chip Emulation (Once) Development Interface

High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)

Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)

MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus
Monitor, and Real-time Clocks

Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with
Book 1 of the PowerPC Architecture Definition) with 32 × 32-bit Fixed Point Registers

 Embedded PowerPC Performs Branch Folding, Branch Prediction with

Conditional Prefetch, without Conditional Execution

4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU
Instruction and Data Caches are Two-way, Set Associative, Physical Address,

4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line
Granularity

MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs
MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB;

16 Virtual Address Spaces and 8 Protection Groups

 Advanced On-chip Emulation Debug Mode

Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)

32 Address Lines

Fully Static Design

= +3.3V ± 5%

max

= 66 MHz

Military Temperature Range: -55

°C < T

< +125

°C

= 0.75 W Typical at 66 MHz

Description

The TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICC

)

is a versatile one-chip integrated microprocessor and peripheral combination that can
be used in a variety of controller applications. It particularly excels in communications
and networking systems. The Power QUICC (pronounced "quick") can be described
as a PowerPC-based derivative of the TS68EN360 (QUICC

The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates
memory management units (MMUs) and instruction and data caches. The communi-
cations processor module (CPM) of the TS68EN360 QUICC has been enhanced with
the addition of a Two-wire Interface (TWI) compatible with protocols such as I

C. Mod-

erate to high digital signal processing (DSP) functionality has been added to the CPM.
The memory controller has been enhanced, enabling the TSPC860 to support any
type of memory, including high performance memories and newer dynamic random
access memories (DRAMs). Overall system functionality is completed with the addi-
tion of a PCMCIA socket controller supporting up to two sockets and a real-time clock.

PBGA 357

ZQ suffix

Integrated
Communication
Processor

TSPC860

Preliminary
Specification
-site

Rev. 2129BHIREL12/04

TSPC860 [Preliminary]

2129BHIREL12/04

Screening/Quality

This product will be manufactured in full compliance with:

According to Atmel Standards

General Description

The TSPC860 is functionally composed of three major blocks:

A 32-bit PowerPC Core with MMUs and Caches

A System Interface Unit

A Communications Processor Module

Figure 1. Block Diagram View of the TSPC860

Embedded

PowerPC

Core

Instruction

Bus

4 or 16 KB

I-Cache

I-MMU

SCC1

SCC2

SCC3

SCC4

SMC1 SMC2

SPI

TWI

Time Slot Assigner

Serial Interface

Parallel I/O

16 Serial DMA

and

Virtual IDMA

Memory Controller

Bus Interface Unit

System Functions

Real Time Clock

PCMCIA Interface

Baud Rate

Generators

Parallel

Interface Port

Timer

32-bit RISC µController

and Program ROM

MAC

Timers

Interrupt

Controller

Dual-Port

RAM

4 or 8 KB

D-Cache

D-MMU

Load/store

BUS

Unified Bus

SYSTEM INTERFACE UNIT

TSPC860 [Preliminary]

2129BHIREL12/04

Main Features

The Following is a List of the TSPC860's Important Features:

Fully Static Design

Four Major Power Saving Modes

357-pin Ball Grid Array Packaging (Plastic)

32-bit Address and Data Busses

Flexible Memory Management

4-Kbyte Physical Address, Two-way, Set-associative Data Cache

4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache

Eight-bank Memory Controller

Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals

Byte Write Enables and Selectable Parity Generation

32-bit Address Decodes with Bit Masks

System Integration Unit

Clock Synthesizer

Power Management

Reset Controller

PowerPC Decrementer And Time Base

Real-time Clock Register

Periodic Interrupt Timer

Hardware Bus Monitor and Software Watchdog Timer

IEEE 1149.1 JTAG Test Access Port

Communications Processor Module

Embedded 32-bit RISC Controller Architecture for Flexible I/O

Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual
DMA Channel Controller

Continuous Mode Transmission And Reception On All Serial Channels

Serial DMA Channels For Reception And Transmission On All Serial
Channels

I/O registers with Open-drain Capability

Memory-memory and Memory-I/O Transfers with Virtual DMA Functionality

TSPC860 [Preliminary]

2129BHIREL12/04

Four serial communications controllers

Protocols Supported by ROM or Downloadable Microcode and Include, but
Limited to, the Digital Portion of:
- Ethernet/IEEE 802.3 CS/CDMA
- HDLC/SDLC and HDLC bus
- Apple Talk
- Signaling System #7 (RAM Microcode Only)
- Universal Asynchronous Receiver Transmitter (UART)
- Synchronous UART
- Binary Synchronous (BiSync) Communications
- Totally Transparent
- Totally Transparent with CRC
- Profibus (RAM Microcode Option)
- Asynchronous HDLC
- DDCMP
- V.14 (RAM Microcode Option)
- X.21 (RAM Microcode Option)
- V.32bis Datapump Filters
- IrDA Serial Infrared
- Basis Rate ISDN (BRI) in Conjunction with SMC Channels
- Primary Rate ISDN (MH Version Only)

Four Hardware Serial Communications Controller Channels Supporting the
Protocols

Two Hardware Serial Management Channels
- Management for BRI Devices as General Circuit Interface Controller
Multiplexed Channels
- Low-speed UART operation

Hardware Serial Peripheral Interfaces

Two-wire Interface (TWI)

Time-slot Assigner

Port Supports Centronics Interfaces and Chip-to-chip

Four Independent Baud Rate Generators and Four Input Clock Pins for
Supplying Clocks to SMC and SCC Serial Channels

Four Independent 16-bit timers Which Can Be Interconnected as Two 32-bit
Timers

TSPC860 [Preliminary]

2129BHIREL12/04

Pin Assignment

Plastic Ball Grid Array

Figure 2. Pin Assignment: Top View

PD3

IRQ7

VDDL

D29

CLKOUT IPA3

DP2

A14

A27

A29

A30

A28

A31

VDDL BSA2

WE1

WE3

CE2A

CS1

CS4

A11

A13

A17

A21

A23

A22

TSIZ0 BSA3 M_CRS WE2 GPLA2

CE1A

CS5

A10

GPLB4

PA15

A12

A16

A20

A24

A26

TSIZ1 BSA1

WE0 GPLA1 GPLA3

CS0

CS7

PB31

GPLA4

PB30

PC14

PC15

N/C

A15

A19

A25

A18

BSA0 GPLA0

N/C

CS6

GPLA5 BDIP

CS2

PA14

TEA

PB28

PC13

PB29

VDDH

CS3

PA13

PB27

PC12

VDDL

GND

IRQ3

VDDL

PA12

BURST

PB26

TMS

PA11

IRQ6

IPB4

TDO

IPB3

TRST

M_MDIO

TCK

IRQ2

IPB0

M_COL

TDI

IPB7

VDDL

PB24

PB25

IPB1

IPB2

IPB5

PA10

ALEB

PC11

PA9

PB21

GND

IPB6 ALEA

BADDR30

PB23

IRQ4

PC10

PC9

PB20

OP1

OP0

PA8

MODCK1

PB22

PC8

PC7

BADDR28

BADDR29

MODCK2

PA6

VDDL

PA7

PA5

PB16

TEXP

EXTCLK

HRESET

PB18

EXTAL

PB19

PB17

VDDL

GND

RSTCONF SRESET

VDDL

PA3

GND

XTAL

PA4

PA2

PD12

VDDH

WAIT_A

PORESET

WAIT_B

PB15

VDDH

KAPWR

PC6

PC5

PD11

VDDH D12

D17

D15

D22

D25

D31

IPA6

IPA0

IPA7

XFC

IPA1

PC4

PD7

VDDSYN

PA1

PB14

PD4

IRQ1

D23

D11

D16

D19

D21

D26

D30

IPA5

IPA2

N/C

IPA4

PD15

PD5

VSSSYN

PA0

PD13

PD6

IRQ0 D13

D27

D10

D14

D18

D20

D24

D28

DP1

DP0

N/C

DP3

PD9

M_Tx_EN

VSSSYN1

PD14

PD10

PD8

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