1
Features
8-bit Resolution
ADC Gain Adjust
1.5 GHz Full Power Input Bandwidth (-3 dB)
1 GSPS (min) Sampling Rate
SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,
at F
S
= 1 GSPS, F
IN
= 20 MHz
SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,
at F
S
= 1 GSPS, F
IN
= 500 MHz
SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,
at F
S
= 1 GSPS, F
IN
= 1000 MHz (-3 dB FS)
2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS
DNL = 0.3 lsb, INL = 0.7 lsb
Low Bit Error Rate (10
-13
) at 1 GSPS
Very Low Input Capacitance: 3 pF
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50
ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Power Consumption: 3.4W at Tj = 70
C Typical
Radiation Tolerance Oriented Design (150 Krad (Si) measured)
Two Package Versions
Evaluation board: TSEV8388B
Demultiplexer TS81102G0: Companion Device Available
Applications
Digital Sampling Oscilloscopes
Satellite Receiver
Electronic Countermeasures/Electronic Warfare
Direct RF Down-conversion
Description
The TS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.
The TS8388B uses an innovative architecture,
including an on-chip Sample and Hold (S/H),
and is fabricated with an advanced
high speed bipolar process.
The on-chip S/H has a 1.5 GHz full power
input bandwidth, providing excellent dynamic
performance in undersampling applications
(High IF digitizing).
ADC 8-bit
1 GSPS
TS8388B
Rev. 2144CBDC04/03
2
TS8388B
2144CBDC04/03
Functional
Description
Block Diagram
The following figure shows the simplified block diagram.
Figure 1. Simplified Block Diagram
Functional
Description
The TS8388B is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology
featuring a cutoff frequency of 25 GHz.
The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering
an error correction circuitry and a resynchronization stage followed by 75
differential output
buffers.
The TS8388B works in fully differential mode from analog inputs up to digital outputs.
The TS8388B features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388B.
The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysili-
con resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
MASTER/SLAVE TRACK & HOLD AMPLIFIER
V
IN
, V
INB
CLOCK
BUFFER
GAIN
GORB
DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
4
5
4
5
8
8
G=2
T/H
G=1
T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
3
TS8388B
2144CBDC04/03
Specifications
Absolute
Maximum Ratings
Note:
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat
sink is mandatory. See "The board set comes fully assembled and tested, with the TS8388B installed." on page 42.
Recommended
Operating
Conditions
Table 1. Absolute Maximum Ratings
Parameter
Symbol
Comments
Value
Unit
Positive supply voltage
V
CC
GND to 6
V
Digital negative supply voltage
DV
EE
GND to -5.7
V
Digital positive supply voltage
V
PLUSD
GND -0.3 to 2.8
V
Negative supply voltage
V
EE
GND to -6
V
Maximum difference between negative supply voltage
DV
EE
to V
EE
0.3
V
Analog input voltages
V
IN
or V
INB
-1 to +1
V
Maximum difference between V
IN
and V
INB
V
IN
- V
INB
-2 to +2
V
Digital input voltage
V
D
GORB
-0.3 to V
CC
+0.3
V
Digital input voltage
V
D
DRRB
V
EE
-0.3 to +0.9
V
Digital output voltage
V
O
V
PLUSD
-3 to V
PLUSD
-0.5
V
Clock input voltage
V
CLK
or V
CLKB
-3 to +1.5
V
Maximum difference between V
CLK
and V
CLKB
V
CLK
- V
CLKB
-2 to +2
V
Maximum junction temperature
T
j
+135
C
Storage temperature
T
stg
-65 to +150
C
Lead temperature (soldering 10s)
T
leads
+300
C
Table 2. Recommended Operating Conditions
Parameter
Symbol
Comments
Recommended Value
Unit
Min
Typ
Max
Positive supply voltage
V
CC
4.5
+5
5.25
V
Positive digital supply voltage
V
PLUSD
ECL output compatibility
GND
V
Positive digital supply voltage
V
PLUSD
LVDS output compatibility
+1.4
+2.4
+2.6
V
Negative supply voltage
V
EE,
DV
EE
-5.25
-5
-4.75
V
4
TS8388B
2144CBDC04/03
Electrical
Operating
Characteristics
V
EE
= DV
EE
= -5V; V
CC
= +5V; V
IN
-V
INB
= 500 mVpp Full Scale differential input;
Digital outputs 75 or 50
differentially terminated;
Tj (typical) = 70
C. Full Temperature Range: up to -55
C < Tc; Tj < +125
C, depending on
device grade.
Differential analog input voltage
(Full Scale)
V
IN,
V
INB
V
IN
- V
INB
50
differential or single-ended
113
450
125
500
137
550
mV
mVpp
Clock input power level
P
CLK,
P
CLKB
50
single-ended clock input
3
4
10
dBm
Operating temperature range
T
J
Commercial grade: "C"
Industrial grade: "V"
Military grade: "M"
0 < Tc; Tj < 90
-40 < Tc; Tj < 110
-55 < Tc; Tj < +125
C
Table 2. Recommended Operating Conditions (Continued)
Parameter
Symbol
Comments
Recommended Value
Unit
Min
Typ
Max
Table 3. Electrical Specifications
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
Power Requirements (CBGA68 package)
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
V
CC
V
PLUSD
V
PLUSD
1
4
4
4.5
1.4
5
0
2.4
5.5
2.6
V
V
V
Positive supply current
Analog
Digital
I
CC
I
PLUSD
1
1
420
130
445
145
mA
mA
Negative supply voltage
V
EE
1
-5.5
-5
-4.5
V
Negative supply current
Analog
Digital
AI
EE
DI
EE
1
1
185
160
200
180
mA
mA
Nominal power dissipation
PD
1
3.9
4.1
W
Power supply rejection ratio
PSRR
4
0.5
2
mW
Power Requirements
Power Requirements (CQFP68 packaged device)
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
V
CC
V
PLUSD
V
PLUSD
1, 2, 6
4
4
4.7
1.4
5
0
2.4
5.3
2.6
V
V
V
5
TS8388B
2144CBDC04/03
Positive supply current
Analog
Digital
I
CC
I
PLUSD
1, 2
6
1, 2
6
385
395
115
120
445
445
145
145
mA
mA
mA
mA
Negative supply voltage
V
EE
1, 2, 6
-5.3
-5
-4.7
V
Negative supply current
Analog
Digital
AI
EE
DI
EE
1, 2
6
1, 2
6
165
170
135
145
200
200
180
180
mA
mA
mA
mA
Nominal power dissipation
PD
1, 2
6
3.4
3.6
4.1
4.3
W
W
Power supply rejection ratio
PSRR
4
0.5
2
mW
Resolution
8
bits
(2)
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
V
IN
V
INB
4
-125
-125
125
125
mV
mV
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
V
IN
V
INB
4
-250
0
250
mV
mV
Analog input capacitance
C
IN
4
3
3.5
pF
Input bias current
I
IN
4
10
20
A
Input Resistance
R
IN
4
0.5
1
M
Full Power input Bandwidth (-3dB)
CBGA68 package
CQFP68 package
FPBW
4
4
1.8
1.5
GHz
GHz
Small signal input Bandwidth (10% full scale)
SSBW
4
1.5
1.7
GHz
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
ECL or specified clock input
power level in dBm
(10)
ECL Clock inputs voltages (V
CLK
or V
CLKB
):
4
Logic "0" voltage
V
IL
-1.5
V
Logic "1" voltage
V
IH
-1.1
V
Logic "0" current
I
IL
5
50
A
Logic "1" current
I
IH
5
50
A
Clock input power level into 50
termination
dBm into 50
Clock input power level
4
-2
4
10
dBm
Clock input capacitance
C
CLK
4
3
3.5
pF
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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