Rev. D - 15 January, 2001
1
TS80C51U2
TS83C51U2
TS87C51U2
Double UART 8-bit CMOS Microcontroller
1. Description
TS80C51U2 is high performance CMOS ROM, OTP
and EPROM versions of the 80C51 CMOS single chip
8-bit microcontroller.
The TS80C51U2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16 Kbytes), 256 bytes
of internal RAM, a 7-source , 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C51U2 has a second UART,
enhanced functions on both UART, enhanced timer 2,
a hardware watchdog timer, a dual data pointer, a baud
rate generator and a X2 speed improvement mechanism.
The fully static design of the TS80C51U2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51U2 has 2 software-selectable modes of
reduced
activity
for
further
reduction
in
power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
q
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q
Second UART
q
Baud Rate Generator
q
Dual Data Pointer
q
On-chip ROM/EPROM (16K-bytes)
q
Programmable Clock Out and Up/Down Timer/
Counter 2
q
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
q
Asynchronous port reset
q
Interrupt Structure with
7 Interrupt sources
4 level priority interrupt system
q
Full duplex Enhanced UARTs
Framing error detection
Automatic address recognition
q
Low EMI (inhibit ALE)
q
Power Control modes
Idle mode
Power-down mode
Power-off Flag
q
Once mode (On-chip Emulation)
q
Power supply: 4.5-5.5V, 2.7-5.5V
q
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
q
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window)
3. The second UART
In this document, UART_0 will make reference to the
first
UART
(present
in
all
Atmel
Wireless
&
Microcontrollers C51 derivatives) and UART_1 will
make reference to the second UART, only present in
the TS80C51U2 part.
The second UART (UART_1) can be seen as an alternate
function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or
P1.7 for TXD1) or can be connected to (pin6 or pin12)
and (pin28 or pin34) of 44-pin package (see Pin
2
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the
clock source. This common internal baud rate generator can be used independently by each UART or both as clock
source allowing to program various speeds.
The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer
2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive
buffered, meaning they can start reception of a second byte before a previously received byte has been read from
the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function
Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate
receive register.
The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the
mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt
bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication
is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication
feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability.
The UART_1 also comes with Frame error detection, similar to the UART_0.
4
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
5. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51U2 fall into the following categories:
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P0, P1, P2, P3
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
Serial I/O port registers for UART_0: SADDR_0, SADEN_0, SBUF_0, SCON_0
Serial I/O port registers for UART_1: SADDR_1, SADEN_1, SBUF_1, SCON_1
Baud Rate Generator registers: BRL, BDRCON, BDRCON_1
Power and clock control registers: PCON
HDW Watchdog Timer Reset: WDTRST, WDTPRG
Interrupt system registers: IE, IP, IPH
Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
Bit
address-
able
Non Bit addressable
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
FFh
F0h
B
0000 0000
F7h
E8h
EFh
E0h
ACC
0000 0000
E7h
D8h
DFh
D0h
PSW
0000 0000
D7h
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CFh
C0h
SCON_1
0000 0000
SBUF_1
XXXX XXXX
C7h
B8h
IP
X000 0000
SADEN_0
0000 0000
SADEN_1
0000 0000
BFh
B0h
P3
1111 1111
IPH
X000 0000
B7h
A8h
IE
0X00 0000
SADDR_0
0000 0000
SADDR_1
0000 0000
AFh
A0h
P2
1111 1111
AUXR1
XXXX XXX0
WDTRST
XXXX XXXX
WDTPRG
XXXX X000
A7h
98h
SCON_0
0000 0000
SBUF_0
XXXX XXXX
BRL
0000 0000
BDRCON
0XXX 0000
BDRCON_1
0X00 00XX
9Fh
90h
P1
1111 1111
97h
88h
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
00XX XXX0
CKCON
XXXX XXX0
8Fh
80h
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00X1 0000
87h
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
reserved
Rev. D - 15 January, 2001
5
TS80C51U2
TS83C51U2
TS87C51U2
6. Pin Configuration
s
5 4 3 2
1
6
44 43 42 41 40
P1.4
P1.0/T2
P1.1/T2EX
P1.3/TxD_1
P1.2/RxD_1
VSS1/NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA/VPP
TxD_1
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XT
AL2
XT
AL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
43
42 41 40
39
44
38 37 36 35 34
P1.4
P1.0/T2
P1.1/T2EX
P1.3/TxD_1
P1.2/RxD_1
VSS1/NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA/VPP
TxD_1
P2.7/A15
P2.5/A13
P2.6/A14
P1.5
P1.6/RxD_1
P1.7/TxD_1
RST
P3.0/RxD_0
RxD_1
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XT
AL2
XT
AL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5
P1.6/RxD_1
P1.7/TxD_1
RST
P3.0/RxD_0
RxD_1
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
NIC*
*NIC: No Internal Connection
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PLCC/CQPJ 44
33
32
31
30
29
28
27
26
25
24
23
VQFP44 1.4
1
2
3
4
5
6
7
8
9
10
11
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
P1.7/TxD_1
RST
P3.0/RxD_0
P3.1/TxD_0
P1.3/TxD_1
1
P1.5
P3.2/INT0
P3.3/INT1
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.3 / A11
P2.4 / A12
P0.4 / A4
P0.6 / A6
P0.5 / A5
P0.7 / A7
ALE/PROG
PSEN
EA/VPP
P2.7 / A15
P2.5 / A13
P2.6 / A14
P1.0 / T2
P1.1 / T2EX
VCC
P0.0 / A0
P0.1 / A1
P0.2 / A2
P0.3 / A3
PDIL/
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CDIL40
P1.6/RxD_1
P1.4
P1.2/RxD_1
P3.4/T0
See "Alternate function on Port 1" on page 32 for accurate RxD_1 and TxD_1 pin location, depending on AUXR
register configuration.
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