Features
High Performance, Low Power AVR
8-Bit Microcontroller
Advanced RISC Architecture
120 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Non-volatile Program and Data Memories
2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny24/44/84)
Endurance: 10,000 Write/Erase Cycles
128/256/512 Bytes In-System Programmable EEPROM (ATtiny24/44/84)
Endurance: 100,000 Write/Erase Cycles
128/256/512 Bytes Internal SRAM (ATtiny24/44/84)
Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
Two Timer/Counters, 8- and 16-bit counters with two PWM Channels on both
10-bit ADC
8 single-ended channels
12 differential ADC channel pairs with programmable gain (1x, 20x)
Temperature Measurement
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Universal Serial Interface
Special Microcontroller Features
debugWIRE On-chip Debug System
In-System Programmable via SPI Port
External and Internal Interrupt Sources
Pin Change Interrupt on 12 pins
Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit
Internal Calibrated Oscillator
On-chip Temperature Sensor
I/O and Packages
14-pin SOIC, PDIP and 20-pin QFN/MLF: Twelve Programmable I/O Lines
Operating Voltage:
1.8 - 5.5V for ATtiny24V/44V/84V
2.7 - 5.5V for ATtiny24/44/84
Speed Grade
ATtiny24V/44V/84V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
ATtiny24/44/84: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
Active Mode:
1 MHz, 1.8V: 380 A
Power-down Mode:
1.8V: 100 nA
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny24/44/84
Preliminary
Rev. 8006AAVR12/05
2
8006AAVR12/05
ATtiny24/44/84
1.
Pin Configurations
Figure 1-1.
Pinout ATtiny24/44/84
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology. Min and Max values will be available after the device is characterized.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
(PCINT8/XTAL1) PB0
(PCINT9/XTAL2) PB1
(PCINT11/RESET/dW) PB3
(PCINT10/INT0/OC0A/CKOUT) PB2
(PCINT7/ICP/OC0B/ADC7) PA7
(PCINT6/OC1A/SDA/MOSI/ADC6) PA6
GND
PA0 (ADC0/AREF/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/T0/PCINT3)
PA4 (ADC4/USCK/SCL/T1/PCINT4)
PA5 (ADC5/DO/MISO/OC1B/PCINT5)
PDIP/SOIC
1
2
3
4
5
QFN/MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
DNC
DNC
GND
VCC
DNC
PA7 (PCINT7/ICP/OC0B/ADC7)
PB2 (PCINT10/INT0/OC0A/CKOUT)
PB3 (PCINT11/RESET/dW)
PB1 (PCINT9/XTAL2)
PB0 (PCINT8/XTAL1)
PA5
DNC
DNC
DNC
PA6
Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/ADC6)
Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)
(ADC4/USCK/SCL/T1/PCINT4) PA4
(ADC3/T0/PCINT3) PA3
(ADC2/AIN1/PCINT2) PA2
(ADC1/AIN0/PCINT1) PA1
(ADC0/AREF/PCINT0) PA0
4
8006AAVR12/05
ATtiny24/44/84
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32
general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit
timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,
programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable
Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption.
The device is manufactured ng Atmel's high density non-volatile memory technology. The On-
chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
5
8006AAVR12/05
ATtiny24/44/84
2.2
Pin Descriptions
2.2.1
VCC
Supply voltage.
2.2.2
GND
Ground.
2.2.3
Port B (PB3...PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of
RESET pin, program (`0') RSTDISBL fuse. As inputs, Port B pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on
Section 12.3 "Alternate Port Functions" on page 59
.
2.2.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in
Table 9-1 on page
38
. Shorter pulses are not guaranteed to generate a reset.
2.2.5
Port A (PA7...PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A has an alternate functions as analog inputs for the ADC, analog comparator,
timer/counter, SPI and pin change interrupt as described in
"Alternate Port Functions" on page
59
3.
Resources
A comprehensive set of development tools, drivers and application notes, and datasheets are
available for download on http://www.atmel.com/avr.
4.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
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