2545DAVR07/04
Features
High Performance, Low Power AVR
8-Bit Microcontroller
Advanced RISC Architecture
131 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20 MHz
On-chip 2-cycle Multiplier
Non-volatile Program and Data Memories
4/8/16K Bytes of In-System Self-Programmable Flash (ATmega48/88/168)
Endurance: 10,000 Write/Erase Cycles
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
256/512/512 Bytes EEPROM (ATmega48/88/168)
Endurance: 100,000 Write/Erase Cycles
512/1K/1K Byte Internal SRAM (ATmega48/88/168)
Programming Lock for Software Security
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Real Time Counter with Separate Oscillator
Six PWM Channels
8-channel 10-bit ADC in TQFP and MLF package
6-channel 10-bit ADC in PDIP Package
Programmable Serial USART
Master/Slave SPI Serial Interface
Byte-oriented 2-wire Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated Oscillator
External and Internal Interrupt Sources
Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
23 Programmable I/O Lines
28-pin PDIP, 32-lead TQFP and 32-pad MLF
Operating Voltage:
1.8 - 5.5V for ATmega48V/88V/168V
2.7 - 5.5V for ATmega48/88/168
Temperature Range:
-40
C to 85
C
Speed Grade:
ATmega48V/88V/168V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
ATmega48/88/168: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Low Power Consumption
Active Mode:
1 MHz, 1.8V: 240A
32 kHz, 1.8V: 15A (including Oscillator)
Power-down Mode:
0.1A at 1.8V
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega48/V
ATmega88/V
ATmega168/V
Preliminary
Rev. 2545DAVR07/04
4
ATmega48/88/168
2545DAVR07/04
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM,
512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working reg-
isters, three flexible Timer/Counters with compare modes, internal and external
interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an
SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and MLF packages), a pro-
grammable Watchdog Timer with internal Oscillator, and five software selectable power
saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,
USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning.
The Power-down mode saves the register contents but freezes the Oscillator, disabling
all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU
and all I/O modules except asynchronous timer and ADC, to minimize switching noise
during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low
power consumption.
The device is manufactured using Atmel's high density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer, or
by an On-chip Boot program running on the AVR core. The Boot program can use any
interface to download the application program in the Application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
w i t h I n - S y s t e m S e l f - P r o g r a m m a b l e F l a s h o n a m o n o l i t h i c c h i p , t h e A t m e l
ATmega48/88/168 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The ATmega48/88/168 AVR is supported with a full suite of program and system devel-
o p m e n t t o o l s i n c l u d i n g : C C o m p i l e r s , M a c r o A s s e m b l e r s , P r o g r a m
Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
Comparison Between
ATmega48, ATmega88,
and ATmega168
The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader
support, and interrupt vector sizes. Table 1 summarizes the different memory and inter-
rupt vector sizes for the three devices.
ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mech-
anism. There is a separate Boot Loader Section, and the SPM instruction can only
execute from there. In ATmega48, there is no Read-While-Write support and no sepa-
rate Boot Loader Section. The SPM instruction can execute from the entire Flash.
Table 1. Memory Size Summary
Device
Flash
EEPROM
RAM
Interrupt Vector Size
ATmega48
4K Bytes
256 Bytes
512 Bytes
1 instruction word/vector
ATmega88
8K Bytes
512 Bytes
1K Bytes
1 instruction word/vector
ATmega168
16K Bytes
512 Bytes
1K Bytes
2 instruction words/vector
5
ATmega48/88/168
2545DAVR07/04
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port B (PB7..0) XTAL1/
XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the invert-
ing Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the
inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as
TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in "Alternate Functions of Port B"
on page 69 and "System Clock and Clock Options" on page 24.
Port C (PC5..0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The PC5..0 output buffers have symmetrical drive characteristics with both high
sink and source capability. As inputs, Port C pins that are externally pulled low will
source current if the pull-up resistors are activated. The Port C pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electri-
cal characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on
this pin for longer than the minimum pulse length will generate a Reset, even if the clock
is not running. The minimum pulse length is given in Table 20 on page 41. Shorter
pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in "Alternate Functions of Port C"
on page 73.
Port D (PD7..0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in "Alternate Functions of Port D"
on page 75.
AV
CC
AV
CC
is the supply voltage pin for the A/D Converter, PC3..0, and ADC7..6. It should be
externally connected to V
CC
, even if the ADC is not used. If the ADC is used, it should be
connected to V
CC
through a low-pass filter. Note that PC6..4 use digital supply voltage,
V
CC
.
AREF
AREF is the analog reference pin for the A/D Converter.
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