ChipFind - документация

Электронный компонент: ATMEGA162

Скачать:  PDF   ZIP

Document Outline

2513FAVR12/03
Features
High-performance, Low-power AVR
8-bit Microcontroller
Advanced RISC Architecture
131 Powerful Instructions Most Single-clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
Non-volatile Program and Data Memories
16K Bytes of In-System Self-programmable Flash
Endurance: 10,000 Write/Erase Cycles
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
1K Bytes Internal SRAM
Up to 64K Bytes Optional External Memory Space
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and
Capture Modes
Real Time Counter with Separate Oscillator
Six PWM Channels
Dual Programmable Serial USARTs
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
35 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, and 44-pad MLF
Operating Voltages
1.8 - 5.5V for ATmega162V
2.7 - 5.5V for ATmega162
Speed Grades
0 - 8 MHz for ATmega162V (see Figure 113 on page 265)
0 - 16 MHz for ATmega162 (see Figure 114 on page 265)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega162
ATmega162V
2
ATmega162/V
2513FAVR12/03
Pin Configurations
Figure 1. Pinout ATmega162
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
(OC0/T0) PB0
(OC2/T1) PB1
(RXD1/AIN0) PB2
(TXD1/AIN1) PB3
(SS/OC3B) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
(TXD0) PD1
(INT0/XCK1) PD2
(INT1/ICP3) PD3
(TOSC1/XCK0/OC3A) PD4
(OC1A/TOSC2) PD5
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
VCC
PA0 (AD0/PCINT0)
PA1 (AD1/PCINT1)
PA2 (AD2/PCINT2)
PA3 (AD3/PCINT3)
PA4 (AD4/PCINT4)
PA5 (AD5/PCINT5)
PA6 (AD6/PCINT6)
PA7 (AD7/PCINT7)
PE0 (ICP1/INT2)
PE1 (ALE)
PE2 (OC1B)
PC7 (A15/TDI/PCINT15)
PC6 (A14/TDO/PCINT14)
PC5 (A13/TMS/PCINT13)
PC4 (A12/TCK/PCINT12)
PC3 (A11/PCINT11)
PC2 (A10/PCINT10)
PC1 (A9/PCINT9)
PC0 (A8/PCINT8)
PA4 (AD4/PCINT4)
PA5 (AD5/PCINT5)
PA6 (AD6/PCINT6)
PA7 (AD7/PCINT7)
PE0 (ICP1/INT2)
GND
PE1 (ALE)
PE2 (OC1B)
PC7 (A15/TDI/PCINT15)
PC6 (A14/TDO/PCINT14)
PC5 (A13/TMS/PCINT13)
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
VCC
(TXD0) PD1
(INT0/XCK1) PD2
(INT1/ICP3) PD3
(TOSC1/XCK0/OC3A) PD4
(OC1A/TOSC2) PD5
(WR) PD6 (RD) PD7
XT
AL2
XT
AL1 GND VCC
(A8/PCINT8) PC0 (A9/PCINT9) PC1
(A10/PCINT10) PC2 (A1
1/PCINT1
1) PC3
(TCK/A12/PCINT12) PC4
PB4 (SS/OC3B) PB3 (TXD1/AIN1) PB2 (RXD1/AIN0) PB1 (OC2/T1) PB0 (OC0/T0) GND VCC P
A0 (AD0/PCINT0)
P
A1 (AD1/PCINT1)
P
A2 (AD2/PCINT2)
P
A3 (AD3/PCINT3)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDIP
1
2
3
4
5
6
7
8
9
10
11
12 14 16 18 20 22
13 15 17 19 21
33
32
31
30
29
28
27
26
25
24
23
44 42 40 38 36 34
43 41 39 37 35
TQFP/MLF
NOTE:
MLF bottom pad should
be soldered to ground.
3
ATmega162/V
2513FAVR12/03
Overview
The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART0
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC
SPI
COMP.
INTERFACE
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
RESET
CONTROL
LINES
VCC
GND
PA0 - PA7
PC0 - PC7
PD0 - PD7
PB0 - PB7
AVR CPU
INTERNAL
CALIBRATED
OSCILLATOR
PORTE
DRIVERS/
BUFFERS
PORTE
DIGITAL
INTERFACE
PE0 - PE2
USART1
4
ATmega162/V
2513FAVR12/03
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega162 provides the following features: 16K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an
external memory interface, 35 general purpose I/O lines, 32 general purpose working
registers, a JTAG interface for Boundary-scan, On-chip Debugging support and pro-
gramming, four flexible Timer/Counters with compare modes, internal and external
interrupts, two serial programmable USARTs, a programmable Watchdog Timer with
Internal Oscillator, an SPI serial port, and five software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register con-
tents but freezes the Oscillator, disabling all other chip functions until the next interrupt
or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the crystal/resonator Oscillator is running while the rest of the device is
sleeping. This allows very fast start-up combined with low-power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer con-
tinue to run.
The device is manufactured using Atmel's high density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer, or
by an On-chip Boot Program running on the AVR core. The Boot Program can use any
interface to download the Application Program in the Application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is
a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega162 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-
cuit Emulators, and evaluation kits.
ATmega161 and
ATmega162
Compatibility
The ATmega162 is a highly complex microcontroller where the number of I/O locations
supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-
ward compatibility with the ATmega161, all I/O locations present in ATmega161 have
the same locations in ATmega162. Some additional I/O locations are added in an
Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM
space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD
instructions only, not by using IN and OUT instructions. The relocation of the internal
RAM space may still be a problem for ATmega161 users. Also, the increased number of
Interrupt Vectors might be a problem if the code uses absolute addresses. To solve
these problems, an ATmega161 compatibility mode can be selected by programming
the fuse M161C. In this mode, none of the functions in the Extended I/O space are in
use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vec-
tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can
replace the ATmega161 on current Printed Circuit Boards. However, the location of
Fuse bits and the electrical characteristics differs between the two devices.
5
ATmega162/V
2513FAVR12/03
ATmega161 Compatibility
Mode
Programming the M161C will change the following functionality:
The extended I/O map will be configured as internal RAM once the M161C Fuse is
programmed.
The timed sequence for changing the Watchdog Time-out period is disabled. See
"Timed Sequences for Changing the Configuration of the Watchdog Timer" on page
55 for details.
The double buffering of the USART Receive Registers is disabled. See "AVR
USART vs. AVR UART Compatibility" on page 167 for details.
Pin change interrupts are not supported (Control Registers are located in Extended
I/O).
One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.
Note that the shared UBRRHI Register in ATmega161 is split into two separate registers
in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be
affected by the ATmega161 compatibility fuse.
Pin Descriptions
VCC
Digital supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. When pins PA0 to PA7 are used as inputs and are externally
pulled low, they will source current if the internal pull-up resistors are activated. The Port
A pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Port A also serves the functions of various special features of the ATmega162 as listed
on page 71.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega162 as listed
on page 71.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running. If the JTAG interface is
enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-
vated even if a Reset occurs.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega162 as listed on page 74.