1
Features
0.6 m Drawn Gate Length (0.5 m Leff) Sea-of-Gates Architecture
with Triple-level Metal
5.0V, 3.3V and 2.0V Operation including Mixed Voltages
On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and
Manage Chip-to-Chip Clock Skew
Compiled (Gate Level) and Embedded (Custom) SRAMs, ROM, and CAMs Available
PCI, SCSI and High Speed (250 MHz) Buffers Available
Easy Alternative Sourcing of Existing ASIC, FPGA and PLD Designs
Design-for-Test Methods, Including JTAG, Serial and Boundary Scan and ATPG
High Output Drive Capability: Up to 48 mA with Slew Rate Control
Description
Atmel's next generation ATL60 Series CMOS ASICs are fabricated using a 0.6m
drawn gate, oxide isolated, triple-level metal process. Extensive cell libraries are avail-
able and support the major CAD software tools. As with all Atmel ASIC families,
customer involvement and satisfaction is integral to all steps of the design flow. A vari-
ety of Design for Testability techniques are supported by the libraries, and a wide
range of packaging options are available. The ATLS version utilizes a fine pitch stag-
gered row on bond pads to achieve the smallest die size possible for a given pad
count. The ATLS60 is only available in a limited number of PQFP packages.
Note:
1. Nominal two input NAND gate with a fanout of 2 at 5.0 volts
Table 1. ATL60 Array Organization
Device
Number
Raw
Gates
Routable
Gates
Max Pin
Count
Max I/O
Pins
Gate
(1)
Speed
ATL60/4
4,000
3,000
44
36
200 ps
ATL60/15
15,000
10,000
68
60
200 ps
ATL60/25
25,000
16,900
84
76
200 ps
ATL60/40
38,000
25,400
100
92
200 ps
ATL60/60
58,000
34,600
120
112
200 ps
ATL60/85
86,000
51,900
144
136
200 ps
ATL60/110
110,000
65,900
160
152
200 ps
ATL60/150
149,000
89,300
184
176
200 ps
ATL60/200
195,000
116,900
208
200
200 ps
ATL60/235
232,000
139,500
226
218
200 ps
ATL60/300
301,000
181,000
256
248
200 ps
ATL60/435
430,000
260,000
304
296
200 ps
ATL60/550
545,000
288,000
340
332
200 ps
ATL60/700
693,000
363,000
380
372
200 ps
ATL60/870
870,000
456,000
424
416
200 ps
ATL60/1100
1,119,000
590,000
480
472
200 ps
ASIC
ATL 60 and
ATLS60 Series
Rev. 0388DASIC07/02
2
ATL60 and ATLS60 Series
0388DASIC07/02
Note:
1. Nominal two-input NAND gate with a fanout of 2 at 5.0 volts
Design
Design Systems
Supported
Atmel supports the major software systems for design with complete macro cell librar-
ies, as well as utilities for checking the netlist and accurate pre-route delay simulations.
Table 2. Design Systems Supported
ATLS60 Array Organization
Device
Number
Raw
Gates
Routable
Gates
Max Pin
Count
Max I/O
Pins
Gate
(1)
Speed
ATLS60/80
12,500
8,000
80
72
200 ps
ATLS60/100
20,400
13,000
100
92
200 ps
ATLS60/120
30,200
17,500
120
112
200 ps
ATLS60/144
44,600
26,000
144
136
200 ps
ATLS60/160
55,300
32,500
160
152
200 ps
ATLS60/208
96,500
57,000
208
200
200 ps
ATLS60/225
113,500
67,500
225
217
200 ps
ATLS60/256
148,200
88,000
256
248
200 ps
System
Tools
Version
Cadence
Design
Systems, Inc.
Opus
TM
Schematic and Layout
NC Verilog
TM
Verilog Simulator
Pearl
TM
Static Path
Verilog-XL
TM
Verilog Simulator
BuildGates
TM
Synthesis (Ambit)
4.46
3.3-s008
4.3-s095
3.3-s006
4.0-p003
Mentor
Graphics
ModelSim
Verilog and VHDL (VITAL) Simulator
Leonardo Spectrum
TM
Logic Synthesis
5.5e
2001.1d
Synopsys
TM
Design Compiler
TM
Synthesis
DFT Compiler 1-Pass Test Synthesis
BSD Compiler Boundary Scan Synthesis
TetraMax
Automatic Test Pattern Generation
PrimeTime
TM
Static Path
VCS
TM
Verilog Simulator
Floorplan Manager
TM
01.01-SP1
01.08-SP1
01.08-SP1
01.08
01.08-SP1
5.2
01.08-SP1
Novas
Software, Inc.
Debussy
5.1
Silicon
Perspective
TM
First Encounter
v2001.2.3
3
ATL60 and ATLS60 Series
0388DASIC07/02
Design Flow
Atmel provides three methods for implementing an ASIC design while maintaining the
same basic design flow for each method. This flow involves both the customer and
Atmel at all critical review and acceptance steps, as shown on the following page. Data-
base Acceptance occurs when Atmel receives and accepts the complete design
database.
Upon completion of this critical step, Atmel performs physical place-and-route. Func-
tional and timing simulations are performed, based on the physical design, including the
generation of a back annotation report to provide the customer with the most accurate
timing information available. Final Design Review is the last step of the design flow prior
to generation of masks. After this acceptance step is completed, masks are generated
and released, and prototype parts in ceramic packages are delivered.
4
ATL60 and ATLS60 Series
0388DASIC07/02
ASIC Design Flow
Rev.2.3-04/02
Synthesis, Translation or Conversion
Customer
(1)
Atmel
(1)
Kickoff Meeting
(2)
Customer
Atmel
Notes:
1) Performed by the customer or optionally by Atmel
2) ISO 9001/QS9000 Milestone
Final Database Submission
Customer
(1)
Atmel
(1)
Database Acceptance
(2)
Physical Design and Verification
Final Design Review
(2)
Prototype Delivery
(2)
Customer
Customer
Atmel
Atmel
Atmel
Customer
Database Submission for Underlayer
Atmel
Customer
Underlayer Acceptance and Tapeout
Atmel
Customer
5
ATL60 and ATLS60 Series
0388DASIC07/02
Pin Definition
Requirements
Within the Physical Design step (i.e., layout), certain restrictions apply during pin defini-
tion. The corner pins on each die are reserved and programmable for power and ground
only. All other buffer pins are fully programmable as input, output, bidirectional, clock-
into-array, power, or ground.
Design Options
Logic Synthesis
Atmel can accept Register Transfer Level (RTL) designs for VHDL (MIL-STD-454, IEEE
STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL simulation
as well as synthesis. VHDL or Verilog-HDL is Atmel's preferred method of performing an
ASIC design.
ASIC Design Translation
Atmel has successfully translated dozens of existing designs from most major ASIC
vendors into our ASICs. These designs have been optimized for speed and gate count
and modified to add logic or memory, or replicated for a pin-for-pin compatible, drop-in
replacement.
FPGA and PLD
Conversions
Atmel has successfully translated existing FPGA/PLD designs from most major vendors
into our ASICs. There are four primary reasons to convert from an FPGA/PLD to an
ASIC. Conversion of high-volume devices (over 10,000 units) for a single or combined
design is cost effective. Performance can often be optimized for speed or power con-
sumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost
while reducing on-board space requirements. Finally, in situations where an FPGA/PLD
was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for
long-term volume production.
PDF 
ZIP