1
Features
Low-Voltage and Standard-Voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
2.5 (V
CC
= 2.5V to 5.5V)
3-Wire Serial Interface
2 MHz Clock Rate (5V) Compatibility
Self-Timed Write Cycle (10 ms max)
High Reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
ESD Protection: > 4,000V
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP, 8-Pin JEDEC SOIC, and 8-Pin TSSOP Packages
Description
The AT93C46A provides 1024 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-
mized for use in many industrial and commercial applications where low power and
low voltage operation are essential. The AT93C46A is available in space saving 8-pin
PDIP, 8-pin JEDEC, and 8-Pin TSSOP packages.
The AT93C46A is enabled through the Chip Select pin (CS), and accessed via a 3-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely self-
timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought "high" following the initiation of a WRITE cycle, the DO pin outputs the
READY/BUSY status of the part.
3-Wire
Serial EEPROM
1K (64 x 16)
AT93C46A
Rev. 0539C07/98
3-Wire, 1K
Serial E
2
PROM
Pin Configurations
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
NC
No Connect
DC
Don't Connect
8-Pin PDIP
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
8-Pin SOIC
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
8-Pin TSSOP
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
AT93C46A
2
The AT93C46A is available in 4.5V to 5.5V, 2.7V to 5.5V,
and 2.5V to 5.5V versions.
Block Diagram
Note:
1. This parameter is characterized and is not 100% tested.
Absolute Maximum Ratings*
Operating Temperature .................................. -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65
C to +150
C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Test Conditions
Max
Units
Conditions
C
OUT
Output Capacitance (DO)
5
pF
V
OUT
= 0V
C
IN
Input Capacitance (CS, SK, DI)
5
pF
V
IN
= 0V
AT93C46A
3
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40
C to +85
C, V
CC
= +2.5V to +5.5V,
T
AC
= 0
C to +70
C, V
CC
= +2.5V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.5
5.5
V
V
CC3
Supply Voltage
2.7
5.5
V
V
CC4
Supply Voltage
4.5
5.5
V
I
CC
Supply Current
V
CC
= 5.0V
READ at 1.0 MHz
0.5
2.0
mA
WRITE at 1.0 MHz
0.5
2.0
mA
I
SB1
Standby Current
V
CC
= 2.5V
CS = 0V
14.0
20.0
A
I
SB2
Standby Current
V
CC
= 2.7V
CS = 0V
14.0
20.0
A
I
SB3
Standby Current
V
CC
= 5.0V
CS = 0V
35.0
50.0
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
0.1
1.0
A
I
OL
Output Leakage
V
IN
= 0V to V
CC
0.1
1.0
A
V
IL1
(1)
V
IH1
(1)
Input Low Voltage
Input High Voltage
4.5V
V
CC
5.5V
-0.6
2.0
0.8
V
CC
+ 1
V
V
IL2
(1)
V
IH2
(1)
Input Low Voltage
Input High Voltage
1.8V
V
CC
2.7V
-0.6
V
CC
x 0.7
V
CC
x 0.3
V
CC
+ 1
V
V
OL1
V
OH1
Output Low Voltage
Output High Voltage
4.5V
V
CC
5.5V
I
OL
= 2.1 mA
0.4
V
I
OH
= -0.4 mA
2.4
V
V
OL2
V
OH2
Output Low Voltage
Output High Voltage
1.8V
V
CC
2.7V
I
OL
= 0.15 mA
0.2
V
I
OH
= -100
A
V
CC
- 0.2
V
AC Characteristics
Applicable over recommended operating range from T
A
= -40
C to + 85
C, V
CC
= +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
f
SK
SK Clock Frequency
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
0
0
0
0
2
1
0.5
0.25
MHz
t
SKH
SK High Time
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
250
250
500
1000
ns
t
SKL
SK Low Time
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
250
250
500
1000
ns
t
CS
Minimum CS Low Time
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
250
250
500
1000
ns
AT93C46A
4
Note:
1. This parameter is characterized and is not 100% tested.
t
CSS
CS Setup Time
Relative to SK
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
50
50
100
200
ns
t
DIS
DI Setup Time
Relative to SK
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
100
100
200
400
ns
t
CSH
CS Hold Time
Relative to SK
0
ns
t
DIH
DI Hold Time
Relative to SK
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
100
100
200
400
ns
t
PD1
Output Delay to `1'
AC Test
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
250
250
500
1000
ns
t
PD0
Output Delay to `0'
AC Test
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
250
250
500
1000
ns
t
SV
CS to Status Valid
AC Test
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
250
250
500
1000
ns
t
DF
CS to DO in High Impedance
AC Test
CS = V
IL
4.5V
V
CC
5.5V
2.7V
V
CC
5.5V
2.5V
V
CC
5.5V
1.8V
V
CC
5.5V
100
100
200
400
ns
t
WP
Write Cycle Time
0.1
10
ms
4.5V
V
CC
5.5V
1
ms
Endurance
(1)
5.0V, 25
C, Page Mode
1M
Write
Cycle
Instruction Set for the AT93C46A
Instruction
SB
Op Code
Address
Comments
x 16
READ
1
10
A
5
- A
0
Reads data stored in memory, at specified address.
EWEN
1
00
11XXXX
Write enable must precede all programming modes.
ERASE
1
11
A
5
- A
0
Erase memory location A
n
- A
0
.
WRITE
1
01
A
5
- A
0
Writes memory location A
n
- A
0
.
ERAL
1
00
10XXXX
Erases all memory locations. Valid only at V
CC
= 4.5V to 5.5V.
WRAL
1
00
01XXXX
Writes all memory locations. Valid only at V
CC
= 4.5V to 5.5V.
EWDS
1
00
00XXXX
Disables all programming instructions.
AC Characteristics (Continued)
Applicable over recommended operating range from T
A
= -40
C to + 85
C, V
CC
= +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
AT93C46A
5
Functional Description
The AT93C46A is accessed via a simple and versatile
three-wire serial communication interface. Device opera-
tion is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge
of CS and consists of a Start Bit (logic `1') followed by the
appropriate Op Code and the desired memory Address
location.
READ (READ):
The Read (READ) instruction contains
the Address code for the memory location to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris-
ing edges of serial clock SK. It should be noted that a
dummy bit (logic `0') precedes the 16-bit data output string.
ERASE/WRITE (EWEN):
To assure data integrity, the
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program-
ming remains enabled until an Erase/Write Disable
(EWDS) instruction is executed or V
CC
power is removed
from the part.
ERASE (ERASE):
The Erase (ERASE) instruction pro-
grams all bits in the specified memory location to the logical
`1' state. The self-timed erase cycle starts once the ERASE
instruction and address are decoded. The DO pin outputs
the READY/BUSY status of the part if CS is brought high
after being kept low for a minimum of 250 ns (t
CS
). A logic
`1' at pin DO indicates that the selected memory location
has been erased, and the part is ready for another instruc-
tion.
WRITE (WRITE):
The Write (WRITE) instruction contains
the 16 bits of data to be written into the specified memory
location. The self-timed programming cycle, t
WP
, starts after
the last bit of data is received at serial data input pin DI.
The DO pin outputs the READY/BUSY status of the part if
CS is brought high after being kept low for a minimum of
250 ns (t
CS
). A logic `0' at DO indicates that programming is
still in progress. A logic `1' indicates that the memory loca-
tion at the specified address has been written with the data
pattern contained in the instruction and the part is ready for
further instructions. A READY/BUSY status cannot be
obtained if the CS is brought high after the end of the
self-timed programming cycle, t
WP
.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction
programs every bit in the memory array to the logic `1' state
and is primarily used for testing purposes. The DO pin out-
puts the READY/BUSY status of the part if CS is brought
high after being kept low for a minimum of 250 ns (t
CS
). The
ERAL instruction is valid only at V
CC
= 5.0V
10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction
programs all memory locations with the data patterns spec-
i f i e d i n t h e i n s t r u c t i o n . T h e D O p i n o u t p u t s t h e
READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (t
CS
). The WRAL
instruction is valid only at V
CC
= 5.0V
10%.
ERASE/WRITE DISABLE (EWDS):
To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
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