AT89S4D12

4-281

Features

Compatible with MCS-51

Products

128K Bytes of In-System Reprogrammable Flash data memory and 4K Bytes of
Downloadable Flash Program Memory

Endurance: 1,000 Write/Erase Cycles per Sector
Data Retention: 10 Years

Sector Programming: 128 Bytes/Sector

Single 3.3V

±
±
±
±

10% Supply

On-Chip 12 MHz oscillator

Two-Level Program Memory Lock

256-Bytes Internal RAM

5 Programmable I/O Lines

Serial Peripheral Interface (SPI) Channel

Serial Program Downloading

Dual Data Pointer Registers

Description

The AT89S4D12 is a low-voltage, highly integrated CMOS 8-bit microcomputer with
4K bytes of downloadable Flash program memory and 128K bytes of in-system repro-
grammable Flash data memory. The device is manufactured using Atmel's high den-
sity Flash memory technology and is compatible with the industry-standard MCS-51

instruction set.

The 128K bytes of on-chip Flash data memory are accessed as two 64K byte blocks.
Bit 0 at SFR location 96H is used to select the active block. The MOVX instruction is
used to read and write the data memory. Both the program and data memory arrays
can be programmed by an external programmer.

The downloadable Flash can be changed one page (128 bytes) at a time and is
accessible through the SPI serial peripheral interface port. Holding RESET active
forces the SPI bus into a slave input mode and allows the program memory to be writ-
ten-from or read-to unless Lock Bit 2 has been activated.

The functional operations of the 128K bytes Flash data memory are equivalent to
those on the AT29LV010A 1M Bit Flash memory device.

0921A-A12/97

8-Bit
Microcontroller
with
132K Bytes
Flash Data
Memory

AT89S4D12

SOIC Top View

GND

TEST1

RESET

SDI/P1.1

SDO/P1.0

TEST2

VCC

P1.2/DTR

P1.3/SCK

P1.4/DSR

PLCC Top View

P1.0/SDO

TEST2

P1.4/DSR

P1.1/SDI

RESET

TEST1

GND

VCC

P1.2/DTR

P1.3/SCK

Pin Configurations

AT89S4D12

4-283

Pin Description

Supply voltage.

GND
Ground.

Port 1
Port 1 is a 5-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

In addition, P1.0, P1.1, and P1.3 can be configured as the
SPI data output, data input and shift clock input pins, as
shown in the following table.

RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

TEST1
TEST1 is set to V

during downloading of the Flash pro-

gram or data memory. This pin can be left unconnected or
tied to ground during normal operation.

TEST2
Test input. This pin has no user available function and can
be left unconnected or tied to ground.

Special Function Registers

A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.

User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.

Memory Control Register The MCON register contains
the RDY/BSY flag and the most significant Flash address
bit A16, for the 128K bytes of on-chip Flash data memory.

SPI Registers Control and status bits for the Serial Periph-
eral Interface are contained in registers SPCR (shown in
Table 3) and SPSR (shown in Table 4). The SPI data bits
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff-
ered for writing and the values in SPDR are not changed by
Reset.

Dual Data Pointer Registers To facilitate data transfer,
two banks of 16-bit Data Pointer Registers are provided:
DP0 at SFR address locations 82H - 83H and DP1 at 84H -
85H. Bit DPS = 0 in SFR MCON selects DP0 and DPS = 1
selects DP1. The user should always initialize the DPS bit
to the appropriate value before accessing the respective
Data Pointer register.

Port Pin

Alternate Functions

P1.0

SDO (data output pin for SPI channel)

P1.1

SDI (data input pin for SPI channel)

P1.3

SCK (clock input pin for SPI channel)

AT89S4D12

4-285

Table 2. MCON--Memory Control Register

Table 3. SPCR--SPI Control Register

MCON Address = 96H

Reset Value = XXXX X010B

DPS

RDY/BSY

A16

Bit

Symbol Function

DPS

Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register,
DP0, and DPS = 1 selects the second bank, DP1.

RDY/BSY

DataFlash Ready/Busy Flag. This bit serves as the RDY/BSY flag in a Read-Only mode
during DataFlash write. RDY/BSY = 1 means that the DataFlash is ready to be
programmed. While programming operations are being executed, the RDY/BSY bit
equals `0' and is automatically reset to `1' when programming is completed.

A16

Memory Block Select. A16 = 0 selects the lower 64K bytes DataFlash memory block.
A16 = 1 selects the upper 64K bytes DataFlash block.

SPCR Address = D5H

Reset Value = 000X 01XXB

SPIE

SPE

DORD

CPOL

CPHA

SPR1

SPR0

Bit

Symbol Function

SPIE

SPI Interrupt Enable. This bit, enables SPI interrupts: SPIE = 1 enable SPI interrupts. SPIE = 0 disables
SPI interrupts.

SPE

SPI Enable. SPI = 1 enables the SPI channel and connects SDO, SDI and SCK to pins P1.0, P1.1, and
P1.3. SPI = 0 disables the SPI channel.

DORD

Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data
transmission.

CPOL

Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is
low when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.

CPHA

Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between
master and slave. Please refer to figure on SPI Clock Phase and Polarity Control.

SPR0
SPR1

SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1
and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency,
F

OSC

., is as follows:

SPR1
0
0
1
1

SPR0
0
1
0
1

SCK = F

OSC

. divided by

4
16
64
128

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