4-45
Features
Compatible with MCS-51TM Products
4K Bytes of Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
2.7V to 6V Operating Range
Fully Static Operation: 0 Hz to 12 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
Description
The AT89LV51 is a low-voltage, high-performance CMOS 8-bit microcomputer with
4K bytes of Flash Programmable and Erasable Read Only Memory. The device is
manufactured using Atmel's high density nonvolatile memory technology and is com-
patible with the industry standard MCS-51TM instruction set and pinout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conven-
tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89LV51 is a powerful microcomputer which pro-
vides a highly flexible and cost effective solution to many embedded control applica-
tions. The AT89LV51 operates at 2.7 volts up to 6.0 volts.
TQFP
2 3
1
I N D E X
C O R N E R
3 4
P1.0
VCC
P1.1
P1.2
P1.4
P1.3
NC
4 2
4 3
4 0
4 1
6
5
4
4 4
3
2
2 6
2 5
2 8
2 7
2 4
1 8
1 9
2 0
2 1
2 2
P 1 . 7
P 1 . 6
P 1 . 5
N C
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
2 9
3 0
3 9
3 8
3 7
3 6
3 5
3 3
3 2
3 1
N C
P S E N
XT
AL1
GND
XT
AL2
GND
P0.0
(AD0)
A L E / P R O G
()
P
3
.
7
RD
E A / V P P
()
P
3
.
6
WR
( R X D )
P 3 . 0
P 0 . 7
( A D 7 )
P 2 . 6
( A 1 4 )
P 0 . 6
( A D 6 )
P 0 . 5
( A D 5 )
P 0 . 4
( A D 4 )
P0.3
(AD3)
P0.2
(AD2)
P0.1
(AD1)
(
)
P 3 . 2
I N T 0
( T X D )
P 3 . 1
( T 1 )
P 3 . 5
(
)
P 3 . 3
I N T 1
( T 0 )
P 3 . 4
P 2 . 7
( A 1 5 )
(A11)
P2.3
(A12)
P2.4
(A10)
P2.2
(A
9)
P
2
.1
(A
8)
P
2
.0
R S T
P 2 . 5
( A 1 3 )
PDIP
P 1 . 0
V
C C
P 1 . 1
P 0 . 0
( A D 0 )
P 1 . 2
(
)
P 3 . 2
I N T 0
A L E / P R O G
(
)
P 3 . 7
R D
P 2 . 3
( A 1 1 )
( T X D )
P 3 . 1
E A / V P P
(
)
P 3 . 6
W R
P 2 . 4
( A 1 2 )
( R X D )
P 3 . 0
P 0 . 7
( A D 7 )
( T 1 )
P 3 . 5
P 2 . 6
( A 1 4 )
R S T
P 0 . 6
( A D 6 )
P 1 . 7
P 0 . 5
( A D 5 )
P 1 . 6
P 0 . 4
( A D 4 )
P 1 . 5
P 0 . 3
( A D 3 )
P 1 . 4
P 0 . 2
( A D 2 )
P 1 . 3
P 0 . 1
( A D 1 )
(
)
P 3 . 3
I N T 1
P S E N
X TA L 2
P 2 . 2
( A 1 0 )
( T 0 )
P 3 . 4
P 2 . 7
( A 1 5 )
X TA L 1
P 2 . 1
( A 9 )
G N D
P 2 . 0
( A 8 )
P 2 . 5
( A 1 3 )
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 1
2 2
2 3
2 4
2 5
2 6
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
PLCC
P1.0
VCC
P1.1
P0.0
(AD0)
P1.2
A L E / P R O G
()
P
3
.
7
RD
XT
AL1
E A / V P P
()
P
3
.
6
WR
GND
( R X D )
P 3 . 0
P 0 . 7
( A D 7 )
P 2 . 6
( A 1 4 )
P 0 . 6
( A D 6 )
P 0 . 5
( A D 5 )
P 0 . 4
( A D 4 )
P0.3
(AD3)
P1.4
P0.2
(AD2)
P1.3
P0.1
(AD1)
P S E N
XT
AL2
(
)
P 3 . 2
I N T 0
( T X D )
P 3 . 1
( T 1 )
P 3 . 5
(
)
P 3 . 3
I N T 1
( T 0 )
P 3 . 4
P 2 . 7
( A 1 5 )
(A11)
P2.3
(A12)
P2.4
(A10)
P2.2
(A
9)
P
2
.1
(A
8)
P
2
.0
NC
2 3
1
R S T
P 1 . 7
P 1 . 6
P 1 . 5
I N D E X
C O R N E R
N C
NC
P 2 . 5
( A 1 3 )
3 4
N C
4 2
4 3
4 0
4 1
6
5
4
4 4
3
2
2 6
2 5
2 8
2 7
1 8
1 9
2 0
2 4
2 1
2 2
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
2 9
3 0
3 9
3 8
3 7
3 6
3 5
3 3
3 2
3 1
8-Bit
Microcontroller
with 4K Bytes
Flash
AT89LV51
Pin Configurations
0303D-D12/97
(continued)
AT89LV51
4-46
Block Diagram
AT89LV51
4-47
The AT89LV51 provides the following standard features:
4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-
bit timer/counters, a five vector two-level interrupt architec-
ture, a full duplex serial port, on-chip oscillator and clock
circuitry. In addition, the AT89LV51 is designed with static
logic for operation down to zero frequency and supports
two software selectable power saving modes. The Idle
M o d e s t o p s t h e C P U w h i l e a l l o w i n g t h e R A M ,
timer/counters, serial port and interrupt system to continue
functioning. The Power Down Mode saves the RAM con-
tents but freezes the oscillator disabling all other chip func-
tions until the next hardware reset.
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode P0 has internal pul-
lups.
Port 0 also receives the code bytes during Flash program-
ming, and outputs the code bytes during program verifica-
tion. External pullups are required during program verifica-
tion.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application it uses strong internal pullups
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
IL
) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89LV51 as listed below:
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash
programming.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency, and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external Data Mem-
ory.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT89LV51 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
AT89LV51
4-48
EA/V
PP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to V
CC
for internal program execu-
tions.
This pin also receives the 12-volt programming enable volt-
age (V
PP
) during Flash programming, when 12-volt pro-
gramming is selected.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89LV51 operate the same
way as Timer 0 and Timer 1 in the AT89C51.
Table 1. AT89LV51 SFR Map and Reset Values
0F8H
0FFH
0F0H
B
00000000
0F7H
0E8H
0EFH
0E0H
ACC
00000000
0E7H
0D8H
0DFH
0D0H
PSW
00000000
0D7H
0C8H
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0CFH
0C0H
0C7H
0B8H
IP
XX000000
0BFH
0B0H
P3
11111111
0B7H
0A8H
IE
0X000000
0AFH
0A0H
P2
11111111
0A7H
98H
SCON
00000000
SBUF
XXXXXXXX
9FH
90H
P1
11111111
97H
88H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
8FH
80H
P0
11111111
SP
00000111
DPL
00000000
DPH
00000000
PCON
0XXX0000
87H
AT89LV51
4-49
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before V
CC
is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Figure 1. Oscillator Connections
Note:
C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Status of External Pins During Idle and Power Down Modes
C2
XTAL2
GND
XTAL1
C1
XTAL2
XTAL1
GND
NC
EXTERNAL
OSCILLATOR
SIGNAL
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
PDF 
ZIP