1
Features
32-Mbit Flash and 4-Mbit/8-Mbit PSRAM
Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
2.7V to 3.3V Operating Voltage
Flash
32-megabit (2M x 16)
2.7V to 3.3V Read/Write
Access Time 70 ns
Sector Erase Architecture
Sixty-three 32K Word Sectors with Individual Write Lockout
Eight 4K Word Sectors with Individual Write Lockout
Fast Word Program Time 15 s
Suspend/Resume Feature for Erase and Program
Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
12 mA Active
13 A Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
PSRAM
8-megabit (512K x 16)
2.7V to 3.3V V
CC
70 ns Access Time
Extended Temperature Range
ISB0 < 10 A when Deep Power-Down
Device Number
Flash Boot
Location
Flash Plane
Configuration
PSRAM
Configuration
AT52BC3221A
Bottom
32M (2M x 16)
8M (512K x 16)
AT52BC3221AT
Top
32M (2M x 16)
8M (512K x 16)
32-Mbit Flash +
8-Mbit PSRAM
Stack Memory
AT52BC3221A
AT52BC3221AT
Preliminary
Rev. 3466ASTKD11/04
2
AT52BC3221A(T)
3466ASTKD11/04
Pin Configuration
CBGA (Top View)
Pin Name
Function
A0 - A18, A19 - A20
Common Address Input for 8M PSRAM/Flash, Flash Address Input
CE
Flash Chip Enable
OE
Flash Output Enable
WE
Flash Write Enable
RESET
Flash Reset
RDY/BUSY
Flash READY/BUSY Output
VPP
Flash Power Supply for Accelerated Program/Erase Operations
VCC
Flash Power
GND
Flash Ground
I/O0 - I/O15
Data Inputs/Outputs
NC
No Connect
PLB
PSRAM Lower Byte
PUB
PSRAM Upper Byte
PVCC
PSRAM Power
PGND
PSRAM Ground
PCS1
PSRAM Chip Select 1
ZZ
Low Power Modes
PWE
PSRAM Write Enable
POE
PSRAM Output Enable
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
NC
A20
A16
WE
PGND
NC
PLB
A18
NC
A11
A8
RDY/BUSY
RESET
VPP
PUB
A17
A5
A15
A10
A19
POE
A7
A4
A14
A9
I/O11
A6
A0
A13
I/O15
I/O13
I/O12
I/O9
A3
CE
A12
PWE
I/O6
ZZ
I/O10
I/O8
A2
GND
GND
I/O14
I/O4
PVCC
I/O2
I/O0
A1
OE
NC
I/O7
I/O5
VCC
I/O3
I/O1
PCS1
NC
NC
NC
NC
NC
3
AT52BC3221A(T)
3466ASTKD11/04
Block Diagram
Description
The AT52BC3221A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit PSRAM
(organized as 512K x 16) in a stacked 66-ball CBGA package. The stacked modules operate
at 2.7V to 3.3V in the extended temperature range.
32-Mbit
FLASH
4/8-Mbit
PSRAM
ADDRESS
DATA
RESET
CE
RDY/BUSY
PCS1
ZZ
WE
PWE
POE
OE
Absolute Maximum Ratings
Temperature under Bias................................... -25
C to +85C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -55
C to +150C
All Input Voltages
except V
PP
(including NC Pins)
with Respect to Ground ..............................-0.2V to V
CC
+0.3V
Voltage on V
PP
with Respect to Ground ..................................-0.2V to + 6.25V
All Output Voltages
with Respect to Ground ..............................-0.2V to V
CC
+0.3V
DC and AC Operating Range
Operating Temperature (Case)
-25
C - 85C
V
CC
Power Supply
2.7V to 3.3V
4
AT52BC3221A(T)
3466ASTKD11/04
32-megabit
Flash Memory
Description
The 32-megabit Flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each.
The memory is divided into 71 sectors for erase operations. The device has CE and OE con-
trol signals to avoid any bus contention. This device can be read or reprogrammed using a
single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see "Sector Lockdown" section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by
the toggle bit.
The VPP pin provides data protection. When the V
PP
input is below 0.4V, the program and
erase functions are inhibited. When V
PP
is at 0.9V or above, normal program and erase opera-
tions can be performed.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back
to V
CC
. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not
work while in this mode; if entered they will result in data being programmed into the device. It
is not recommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
Block Diagram
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
INPUT
BUFFER
COMMAND
REGISTER
DATA
REGISTER
Y-GATING
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
RDY/BUSY
VPP
VCC
GND
Y-DECODER
X-DECODER
INPUT
BUFFER
ADDRESS
LATCH
I/O0 - I/O15
A0 - A20
MAIN
MEMORY
5
AT52BC3221A(T)
3466ASTKD11/04
Device
Operation
READ: The 32-Mbit Flash memory is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE
is high. This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the "Command Definition in Hex" table on page 12 (I/O8 - I/O15 are
don't care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical "1". The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t
EC
.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sec-
tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is t
SEC
. When the sec-
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper-
ation terminating immediately.
WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0")
on a word-by-word basis. Programming is accomplished via the internal device command reg-
ister and is a four-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase
operations can convert "0"s to "1"s. Programming is completed after the specified t
BP
cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a "1", the device was not able to verify that the
erase or program operation was performed successfully.
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