1
DIP Top View
4-Megabit
(512K x 8)
5-volt Only
CMOS
Flash Memory
AT49F040
AT49F040T
AT49F040/040T
Features
Single Voltage Operation
5V Read
5V Reprogramming
Fast Read Access Time - 70 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte By Byte Programming - 50
s/Byte
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
50 mA Active Current
100
A CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is
organized as 524,288 words by 8 bits. Manufactured with Atmel's advanced nonvola-
tile CMOS technology, the device offers access times to 70 ns with power dissipation
of just 275 mW over the commercial temperature range. When the device is dese-
lected, the CMOS standby current is less than 100
A.
The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49F040 locates the boot block at lowest order
addresses ("bottom boot"); the AT49F040T locates it at highest order addresses ("top
boot").
Rev. 0998A-A01/98
AT49F040/040T
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
PLCC Top View
TSOP Top View
Type 1
(continued)
AT49F040/040T
2
To allow for simple in-system reprogrammability, the
AT49F040 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F040 is performed by erasing
the entire 4 megabits of memory and then programming on
a byte by byte basis. The byte programming time is a fast
50
s. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49F040 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
ERASURE: Before a byte can be reprogrammed, the
512K bytes memory array (or 496K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical "1". The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is erased,
the device is programmed (to a logical "0") on a byte-by-
byte basis. Please note that a data "0" cannot be pro-
grammed back to a "1"; only erase operations can convert
"0"s to "1"s. Programming is accomplished via the internal
device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the AT49F040
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(496K BYTES)
OE
WE
CE
ADDRESS
INPUTS
V
CC
GND
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
03FFFH
00000H
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(496K BYTES)
7C000H
00000H
AT49F040T
AT49F040
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
7FFFFH
7FFFFH
AT49F040/040T
3
boot block is 00000H to 03FFFH while the address range
of the AT49F040T boot block is 7C000H to 7FFFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F040 features DATA polling to
indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F040
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F040 in
the following ways: (a) V
CC
sense: if V
CC
is below 3.8V (typ-
ical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
AT49F040/040T
4
Notes:
1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F040 and 7C000H to 7FFFFH for the
AT49F040T.
2. Either one of the Product ID exit commands can be used.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
Addr
D
OUT
Chip Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
Byte Program
4
5555
AA
2AAA
55
5555
A0
Addr
D
IN
Boot Block Lockout
(1)
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID Entry
3
5555
AA
2AAA
55
5555
90
Product ID Exit
(2)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
(2)
1
XXXX
F0
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65
C to +150
C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
AT49F040/040T
5
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
0.5V.
4. Manufacturer Code: 1FH, Device Code: 13H (AT49F040), 12H (AT49F040T).
5. See details under Software Product Identification Entry/Exit.
Note:
1. In the erase mode, ICC is 90 mA.
DC and AC Operating Range
AT49F040-70
AT49F040-90
AT49F040-12
Operating
Temperature (Case)
Com.
0
C - 70
C
0
C - 70
C
0
C - 70
C
Ind.
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
V
CC
Power Supply
5V
10%
5V
10%
5V
10%
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
V
IL
V
IL
V
IH
Ai
D
OUT
Program
(2)
V
IL
V
IH
V
IL
Ai
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
X
High Z
Program Inhibit
X
X
V
IH
Program Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Product Identification
Hardware
V
IL
V
IL
V
IH
A1 - A18 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
Manufacturer Code
(4)
A1 - A18 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
Device Code
(4)
Software
(5)
A0 = V
IL
, A1 - A18 = V
IL
Manufacturer Code
(4)
A0 = V
IH
, A1 - A18 = V
IL
Device Code
(4)
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
10
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
A
I
SB1
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
Com.
100
A
Ind.
300
A
I
SB2
V
CC
Standby Current TTL
CE = 2.0V to V
CC
3
mA
I
CC
(1)
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA
50
mA
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
.45
V
V
OH1
Output High Voltage
I
OH
= -400
A
2.4
V
V
OH2
Output High Voltage CMOS
I
OH
= -100
A; V
CC
= 4.5V
4.2
V
PDF 
ZIP