1
Features
Full Compliance with USB Spec Rev 1.1
Four Downstream Ports
Full-speed and Low-speed Data Transfers
Bus-powered Controller
Bus-powered or Self-powered Hub Operation
Per Port Overcurrent Monitoring
Individual Port Power Control
USB Connection Status Indicators
5V Operation with On-chip 3.3V Format
32-lead SOIC and LQFP
Overview
Introduction
The AT43312A is a 5 port USB hub chip supporting one upstream and four down-
stream ports. The AT43312A connects to an upstream hub or Host/Root Hub via Port0
and the other ports connect to external downstream USB devices. The hub re-trans-
mits the USB differential signal between Port0 and Ports[1:4] in both directions. A USB
hub with the AT43312A can operate as a bus-powered or self-powered through chip's
power mode configuration pin. In the self-powered mode, port power can be switched
or unswitched. Overcurrent reporting and port power control can be individual or glo-
bal. An on-chip power supply eliminates the need for an external 3.3V supply.
The AT43312A supports the 12-Mb/sec full speed as well as 1.5-Mb/sec slow speed
USB transactions. To reduce EMI, the AT43312A's oscillator frequency is 6 MHz even
though some internal circuitry operates at 48 MHz.
The AT43312A consists of a Serial Interface Engine, a Hub Repeater, and a Hub
Controller.
Self- and Bus-
powered USB
Hub Controller
AT43312A
Rev. 1255FUSB3/04
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PWR2
PWR3
PWR4
VCC5
VSS
OSC1
OSC2
LFT
TEST
OVC4
OVC3
OVC2
OVC1
LPSTAT
SELF/BUS
STAT4
PWR1
DP4
DM4
DP3
DM3
VSS
DP2
DM2
CEXT
DP1
DM1
DP0
DM0
STAT1
STAT2
STAT3
LQFP Top View
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DP3
DM4
DP4
PWR1
PWR2
PWR3
PWR4
VCC5
DMO
STAT1
STAT2
STAT3
STAT4
SELF/BUS
LPSTAT
OVC1
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
VSS
OSC1
OSC2
LFT
TEST
OVC4
OVC3
OVC2
DM3
VSS
DP2
DM2
CEXT
DP1
DM1
DP0
2
AT43312A
1255FUSB3/04
The Serial Interface Engine's
Tasks are:
Manage the USB communication protocol
USB signaling detection/generation
Clock/Data separation, data encoding/decoding, CRC generation/checking
Data serialization/de-serialization
The Hub Repeater is
Responsible for:
Providing upstream connectivity between the selected device and the Host
Managing connectivity setup and tear-down
Handling bus fault detection and recovery
Detecting connect/disconnect on each port
The Hub Controller is
Responsible for:
Hub enumeration
Providing configuration information to the Host
Providing status of each port to the Host
Controlling each port per Host command
Figure 1. Block Diagram
Note:
This document assumes that the reader is familiar with the Universal Serial Bus and
therefore only describes the unique features of the AT43312A chip. For detailed informa-
tion about the USB and its operation, the reader should refer to the Universal Serial Bus
Specification Version 1.1, September 23, 1998.
HUB
CONTROLLER
SERIAL
INTERFACE
ENGINE
HUB
REPEATER
ENDPOINT 0
ENDPOINT 1
PORT 1
PORT 2
PORT 3
PORT 4
TO DOWNSTREAM DEVICES
UPSTREAM PORT
PORT 0
5
AT43312A
1255FUSB3/04
Signal Description
OSC1
Oscillator Input. Input to the inverting 6 MHz oscillator amplifier.
OSC2
Oscillator Output. Output of the inverting oscillator amplifier.
LFT
PLL Filter. For proper operation of the PLL, this pin should be connected through a
2.2 nF capacitor in parallel with a 100
resistor in series with a 10 nF capacitor to
ground (VSS).
SELF/BUS
Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high
on this pin enables the self-powered mode, a low enables the bus-powered mode.
LPSTAT
Local Power Status. In the self-powered mode, this is an input pin that should be con-
nected to the local power supply through a 47 k
resistor. The voltage on this pin is
used by the chip for reporting the condition of the local power supply. In the bus-pow-
ered mode, this pin is not used.
DP0
Upstream Plus USB I/O. This pin should be connected to CEXT through an external
1.5 k
pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to
the Host Controller or an upstream Hub.
DM0
Upstream Minus USB I/O.
DP[1:4]
Port Plus USB I/O. This pin should be connected to VSS through an external 15 k
resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream
USB devices.
DM[1:4]
Port Minus USB I/O. This pin should be connected to VSS through an external 15 k
resistor
OVC[1:4]
Overcurrent. This is the input signal used to indicate to the AT43312A that an overcur-
rent is detected at the port. If OVCx is asserted, AT43312A will assert the PWRx pin and
report the status to the USB Host.
PWR[1:4]
Power Switch. This is an output signal used to enable or disable the external voltage
regulator supplying power to a port. PWRx is de-asserted when a power supply problem
is detected at OVCx.
STAT[1:4]
Connect Status. This is an output pin indicating that a port is properly connected. STATx
is asserted when the port is enabled.
CEXT
External Capacitor. For proper operation of the on chip regulator, a 0.27 F capacitor
must be connected to this pin.
TEST
Test. This pin should be connected to a logic high for normal operation.
VCC
5V Power Supply.
VSS
Ground.
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