Features
High Performance, Low Power AVR
32 32-Bit Microcontroller
133 MHz clock frequency
16 KB instruction cache and 16 KB data caches
Memory Management Unit enabling use of operating systems
Single-cycle RISC instruction set including SIMD and DSP instructions
Java Hardware Acceleration
Multimedia Co-Processor
Vector Multiplication Unit for video acceleration through color-space conversion
(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation
Multi-hierarchy bus system
High-performance data transfers on separate buses for increased performance
Data Memories
32KBytes SRAM
External Memory Interface
SDRAM, DataFlash
TM
, SRAM, Multi Media Card (MMC), Secure Digital (SD),
Compact Flash, Smart Media, NAND Flash,
Direct Memory Access Controller
External Memory access without CPU intervention
Interrupt Controller
Individually maskable Interrupts
Each interrupt request has a programmable priority and autovector address
System Functions
Power and Clock Manager
Crystal Oscillator with Phase-Lock-Loop (PLL)
Watchdog Timer
Real-time Clock
6 Multifunction timer/counters
Three external clock inputs, I/O pins, PWM, capture and various counting
capabilities
4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
115.2 kbps IrDA Modulation and Demodulation
Hardware and software handshaking
3 Synchronous Serial Protocol controllers
Supports I2S, SPI and generic frame-based protocols
Two-Wire Interface
Sequential Read/Write Operations, Philips' I2C compatible
Liquid Crystal Display (LCD) interface
Supports TFT displays
Configurable pixel resolution supporting QCIF/QVGA/VGA/SVGA configurations.
Image Sensor Interface
12-bit Data Interface for CMOS cameras
Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device
On-chip Transceivers with physical interface
2 Ethernet MAC 10/100 Mbps interfaces
802.3 Ethernet Media Access Controller
Supports Media Independent Interface (MII) and Reduced MII (RMII)
16-bit stereo audio DAC
Sample rates up to 50 kHz
On-Chip Debug System
Nexus Class 3
Full speed, non-intrusive data and program trace
Runtime control and JTAG interface
Package/Pins
256-ball CABGA 1.0mm pitch/160 GPIO pins
Power supplies
1.65V to1.95V VDDCORE
3.0V to 3.6V VDDIO
32003FSAVR3207/06
AVR
32 32-bit
Microcontroller
AT32AP7000
Preliminary
Summary
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
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32003FSAVR3207/06
AT32AP7000
1.
Part Description
The AT32AP7000 is a complete System-on-chip application processor with an AVR32 RISC
processor running at frequencies up to 133 MHz. AVR32 is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high application performance.
AT32AP7000 implements a Memory Management Unit (MMU) and a flexible interrupt controller
supporting modern operating systems and real-time operating systems. The processor also
includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom
applications.
AT32AP7000 incorporates SRAM memories on-chip for fast and secure access. For applica-
tions requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM
controller provides off-chip volatile memory access as well as controllers for all industry standard
off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital
(SD)-card, SmartCard, NAND Flash and Atmel DataFlashTM.
The Direct Memory Access controller for all the serial peripherals enables data transfer between
memories without processor intervention. This reduces the processor overhead when transfer-
ring continuous and large data streams between modules in the MCU.
The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform a wide range of functions including frequency measure-
ment, event counting, interval measurement, pulse generation, delay timing and pulse width
modulation.
AT32AP7000 also features an onboard LCD Controller, supporting single and double scan
monochrome and color passive STN LCD modules and single scan active TFT LCD modules.
On monochrome STN displays, up to 16 gray shades are supported using a time-based dither-
ing algorithm and Frame Rate Control (FRC) method. This method is also used in color STN
displays to generate up to 4096 colors.
The LCD Controller is programmable for supporting resolutions up to 2048 x 2048 with a pixel
depth from 1 to 24 bits per pixel.
A pixel co-processor provides color space conversions for images and video, in addition to a
wide variety of hardware filter support
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC modules
provides on-chip solutions for network-connected devices.
Synchronous Serial Controllers provide easy access to serial communication protocols, audio
standards like AC'97, I2S, I2C and various SPI modes. The modules support frame-based pro-
tocols, like VoIP SIP protocols.
The Java hardware acceleration implementation in AVR32 allows for a very high Java byte-code
execution. AVR32 implements Java instructions in hardware, reusing the existing RISC data
path, which allows for a near-zero hardware overhead and cost with a very high performance.
The Image Sensor Interface supports cameras with up to 12-bit data buses and connects
directly to the LCD interface through a separate bus.
PS2 connectivity is provided for standard input devices like mice and keyboards.
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32003FSAVR3207/06
AT32AP7000
AT32AP7000 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.
The C-compiler is closely linked to the architecture and is able to utilize code optimization fea-
tures, both for size and speed.
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32003FSAVR3207/06
AT32AP7000
2.
Blockdiagram
Figure 2-1.
Blockdiagram
System Manager
INTC
PWM
TC0
TC1
PS2
TWI
AHB Bus
Matrix
DMA Controller
16kB SRAM
16kB SRAM
AHB-APB
Bridge
AHB-APB
Bridge
Configuration
Registers
PHY
MACB0
MACB1
ISI
USB
HMATRIX
SMC
SDRAM
ECC
AVR32 AP CPU
16kB ICACHE
16kB DCACHE
MMU
Nexus Class 3
OCD
Pixel
Coprocessor
SSC0
SSC1
SSC2
PD
C
SPI0
SPI1
PDC
USART0
USART1
USART2
USART3
PDC
LCD Controller
DM
A
Ethernet MAC1
DM
A
Ethernet MAC0
DM
A
Image Sensor
Interface
DM
A
USB HS Device
DM
A
DAC
DM
A
AC97C
DM
A
MCI
DM
A
PIO
PIO
A
PB B
u
s A
AP
B B
u
s B
APB Bus A
Peripheral DMA
Controller
SDRAM
Controller
Static Memory
Controller
ECC
EBI
Input/Outpu
t Pi
ns
Input/Outp
u
t Pi
n
s
5
32003FSAVR3207/06
AT32AP7000
2.1
Processor and architecture
2.1.1
AVR32AP CPU
32-bit load/store AVR32B RISC architecture.
Up to 15 general-purpose 32-bit registers.
32-bit Stack Pointer, Program Counter and Link Register reside in register file.
Fully orthogonal instruction set.
Privileged and unprivileged modes enabling efficient and secure Operating Systems.
Innovative instruction set together with variable instruction length ensuring industry leading
code density.
DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
SIMD extention for media applications.
7 stage pipeline allows one instruction per clock cycle for most instructions.
Java Hardware Acceleration.
Byte, half-word, word and double word memory access.
Unaligned memory access.
Shadowed interrupt context for INT3 and multiple interrupt priority levels.
Dynamic branch prediction and return address stack for fast change-of-flow.
Coprocessor interface.
Full MMU allows for operating systems with memory protection.
16Kbyte Instruction and 16Kbyte data caches.
Virtually indexed, physically tagged.
4-way associative.
Write-through or write-back.
Nexus Class 3 On-Chip Debug system.
Low-cost NanoTrace supported.
2.1.2
Pixel Coprocessor (PiCo)
Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.
Three parallel Vector Multiplication Units (VMU) where each unit can:
Multiply three pixel components with three coefficients.
Add the products from the multiplications together.
Accumulate the result or add an offset to the sum of the products.
Can be used for accelerating:
Image Color Space Conversion.
Configurable Conversion Coefficients.
Supports packed and planar input and output formats.
Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).
Image filtering/scaling.
Configurable Filter Coefficients.
Throughput of one sample per cycle for a 9-tap FIR filter.
Can use the built-in accumulator to extend the FIR filter to more than 9-taps.
Can be used for bilinear/bicubic interpolations.
MPEG-4/H.264 Quarter Pixel Motion Compensation.
Flexible input Pixel Selector.
Can operate on numerous different image storage formats.
Flexible Output Pixel Inserter.
Scales and saturates the results back to 8-bit pixel values.
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