Product Overview

ARM920T

System-on-Chip Open OS Processor

ARM Confidential

Applications

Applications running an
Open OS:
- Symbian OS
- Linux, Palm OS
- WindowsCE

High performance wireless
applications:
- Smart phones
- PDAs

Networking applications

Digital set top boxes

Imaging

Automotive control
solutions

Audio and video encoding
and decoding

Benefits

Designed specifically for
System-on-Chip
integration

Supports the Thumb
instruction set offering the
same excellent code
density as the ARM7TDMI

High performance allows
system designers to
integrate more functionality
into price and
power-sensitive
applications demanding
more performance

Cached processor with an
easy to use lower
frequency on-chip system
bus interface.

The ARM920TTM

The ARM920T is a high-performance 32-bit RISC processor macrocell
combining an ARM9TDMITM processor core with:

16KB instruction and 16KB data caches

instruction and data Memory Management Units (MMUs)

write buffer

an AMBATM (Advanced Microprocessor Bus Architecture) bus interface

an Embedded Trace Macrocell (ETM) interface.

High performance

The ARM920T provides a high-performance processor solution for open
systems requiring full virtual memory management and sophisticated memory

protection. An enhanced ARM

architecture v4 MMU implementation provides

translation and access permission checks for instruction and data addresses.

The ARM920T high-performance processor solution gives considerable
savings in chip complexity and area, chip system design, and power
consumption.

Compatible with ARM7TM and StrongARM

The ARM920T processor is 100% user code binary compatible with

ARM7TDMI, and backwards compatible with the ARM7 Thumb

Family and

the StrongARM processor families, giving designers software-compatible
processors with a range of price/performance points from 60 MIPS to 200+
MIPS. Support for the ARM architecture today includes:

WindowsCE, Symbian OS, Linux, and QNX operating systems

40+ Real Time Operating Systems

co-simulation tools from leading EDA vendors

variety of software development tools.

ARM920T

ARM Confidential

ARM920T Macrocell

The ARM920T macrocell is based on
the ARM9TDMI Harvard architecture
processor core, with an efficient
5-stage pipeline. The architecture of
the processor core or integer unit is
described in more detail page 9.

To reduce the effect of main memory
bandwidth and latency on
performance, the ARM920T includes:

instruction cache

data cache

MMU

TLBs

write buffer

physical address TAG RAM.

Caches

Two 16KB caches are implemented,
one for instructions, the other for
data, both with an 8-word line size. A
32-bit data bus connects each cache
to the ARM9TDMI core allowing a

32-bit instruction to be fetched and
fed into the instruction Decode stage
of the pipeline at the same time as a
32-bit data access for the Memory
stage of the pipeline.

Cache lock-down

Cache lock-down is provided to allow
critical code sequences to be locked
into the cache to ensure predictability
for real-time code. The cache
replacement algorithm can be
selected by the operating system as

ARM920T function block diagram

ARM9TDMI

Processor core

(Integral EmbeddedICE)

Write

buffer

ID[31:0]

IMVA[31:0]

WBPA[31:0]

DPA[31:0]

IPA[31:0]

ASB

Write back

PATAG RAM

CP15

R13

IVA[31:0]

DVA[31:0]

JTAG

External

coprocessor

interface

DD[31:0]

Instruction

cache

Instruction

MMU

Data

MMU

Data

cache

R13

DINDEX[5:0]

Trace

interface

port

AMBA

bus

interface

DMVA[31:0]

ARM920T

DVI 0024B

Page 3

ARM Confidential

either pseudo random or round-robin.
Both caches are 64-way set-
associative. Lock-down operates on
a per-set basis.

Write buffer

The ARM920T also incorporates a
16-entry write buffer, to avoid stalling
the processor when writes to external
memory are performed.

PATAG RAM

The ARM920T implements PATAG
RAM to perform write-backs from the
data cache.

The physical address of all the lines
held in the data cache is stored by
the PATAG memory, removing the
need for address translation when
evicting a line from the cache.

MMUs

The standard ARM920T implements
an enhanced ARMv4 MMU to
provide translation and access
permission checks for the instruction
and data address ports of the
ARM9TDMI.

The MMU features are:

standard ARMv4 MMU mapping
sizes, domains, and access
protection scheme

mapping sizes are 1MB sections,
64KB large pages, 4KB small
pages, and new 1KB tiny pages

access permissions for sections

access permissions for large
pages and small pages can be
specified separately for each
quarter of the page (these
quarters are called subpages)

16 domains implemented in
hardware

64-entry instruction TLB and 64-
entry data TLB

hardware page table walks

round-robin replacement
algorithm (also called cyclic).

System controller

The system controller oversees the
interaction between the instruction
and data caches and the Bus
Interface Unit. It controls internal
arbitration between the blocks and
stalls appropriate blocks when
required.

The system controller arbitrates
between instruction and data access
to schedule single or simultaneous
requests to the MMUs and the Bus
Interface Unit. The system controller
receives acknowledgement from
each resource to allow execution to
continue.

Control coprocessor (CP15)

The CP15 allows configuration of the
caches, the write buffer, and other
ARM920T options.
Several registers within CP15 are
available for program control,
providing access to features such as:

invalidate whole TLB using CP15

invalidate TLB entry, selected by
modified virtual address, using
CP15

independent lock-down of
instruction TLB and data TLB
using CP15 register 10

big or little-endian operation

low power state

memory partitioning and
protection

page table address

cache and TLB maintenance
operations.

The ARMv4T Architecture

ARM Confidential

Registers

The ARM9TDMI processor core
consists of a 32-bit datapath and
associated control logic. This
datapath contains 31 general-
purpose registers, coupled to a full
shifter, Arithmetic Logic Unit, and
multiplier. At any one time 16
registers are visible to the user. The
remainder are synonyms used to
speed up exception processing.
Register 15 is the Program Counter
(PC) and can be used in all
instructions to reference data relative
to the current instruction. R14 holds
the return address after a subroutine
call. R13 is used (by software
convention) as a stack pointer.

Modes and exception
handling

All exceptions have banked registers
for R14 and R13. After an exception,
R14 holds the return address for
exception processing. This address
is used both to return after the
exception is processed and to
address the instruction that caused
the exception.

R13 is banked across exception
modes to provide each exception
handler with a private stack pointer.
The fast interrupt mode also banks
registers 8 to 12 so that interrupt
processing can begin without the
need to save or restore these
registers.

A seventh processing mode, System
mode, does not have any banked
registers. It uses the User mode
registers. System mode runs tasks
that require a privileged processor
mode and allows them to invoke all
classes of exceptions.

Status registers

All other processor states are held in
status registers. The current
operating processor status is in the
Current Program Status Register
(CPSR). The CPSR holds:

four ALU flags (Negative, Zero,
Carry, and Overflow)

two interrupt disable bits (one for
each type of interrupt)

a bit to indicate ARM or Thumb
execution

and five bits to encode the
current processor mode.

All five exception modes also have a
Saved Program Status Register
(SPSR) that holds the CPSR of the
task immediately before the
exception occurred.

Exception types

ARM9TDMI supports five types of
exception, and a privileged
processing mode for each type. The
types of exceptions are:

fast interrupt (FIQ)

normal interrupt (IRQ)

memory aborts (used to
implement memory protection or
virtual memory)

attempted execution of an
undefined instruction

software interrupts (SWIs).

Conditional execution

All ARM instructions are conditionally
executed. Instructions optionally
update the four condition code flags
(Negative, Zero, Carry, and Overflow)
according to their result. Subsequent

instructions are conditionally
executed according to the status of
flags. Fifteen conditions are
implemented.

Four classes of
instructions

The ARM and Thumb instruction sets
can be divided into four broad
classes of instruction:

data processing instructions

load and store instructions

branch instructions

coprocessor instructions.

Data processing

The data processing instructions
operate on data held in general-
purpose registers. Of the two source
operands, one is always a register.
The other has two basic forms:

an immediate value

a register value optionally
shifted.

If the operand is a shifted register the
shift amount might have an
immediate value or the value of
another register. Four types of shift
can be specified. Most data
processing instructions can perform
a shift followed by a logical or
arithmetic operation. Multiply
instructions come in two classes:

normal, 32-bit result

long, 32-bit result variants.

Both types of multiply instruction can
optionally perform an accumulate
operation.

The ARMv4T Architecture

ARM Confidential

Load and store

The second class of instruction is
load and store instructions. These
instructions come in two main types:

load or store the value of a single
register

load and store multiple register
values.

Load and store single register
instructions can transfer a 32-bit
word, a 16-bit halfword and an 8-bit
byte between memory and a register.
Byte and halfword loads might be
automatically zero extended or sign
extended as they are loaded. Swap
instructions perform an atomic load
and store as a synchronization
primitive.

Addressing modes

Load and store instructions have
three primary addressing modes:

offset

pre-indexed

post-indexed.

They are formed by adding or
subtracting an immediate or register-
based offset to or from a base
register. Register-based offsets can
also be scaled with shift operations.
Pre-indexed and post-indexed
addressing modes update the base
register with the base plus offset
calculation. As the PC is a general-
purpose register, a 32-bit value can
be loaded directly into the PC to
perform a jump to any address in the
4GB memory space.

Block transfers

Load and store multiple instructions
perform a block transfer of any
number of the general purpose
registers to or from memory. Four
addressing modes are provided:

pre-increment addressing

post-increment addressing

pre-decrement addressing

post-decrement addressing.

The base address is specified by a
register value (that can be optionally
updated after the transfer). As the
subroutine return address and the
PC values are in general-purpose
registers, very efficient subroutine
calls can be constructed.

Branch

As well as allowing any data
processing or load instruction to
change control flow (by writing the
PC) a standard branch instruction is
provided with 24-bit signed offset,
allowing forward and backward
branches of up to 32MB.

Branch with Link

There is a Branch with Link (BL) that
allows efficient subroutine calls. BL
preserves the address of the
instruction after the branch in R14
(the Link Register or LR). This allows
a move instruction to put the LR in to
the PC and return to the instruction
after the branch.

Coprocessor

There are three types of coprocessor
instructions:

coprocessor data processing
instructions invoke a coprocessor
specific internal operation

coprocessor register transfer
instructions allow a coprocessor
value to be transferred to or from
an ARM register

coprocessor data transfer
instructions transfer coprocessor
data to or from memory, where

the ARM calculates the address
of the transfer.

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