07/2005
ARA2004
Reverse Amplifier with Step Attenuator
Data Sheet - Rev 2.1
FEATURES
Low Cost Integrated Amplifier with Step
Attenuator
Attenuation Range: 0-58 dB, adjustable in 1 dB
increments via a 3 wire serial control
Meets DOCSIS distortion requirements at +60
dBmV output signal level
Low distortion and low noise
Frequency range: 5-100 MHz
5 Volt operation
-40 to +85
o
C temperature range
RoHS Compliant Package Option
APPLICATIONS
MCNS/DOCSIS Compliant Cable Modems
CATV Interactive Set-Top Box
Telephony over Cable Systems
OpenCable Set-Top Box
Residential Gateway
PRODUCT DESCRIPTION
The ARA2004 is designed to provide the reverse path
amplification and output level control functions in a
CATV Set-Top Box or Cable Modem. It incorporates
a digitally controlled precision step attenuator that is
preceded by an ultra low noise amplifier stage, and
followed by an ultra-linear output driver amplifier. This
device uses a balanced circuit design that exceeds
the MCNS/DOCSIS requirement for harmonic
Figure 1: Cable Modem or Set Top Box Application Diagram
S12 Package
28 Pin SSOP
with Heat Slug
Diplexer
ARA2004
SAW
Filter
Double-
Conversion
Tuner
MAC
Upstream
QPSK/16QAM
Modulator
QAM Receiver
with FEC
Balun
Low Pass
Filter
Transmit Enable/Disable
Enable
Data
Clock
Microcontroller
with Ethernet
MAC
RAM
ROM
10Base-T
Transceiver
RJ45
Connector
Clock
Clock
Data
Data
54-860 MHz
44 MHz
5-42 MHz
performance at a +60 dBmV output level while only
requiring a single polarity +5 V supply. Both the input
and output are matched to 75 ohms with an
appropriate transformer. The precision attenuator
provides up to 58 dB of attenuation in 1 dB increments
via a three-wire serial interface. With external passive
components, this device meets IEC 1000-4-12 and
ANSI/IEEE C62.41-1991 100KHz ringwave tests, as
well as IEC1000-4-5 1.2/50
S surge tests. The
ARA2004 is offered in a 28-pin SSOP package
featuring a heat slug on the bottom of the package.
2
Data Sheet - Rev 2.1
07/2005
ARA2004
Figure 2: Functional Block Diagram
32 dB
16 dB
8 dB
4 dB
2 dB
1 dB
EFET
EFET
GaAs IC
ATT
IN
(+)
A1
OUT
(+)
A1
IN
(+)
I
SET1
Vg1
A1
OUT
(-)
A1
IN
(-)
ATT
IN
(-)
ATT
OUT
(-)
A2
IN
(-)
A2
OUT
(-)
Vg2
I
SET2
A2
OUT
(+)
A2
IN
(+)
ATT
OUT
(+)
16 dB
1 dB
2 dB
4 dB
8 dB
32 dB
CMOS IC (Serial to Parallel Interface)
8-Bit Shift
Register/
Address
Buffer
Control Latch
P5
P4
P3
P2
P1
P0
8
Clock
Data
Enable
Figure 3: Pin Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
GND
I
SET1
A1
OUT
(-)
Vg1
ATT
IN
(-)
V
CMOS
A1
IN
(+)
A1
OUT
(+)
CLK
ATT
IN
(+)
DAT
V
ATTN
En
A1
IN
(-)
A2
OUT
(-)
I
SET2
A2
IN
(-)
Vg2
ATT
OUT
(-)
A2
OUT
(+)
GND
CMOS
A2
IN
(+)
N/C
ATT
OUT
(+)
N/C
N/C
N/C
Data Sheet - Rev 2.1
07/2005
3
ARA2004
Table 1: Pin Description
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
1
D
N
G
d
n
u
o
r
G
5
1
C
/
N
n
o
it
c
e
n
n
o
C
o
N
)
1
(
2
V
N
T
T
A
r
o
t
a
u
n
e
tt
A
r
o
f
y
l
p
p
u
S
6
1
C
/
N
n
o
it
c
e
n
n
o
C
o
N
)
1
(
3
T
T
A
N
I
)
+
(
t
u
p
n
I
)
+
(
r
o
t
a
u
n
e
tt
A
)
2
(
7
1
C
/
N
n
o
it
c
e
n
n
o
c
o
N
)
1
(
4
1
A
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
1
A
r
e
if
il
p
m
A
8
1
D
N
G
S
O
M
C
l
a
ti
g
i
D
r
o
f
d
n
u
o
r
G
ti
u
c
r
i
C
S
O
M
C
5
1
A
N
I
)
+
(
t
u
p
n
I
)
+
(
1
A
r
e
if
il
p
m
A
)
2
(
9
1
T
T
A
T
U
O
)
-
(
t
u
p
t
u
O
)
-
(
r
o
t
a
u
n
e
tt
A
)
2
(
6
1
g
V
l
o
r
t
n
o
C
)
-
/
+
(
1
A
r
e
if
il
p
m
A
0
2
2
A
N
I
)
-
(
t
u
p
n
I
)
-
(
2
A
r
e
if
il
p
m
A
)
2
(
7
I
1
T
E
S
t
n
e
r
r
u
C
)
-
/
+
(
1
A
r
e
if
il
p
m
A
t
s
u
j
d
A
1
2
2
A
T
U
O
)
-
(
t
u
p
t
u
O
)
-
(
2
A
r
e
if
il
p
m
A
8
1
A
N
I
)
-
(
t
u
p
n
I
)
-
(
1
A
r
e
if
il
p
m
A
)
2
(
2
2
I
2
T
E
S
)
-
/
+
(
2
A
r
e
if
il
p
m
A
t
s
u
j
d
A
t
n
e
r
r
u
C
9
1
A
T
U
O
)
-
(
t
u
p
t
u
O
)
-
(
1
A
r
e
if
il
p
m
A
3
2
2
g
V
l
o
r
t
n
o
C
)
-
/
+
(
2
A
r
e
if
il
p
m
A
0
1
T
T
A
N
I
)
-
(
t
u
p
n
I
)
-
(
r
o
t
a
u
n
e
tt
A
)
2
(
4
2
2
A
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
2
A
r
e
if
il
p
m
A
1
1
V
S
O
M
C
l
a
ti
g
i
D
r
o
F
y
l
p
p
u
S
ti
u
c
r
i
C
S
O
M
C
5
2
2
A
N
I
)
+
(
t
u
p
n
I
)
+
(
2
A
r
e
if
il
p
m
A
)
2
(
2
1
K
L
C
k
c
o
l
C
6
2
T
T
A
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
r
o
t
a
u
n
e
tt
A
)
2
(
3
1
T
A
D
a
t
a
D
7
2
C
/
N
n
o
it
c
e
n
n
o
C
o
N
)
1
(
4
1
n
E
e
l
b
a
n
E
8
2
D
N
G
d
n
u
o
r
G
Notes:
(1) All N/C pins should be grounded.
(2) Pins should be AC-coupled. No external DC bias should be applied.
4
Data Sheet - Rev 2.1
07/2005
ARA2004
ELECTRICAL CHARACTERISTICS
R
E
T
E
M
A
R
A
P
N
I
M
X
A
M
T
I
N
U
)
4
2
,
1
2
,
9
,
4
,
2
s
n
i
p
(
y
l
p
p
u
S
g
o
l
a
n
A
0
9
C
D
V
V
:
y
l
p
p
u
S
l
a
ti
g
i
D
CMOS
)
1
1
n
i
p
(
0
6
C
D
V
)
3
2
,
6
s
n
i
p
(
2
g
V
,
1
g
V
s
l
o
r
t
n
o
C
r
e
if
il
p
m
A
5
-
2
V
F
R
s
t
u
p
n
I
t
a
r
e
w
o
P
s
n
i
p
(
8
,
5
)
-
0
6
+
V
m
B
d
)
4
1
,
3
1
,
2
1
s
n
i
p
(
e
c
a
f
r
e
t
n
I
l
a
ti
g
i
D
5
.
0
-
V
CMOS
5
.
0
+
V
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
5
5
-
0
0
2
+
0
C
e
r
u
t
a
r
e
p
m
e
T
g
n
ir
e
d
l
o
S
-
0
6
2
0
C
e
m
i
T
g
n
ir
e
d
l
o
S
-
5
c
e
S
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
V
:
y
l
p
p
u
S
r
e
if
il
p
m
A
DD
)
4
2
,
1
2
,
9
,
4
s
n
i
p
(
5
.
4
5
7
C
D
V
V
:
y
l
p
p
u
S
r
o
t
a
u
n
e
tt
A
ATTN
)
2
n
i
p
(
V
DD
5
.
0
-
5
7
C
D
V
V
:
y
l
p
p
u
S
l
a
ti
g
i
D
CMOS
)
1
1
n
i
p
(
0
.
3
-
5
.
5
C
D
V
e
c
a
f
r
e
t
n
I
l
a
ti
g
i
D
0
-
V
CMOS
V
)
3
2
,
6
s
n
i
p
(
2
g
V
,
1
g
V
s
l
o
r
t
n
o
C
r
e
if
il
p
m
A
5
-
1
2
V
e
r
u
t
a
r
e
p
m
e
T
e
s
a
C
0
4
-
5
2
5
8
0
C
Stresses in excess of the absolute ratings may cause permanent damage. Functional
operation is not implied under these conditions. Exposure to absolute ratings for
extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical specifications.
Notes:
1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be
applied.
2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC
bias should be applied.
Data Sheet - Rev 2.1
07/2005
5
ARA2004
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
)
9
,
4
s
n
i
p
(
t
n
e
r
r
u
C
1
A
r
e
if
il
p
m
A
-
-
8
4
4
.
2
0
8
6
A
m
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
)
4
2
,
1
2
s
n
i
p
(
t
n
e
r
r
u
C
2
A
r
e
if
il
p
m
A
-
-
7
7
7
.
3
0
2
1
9
A
m
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
)
2
n
i
p
(
t
n
e
r
r
u
C
r
o
t
a
u
n
e
tt
A
-
9
5
1
A
m
n
o
it
p
m
u
s
n
o
C
r
e
w
o
P
l
a
t
o
T
-
-
7
6
.
0
5
7
8
0
.
1
0
5
1
W
W
m
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
Note: As measured in ANADIGICS test fixture
Table 4: DC Electrical Specifications
T
A
=25
C; V
DD
, V
ATTN
, V
CMOS
= +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
)
z
H
M
0
1
(
n
i
a
G
5
.
7
2
3
.
9
2
5
.
0
3
B
d
g
n
it
t
e
s
n
o
it
a
u
n
e
tt
a
B
d
0
s
s
e
n
t
a
l
F
n
i
a
G
-
-
5
7
.
0
5
.
1
-
-
B
d
z
H
M
2
4
o
t
5
z
H
M
5
6
o
t
5
e
r
u
t
a
r
e
p
m
e
T
r
e
v
o
n
o
it
a
ir
a
V
n
i
a
G
-
6
0
0
.
0
-
-
C
/
B
d
B
d
1
s
p
e
t
S
n
o
it
a
u
n
e
tt
A
B
d
2
B
d
4
B
d
8
B
d
6
1
B
d
2
3
5
6
.
0
6
.
1
6
.
3
5
.
7
0
.
5
1
2
.
0
3
3
8
.
0
0
7
.
1
5
7
.
3
5
7
.
7
0
4
.
5
1
5
7
.
0
3
0
0
.
1
5
0
.
2
0
.
4
0
.
8
8
.
5
1
3
.
1
3
B
d
c
i
n
o
t
o
n
o
M
n
o
it
a
u
n
e
tt
A
m
u
m
i
x
a
M
6
.
8
5
3
.
0
6
-
B
d
2
d
n
l
e
v
e
L
n
o
it
r
o
t
s
i
D
c
i
n
o
m
r
a
H
)
z
H
M
0
1
(
-
5
7
-
3
5
-
c
B
d
s
m
h
O
5
7
o
t
n
i
V
m
B
d
0
6
+
3
d
r
l
e
v
e
L
n
o
it
r
o
t
s
i
D
c
i
n
o
m
r
a
H
)
z
H
M
0
1
(
-
0
6
-
3
5
-
c
B
d
s
m
h
O
5
7
o
t
n
i
V
m
B
d
0
6
+
3
d
r
t
p
e
c
r
e
t
n
I
t
u
p
t
u
O
r
e
d
r
O
8
7
-
-
V
m
B
d
t
n
i
o
P
n
o
i
s
s
e
r
p
m
o
C
n
i
a
G
B
d
1
-
5
.
8
6
-
V
m
B
d
e
r
u
g
i
F
e
s
i
o
N
-
0
.
3
0
.
4
B
d
s
s
o
l
n
u
l
a
b
t
u
p
n
i
s
e
d
u
l
c
n
I
Table 5: AC Electrical Specifications
T
A
=25
C; V
DD
, V
ATTN
, V
CMOS
= +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
6
Data Sheet - Rev 2.1
07/2005
ARA2004
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
r
e
w
o
P
e
s
i
o
N
t
u
p
t
u
O
.t
e
S
.
n
e
tt
A
.
n
i
M
/
l
a
n
g
i
S
o
N
/
e
v
it
c
A
.t
e
S
.
n
e
tt
A
.
x
a
M
/
l
a
n
g
i
S
o
N
/
e
v
it
c
A
-
-
-
-
5
.
8
3
-
8
.
3
5
-
V
m
B
d
h
t
d
i
w
d
n
a
b
z
H
k
0
6
1
y
n
A
z
H
M
2
4
o
t
5
m
o
r
f
e
d
o
m
e
l
b
a
s
i
d
x
T
n
i
)
z
H
M
5
4
(
n
o
it
a
l
o
s
I
-
5
6
-
B
d
t
u
p
t
u
o
n
i
e
c
n
e
r
e
ff
i
D
x
T
n
e
e
w
t
e
b
l
a
n
g
i
s
e
l
b
a
s
i
d
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3
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h
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8
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n
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w
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t
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e
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r
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m
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5
7
(
-
-
0
2
-
5
-
2
1
-
-
B
d
d
e
l
b
a
n
e
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T
d
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b
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3
-
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2
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n
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p
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t
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5
7
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s
m
h
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r
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r
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a
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ti
w
s
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n
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t
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p
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e
c
n
a
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p
m
i
c
it
s
ir
e
t
c
a
r
a
h
c
m
h
O
5
7
(
-
-
7
1
-
5
1
-
2
1
-
0
1
-
B
d
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
t
n
e
i
s
n
a
r
T
e
g
a
tl
o
V
t
u
p
t
u
O
e
l
b
a
s
i
d
x
T
/
e
l
b
a
n
e
x
T
-
-
-
4
0
0
1
7
p
-
p
V
m
g
n
it
t
e
s
r
o
t
a
u
n
e
tt
a
B
d
0
g
n
it
t
e
s
r
o
t
a
u
n
e
tt
a
B
d
4
2
Note: As measured in ANADIGICS test fixture
continued: AC Electrical Specifications
T
A
=25
C; V
DD
, V
ATTN
, V
CMOS
= +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
Data Sheet - Rev 2.1
07/2005
7
ARA2004
Figure 4: Test Circuit
22
7
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
GN
D
I
SE
T
1
Vg1
A1
IN
(+
)
A1
OU
T
(+
)
AT
T
IN
(+
)
V
AT
T
N
V
CM
O
S
CL
K
DA
T
En
N
/
C
A2
OU
T
(-
)
I
SE
T
2
A2
IN
(-
)
Vg
2
AT
T
OU
T
(-
)
GN
D
CM
O
S
A2
IN
(+
)
A2
OU
T
(+
)
N/
C
N/
C
N/
C
GN
D
A1
IN
(-)
A1
OU
T
(-)
AT
T
IN
(-)
AT
T
OU
T
(+
)
(
75 O
h
m
s
)
470
pF
470
pF
1K O
h
m
s
470p
F
2K O
h
ms
Tu
rn
s
Ra
ti
o
2:1
1
500pF
R
F
O
u
tput
(
75 O
h
m
s
)
0 / +
3
V
Co
ntr
o
l
A
2
+5
V
1u
F
0
.
1uF
3.9 O
h
m
s
Cloc
k
Enable
Data
+5
V
1000
pF
10
00pF
1.2
K
O
h
m
s
RF
Input
0 / +
3
V
Co
ntr
o
l
A
1
+5
V
1.2K O
h
m
s
1000pF
1000p
F
1u
F
0.1
u
F
1K O
h
m
s
470p
F
2K
O
h
m
s
AR
A2
004
1
0uH
10uH
1u
F
0.1uF
+5
V
1uF
0.1u
F
No
t
e
:
Tx
En
ab
l
e
:
C
o
nt
r
o
l
A
1
an
d C
o
nt
r
o
l
A
2
=
+
3
V
Tx
D
i
s
a
b
l
e:
C
o
n
t
r
o
l
A1
an
d
C
o
nt
r
o
l
A
2
=
0
V
To
ko
B
a
l
u
n
6
16PT
-
1030
2K O
h
ms
2K
O
h
m
s
Tu
rn
s
Rat
i
o
1:2
8
Data Sheet - Rev 2.1
07/2005
ARA2004
PERFORMANCE DATA
Figure 5: Attenuation Level vs Control Word
Figure 6: Gain & Noise Figure vs Frequency
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
Control Word
A
tte
n
u
a
tio
n
(d
B
)
Figure 7: Gain & Noise Figure vs V
DD
5
10
15
20
25
30
35
10
30
50
70
90
Frequency (MHz)
Ga
i
n
(
d
B)
2
3
4
5
6
7
8
NF
(
d
B)
Gain
Noise Figure
20
23
26
29
32
35
3
4
5
6
7
V
DD
( Volts )
GA
IN
(
d
B
)
1
2
3
4
5
6
NF (
d
B)
Gain
Noise Figure
Measured @ 30 MHz
Data Sheet - Rev 2.1
07/2005
9
ARA2004
Figure 8: Gain & Noise Figure vs Temperature
Figure 9: Harmonic Distortion vs V
DD
P
OUT
= 58dBmV
Figure 10: Harmonic Distortion vs V
DD
P
OUT
= 58dBmV
-80
-70
-60
-50
-40
-30
-20
3
4
5
6
7
V
DD
( Volts )
H
a
rm
onic Level (dB
c
)
2nd Harmonic
3rd Harmonic
Measured @ 5 MHz
-80
-70
-60
-50
-40
-30
-20
3
4
5
6
7
V
DD
( Volts )
H
a
rm
oni
c Level
(
d
B
c
)
2nd Harmonic
3rd Harmonic
Measured @ 12 MHz
20
23
26
29
32
35
-40
-25
-10
5
20
35
50
65
80
Temperature (C
o
)
GA
IN
(d
B
)
1
2
3
4
5
6
NF (
d
B)
Gain
Noise Figure
Measured @ 30 MHz
10
Data Sheet - Rev 2.1
07/2005
ARA2004
Figure 11: Harmonic Distortion vs Temperature
P
OUT
= 58dBmV
Figure 12: Harmonic Distortion vs Power Out
-80
-75
-70
-65
-60
-55
-50
-45
-40
-40
-25
-10
5
20
35
50
65
80
Temperature (C
o
)
H
a
rm
o
n
i
c level (d
B
c
)
2nd Harmonic
3rd Harmonic
Measured @ 5 MHz
Figure 13: Transients vs Attenuation
P
OUT
= 55dBmV at 0dB attenuation
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
49
51
53
55
57
59
61
63
65
67
Pout (dBmV)
Ha
r
m
o
n
i
c
s
(
d
Bc
)
2nd
3rd
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
Power Attenuation (dB)
T
r
an
sien
t (m
V
)
DOCSIS 1.1 Spec.
ARA2001
ARA2004
Data Sheet - Rev 2.1
07/2005
11
ARA2004
Figure 14: Harmonic Performance over
Frequency
P
OUT
= +62dBmV
Figure 15: IIP
2
& IIP
3
vs Frequency
Figure 16: IIP
2
& IIP
3
vs V
DD
20
24
28
32
36
40
5
15
25
35
45
55
65
75
85
95
Frequency (MHz)
IIP
2
(d
B
m
)
4
6
8
10
12
14
IIP
3
(d
B
m
)
IIP2
IIP3
Measured @ V
DD
= 5 Volts
Pin = -20 dBm per tone
20
24
28
32
36
40
3
4
5
6
7
V
DD
(Volts)
IIP
2
(d
B
m
)
-5
-1
3
7
11
15
IIP
3
(d
B
m
)
IIP2
IIP3
Measured @ 65 MHz
Two tones @ 29.5 MHz
-72
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50
0
5
10
15
20
25
30
35
40
Frequency (MHz)
H
a
rm
oni
c Level
(
d
B
c
)
2nd Harmonic
3rd Harmonic
12
Data Sheet - Rev 2.1
07/2005
ARA2004
DATA
CLOCK
ENABLE
ENABLE
OR
D
7
: MSB
D
6
D
4
D
3
D
1
D
0
: LSB
Table 6: Programming Word
T
I
B
A
T
A
D
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
e
u
l
a
V
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
LOGIC PROGRAMMING
Table 7: Data Description
Figure 17: Serial Data Input Timing
E
U
L
A
V
N
O
I
T
C
N
U
F
)
s
s
a
p
y
b
=
0
,
n
o
=
1
(
7
P
A
/
N
6
P
A
/
N
5
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
2
3
4
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
6
1
3
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
8
2
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
4
1
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
2
0
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
1
Programming Instructions
The programming word is set through an 8 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
Data Sheet - Rev 2.1
07/2005
13
ARA2004
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2004 includes two amplification stages that
each can be shut down through external control pins
Vg1 and Vg2 (pins 6 and 23, respectively.) By
applying a slightly positive bias of typically +1.0 Volts,
the amplifier is enabled. In order to disable the
amplifier, the control pin needs to be pulled to
ground.
A practical way to implement the necessary control
is to use bias resistor networks similar to those
shown in the test circuit schematic (Figure 4.) Each
network includes a resistor shunted to ground that
serves as a pull-down to disable the amplifier when
no control voltage is applied. When a positive voltage
is applied, the network acts as a voltage divider that
presents the required +1.0 Volts to enable the
amplifier. By selecting different resistor values for
the voltage divider, the network can accommodate
different control voltage inputs.
The Vg1 and Vg2 pins may be connected together
directly, and controlled through a single resistor
network from a common control voltage.
Amplifier Bias Current
The I
SET
pins (7 and 22) set the bias current for the
amplification stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use
the configuration shown in the test circuit schematic
in Figure 4.
Thermal Layout Considerations
The device package for the ARA2004 features a heat
slug on the bottom of the package body. Use of the
heat slug is an integral part of the device design.
Soldering this slug to the ground plane of the PC
board will ensure the lowest possible thermal
resistance for the device, and will result in the longest
MTF (mean time to failure.)
A PC board layout that optimizes the benefits of the
heat slug is shown in Figure 18. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide a
sufficient heat sink. The recommended solder mask
outline is shown in Figure 19.
Figure 18: PC Board Layout
14
Data Sheet - Rev 2.1
07/2005
ARA2004
Figure 19: Solder Mask Outline
Output Transformer
Matching the output of the ARA2004 to a 75 Ohm
load is accomplished using a 2:1 turns ratio
transformer. In addition to providing an impedance
transformation, this transformer provides the bias to
the output amplifier stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the amplifiers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF
and DC power requirements without saturating the
core, and it must have adequate isolation and good
phase and amplitude balance. It also must operate
over the desired frequency and temperature range
for the intended application.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to this device. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Although the
ARA2004 has some built-in ESD protection, proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
Data Sheet - Rev 2.1
07/2005
15
ARA2004
Figure 20: S12 Package Outline - 28 Pin SSOP with Heat Slug
PACKAGE OUTLINE
16
Data Sheet - Rev 2.1
07/2005
ARA2004
COMPONENT PACKAGING
Figure 22: Tape Dimensions
Volume quantities of the ARA2004 are supplied on
tape and reel. Each reel holds 3,500 pieces.
Figure 21: Reel Dimensions
DIRECTION OF FEED
Data Sheet - Rev 2.1
07/2005
17
ARA2004
NOTES
18
Data Sheet - Rev 2.1
07/2005
ARA2004
NOTES
Data Sheet - Rev 2.1
07/2005
19
ARA2004
NOTES
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
Data Sheet - Rev 2.1
07/2005
20
ARA2004
ORDERING INFORMATION
R
E
B
M
U
N
R
E
D
R
O
E
R
U
T
A
R
E
P
M
E
T
E
G
N
A
R
E
G
A
K
C
A
P
N
O
I
T
P
I
R
C
S
E
D
G
N
I
G
A
K
C
A
P
T
N
E
N
O
P
M
O
C
1
P
2
1
S
4
0
0
2
A
R
A
5
8
o
t
0
4
-
0
C
h
ti
w
P
O
S
S
n
i
P
8
2
g
u
l
S
t
a
e
H
l
e
e
r
d
n
a
e
p
a
t
e
c
e
i
p
0
0
5
,
3
1
P
2
1
S
R
4
0
0
2
A
R
A
5
8
o
t
0
4
-
0
C
t
n
a
il
p
m
o
C
S
H
o
R
h
ti
w
P
O
S
S
n
i
P
8
2
g
u
l
S
t
a
e
H
l
e
e
r
d
n
a
e
p
a
t
e
c
e
i
p
0
0
5
,
3
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