LP62S16128C-I Series

Preliminary

128K X 16 BIT LOW VOLTAGE CMOS SRAM

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Features

General Description

Operating voltage: 2.7V to 3.6V

Access times: 55/70 ns (max.)

Current:

Very low power version: Operating:

55ns 40mA (max.)

70ns 35mA (max.)

Standby: 10

A (max.)

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Data retention voltage: 2V (min.)

Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)

packages

The LP62S16128C-I is a low operating current
2,097,152-bit static random access memory organized as
131,072 words by 16 bits and operates on low power
voltage from 2.7V to 3.6V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

CCDR

, Typ.)

Standby

SB1

, Typ.)

Operating

CC2

, Typ.)

Package

Type

LP62S16128C

-40

C ~ +85

C 2.7V~3.6V

55ns / 70ns

0.2

0.5

5mA

44L TSOP

48B MBGA

1. Typical values are measured at VCC = 3.0V, T

= 25

C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configurations

TSOP

CSP (Chip Size Package)

48-pin Top View

I/O

GND

VCC

I/O

A12

A10

A11

A13

A14

A15

I/O

GND

VCC

I/O

A16

I/O

VCC

GND

I/O

A16

A15

A14

A13

A11

A10

I/O

VCC

GND

I/O

LP62S16128CV-I

A12

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Block Diagram

DECODER

512 X 4096

MEMORY ARRAY

COLUMN I/O

INPUT

DATA

CIRCUIT

CONTROL

CIRCUIT

VCC

GND

I/O

A16

A15

INPUT

DATA

CIRCUIT

I/O

Pin Descriptions -- TSOP

Pin No.

Symbol

Description

1 - 5, 18 22,

24 27, 42 - 44

A0 - A16

Address Inputs

Chip Enable Input

7 - 10, 13 - 16,

29 - 32, 35 - 38

I/O

- I/O

Data Inputs/Outputs

Write Enable Input

Lower Byte Enable Input (I/O

to I/O

)

Higher Byte Enable Input (I/O

to I/O

)

Output Enable Input

11, 33

VCC

Power

12, 34

GND

Ground

23, 28

No Connection

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Pin Description - CSP

Symbol

Description

Symbol

Description

A0 - A16

Address Inputs

Higher Byte Enable Input
(I/O

- I/O

)

Chip Enable

Output Enable

I/O

- I/O

Data Input/Output

VCC

Power Supply

Write Enable Input

GND

Ground

Byte Enable Input
(I/O

- I/O

)

No Connection

Recommended DC Operating Conditions

= -40

C to + 85

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCC

Supply Voltage

2.7

3.6

GND

Ground

Input High Voltage

2.2

VCC + 0.3

Input Low Voltage

-0.3

+0.6

Output Load

TTL

Output Load

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Absolute Maximum Ratings*

VCC to GND ...............................................-0.5V to +4.6V
IN, IN/OUT Volt to GND .................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ....................-40

C to +85

Storage Temperature, Tstg......................-55

C to +125

Power Dissipation, P

............................................... 0.7W

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics

= -40

C to + 85

C, VCC = 2.7V to 3.6V, GND = 0V)

Symbol

Parameter

LP62S16128C-55LLI

LP62S16128C-70LLI Unit

Conditions

Min.

Max.

Min.

Max.

Input Leakage Current

= GND to VCC

Output Leakage
Current

CE = V

LB = HB = V

I/O

= GND to VCC

Active Power Supply
Current

CE = V

LB = V

or HB = V

IL ,

I/O

= 0 mA

CC1

Dynamic Operating

Min. Cycle, Duty = 100%

CE = V

LB = V

or HB = V

IL ,

I/O

= 0 mA

CC2

Current

0.2V ,

0.2V or HB

0.2V,

f = 1MHz , I

I/O

= 0 mA

0.5

CE = V

or LB = HB = V

SB1

Standby Power
Supply Current

VCC 0.2V or

LB = HB

VCC 0.2V,

VCC 0.2V or V

0.2V

Output Low Voltage

0.4

= 2.1 mA

Output High Voltage

2.2

= -1.0 mA

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Truth Table

I/O

to I/O

Mode

I/O

to I/O

Mode

VCC Current

Not selected

SB1

, I

High-Z

SB1

, I

Read

CC1

, I

CC2

, I

Read

High - Z

CC1

, I

CC2

, I

High - Z

Read

CC1

, I

CC2

, I

Write

CC1

, I

CC2

, I

Write

High - Z

CC1

, I

CC2

, I

High - Z

Write

CC1

, I

CC2

, I

High - Z

CC1

, I

CC2

, I

High - Z

CC1

, I

CC2

, I

Note: X = H or L

Capacitance

= 25

C, f = 1.0MHz)

Symbol

Parameter

Min.

Max.

Unit

Conditions

Input Capacitance

= 0V

I/O

Input/Output Capacitance

I/O

= 0V

* These parameters are sampled and not 100% tested.

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

AC Characteristics

= -40

C to +85

C, VCC = 2.7V to 3.6V)

Symbol

Parameter

LP62S16128C-55LLI

LP62S16128C-70LLI

Unit

Min.

Max.

Min.

Max.

Read Cycle

Read Cycle Time

Address Access Time

ACE

Chip Enable Access Time

Byte Enable Access Time

Output Enable to Output Valid

CLZ

Chip Enable to Output in Low Z

BLZ

Byte Enable to Output in Low Z

OLZ

Output Enable to Output in Low Z

CHZ

Chip Disable to Output in High Z

BHZ

Byte Disable to Output in High Z

OHZ

Output Disable to Output in High Z

Output Hold from Address Change

Write Cycle

Write Cycle Time

Chip Enable to End of Write

Byte Enable to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

WHZ

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

Note: t

BLZ

, t

OLZ,

CHZ

, t

BHZ

and t

OHZ

and t

WHZ

are defined as the time at which the outputs achieve the open circuit condition

and are not referred to output voltage levels.

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Timing Waveforms

Read Cycle 1

(1, 2, 4)

Address

OUT

Read Cycle 2

(1, 2, 3)

Address

ACE

CHZ5

HB, LB

BHZ5

CLZ5

BLZ5

OLZ5

OHZ5

OUT

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE = V

, HB = V

and, or LB = V

3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.

4. OE = V

5. Transition is measured

500mV from steady state. This parameter is sampled and not 100% tested.

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 3
(Byte Enable Controlled)

Address

DATA IN

DATA OUT

HB, LB

WR3

BW2

AS1

WHZ4

Notes: 1. t

is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (t

, t

) of a low CE , WE and ( HB and , or LB ).

3. t

is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle.

4. OE level is high or low.

5. Transition is measured

500mV from steady state. This parameter is sampled and not 100% tested.

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels

0.4V to 2.4V

Input Rise And Fall Time

5 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

30pF

* Including scope and jig.

TTL

5pF

TTL

Figure 1. Output Load

Figure 2. Output Load for t

CLZ

OLZ

BHZ

BLZ

CHZ

OHZ

WHZ

and t

Data Retention Characteristics

= -40

C to 85

Symbol

Parameter

Min.

Max.

Unit

Conditions

VCC for Data Retention

2.0

3.6

VCC - 0.2V or

LB = HB

VCC-0.2V

CCDR

Data Retention Current

VCC = 2V,

VCC - 0.2V or

LB = HB

VCC-0.2V

VCC - 0.2V or V

0.2V

CDR

Chip Disable to Data Retention Time

Operation Recovery Time

See Retention Waveform

VCC Rising Time from Data Retention
Voltage to Operating Voltage

* LP62S16128C-55 / 70LLI

CCDR

: max. 1

A at T

= 0

C to + 40

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Low VCC Data Retention Waveform

VCC

CDR

2.7V

DATA RETENTION MODE

- 0.2V

Ordering Information

Part No.

Access Time (ns)

Operating Current

Max. (mA)

Standby Current

Max. (

µ
µ

Package

LP62S16128CV-55LLI

44L TSOP

LP62S16128CU-55LLI

48L CSP

LP62S16128CV-70LLI

44L TSOP

LP62S16128CU-70LLI

48L CSP

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Package Information

TSOP 44L TYPE II Outline Dimensions

unit: inches/mm

0.254

D y

Symbol

Dimension in inch

Dimension in mm

Min. Nom. Max. Min. Nom. Max.

0.047

1.20

0.002

0.05

0.037 0.039 0.041 0.95

1.00

1.05

0.010 0.014 0.018 0.25

0.35

0.45

0.006

0.15

0.721 0.725 0.729 18.31 18.41 18.51

0.396 0.400 0.404 10.06 10.16 10.26

0.031

0.80

0.455 0.463 0.471 11.56 11.76 11.96

0.016 0.020 0.024 0.40

0.50

0.60

0.031

0.80

0.036

0.93

0.004

0.10

Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.

LP62S16128C-I Series

PRELIMINARY (April, 2002, Version 0.0)

AMIC Technology, Inc.

Package Information

48LD CSP (6 x 8 mm) Outline Dimensions

unit: mm

(48TFBGA)

A
B

C
D

E
F

G
H

TOP VIEW

Ball#A1 CORNER

SIDE VIEW

SEATING PLANE

A
B
C
D
E
F

G
H

1 2 3 4 5 6

0.10

0.25

A B

b (48X)

BOTTOM VIEW

Ball*A1 CORNER

0.20(4X)

0.10

Dimensions in mm

Symbol

MIN.

NOM. MAX.

---

1.20

0.20

0.25

0.30

5.90

6.00

6.10

7.90

8.00

8.10

---

3.75

---

5.25

---

0.75

---

0.30

0.35

0.40

Note:

1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS

ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL

CROWNS OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.

THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.

4. BALL PAD OPENING OF SUBSTRATE IS

0.3mm (SMD)

SUGGEST TO DESIGN THE PCB LAND SIZE AS

0.3mm (NSMD)

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