Publication# 16491

Rev. D

Amendment /0

Issue Date: February 1996

2-155

Advanced

Micro

Devices

PALCE20V8 Family

EE CMOS 24-Pin Universal Programmable Array Logic

FINAL

COM'L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all GAL

20V8/As

Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability

High-speed CMOS technology
-- 5-ns propagation delay for "-5" version
-- 7.5-ns propagation delay for "-7" version

Direct plug-in replacement for a wide range of
24-pin PAL devices

Programmable enable/disable control

Outputs individually programmable as
registered or combinatorial

Peripheral Component Interconnect (PCI)
compliant

Preloadable output registers for testability

Automatic register reset on power-up

Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages

Extensive third-party software and programmer
support through FusionPLD partners

Fully tested for 100% programming and func-
tional yields and high reliability

Programmable output polarity

5-ns version utilizes a split leadframe for
improved performance

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.

Device logic is automatically configured according to the
user's design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.

The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.

The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.

16491D-1

MACRO

CLK/I

I/O

Input
Mux.

BLOCK DIAGRAM

Programmable AND Array

40 x 64

AMD

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PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com'l)

PALCE20V8H-15/25, Q-20/25 (Ind)

ORDERING INFORMATION
Commercial and Industrial Products

PALCE20V8Q-15

PALCE20V8H-15

PALCE20V8Q-10

Blank, /4

NUMBER OF FLIP-FLOPS

OUTPUT TYPE
V = Versatile

TECHNOLOGY
CE = CMOS Electrically Erasable

PC, JC

Valid Combinations

AMD programmable logic products for commercial and industrial applications are available with several ordering options. The
order number (Valid Combination) is formed by a combination of:

PAL

20 V 8 H -5

P C

PALCE20V8Q-20

PACKAGE TYPE
P = 24-Pin 300 mil Plastic

SKINNYDIP (PD3024)

J = 28-Pin Plastic Leaded Chip

Carrier (PL 028)

OPERATING CONDITIONS
C = Commercial (0

C to +75

= Industrial (40

C to +85

SPEED
-5

= 5 ns t

-7

= 7.5 ns t

-10 = 10 ns t

-15 = 15 ns t

-20 = 20 ns t

-25 = 25 ns t

FAMILY TYPE
PAL = Programmable Array Logic

POWER
H = Half Power (90-125 mA I

)

Q = Quarter Power (55 mA I

)

PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4

= First Revision

Second Revision
(Same algorithm as /4)

PALCE20V8H-10

NUMBER OF ARRAY INPUTS

PALCE20V8H-7

PALCE20V8H-25

PALCE20V8H-5

Blank,

Valid Combinations

Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of spe-
cific valid combinations and to check on newly re-
leased combinations.

PC, JC, PI, JI

PC, JC

PALCE20V8Q-25

PI, JI

PC, JC, PI, JI

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PALCE20V8 Family

FUNCTIONAL DESCRIPTION

The PALCE20V8 is a universal PAL device. It has eight
independently configurable macrocells (MC

..MC

Each macrocell can be configured as a registered out-
put, combinatorial output, combinatorial I/O, or dedi-
cated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complemen-
tary outputs to provide user-programmable input signal
polarity. Pins 1 and 13 serve either as array inputs or as
clock (CLK) and output enable (

) for all flip-flops.

Unused input pins should be tied directly to V

or GND.

Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.

The programmable functions on the PALCE20V8 are
automatically configured from the user's design specifi-
cation, which can be in a number of formats. The design

specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user's desired function.

The user is given two design options with the
PALCE20V8. First, it can be programmed as an emu-
lated PAL device. This includes the PAL20R8 series
and most 24-pin combinatorial PAL devices. The PAL
device programmer manufacturer will supply device
codes for the standard PAL architectures to be used
with the PALCE20V8. The programmer will program the
PALCE20V8 to the corresponding PAL device architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed
directly as a PALCE20V8. Here the user must use the
PALCE20V8 device code. This option provides full utili-
zation of the macrocells, allowing non-standard archi-
tectures to be built.

16491D-4

* In Macrocells MC

and MC

SG1 is replaced by

SG0

on the feedback multiplexer.

1 1

0 X
1 0

1 1
1 0
0 0
0 1

1 1

1 0

0 X

1 0

0 X

1 1

SG1

SL1

CLK

Adjacent

Macrocell

From
Adjacent
Pin

SL0

*SG1

I/O

SL0

Figure 1. PALCE20V8 Macrocell

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PALCE20V8 Family

Configuration Options

Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O or dedicated input. In the registered output
configuration, the output buffer is enabled by the

pin.

In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, the buffer is always dis-
abled. A macrocell configured as a dedicated input de-
rives the input signal from an adjacent I/O.

The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL0

through SL0

and SL1

through SL1

). SG0 determines whether registers will

be allowed. SG1 determines whether the PALCE20V8
will emulate a PAL20R8 family or a combinatorial de-
vice. Within each macrocell, SL0

, in conjunction with

SG1, selects the configuration of the macrocell and
SL1

sets the output as either active low or active high.

The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0

are the control signals for all four multiplexers. In

and MC

SG0

replaces SG1 on the feedback

multiplexer.

These configurations are summarized in table 1 and il-
lustrated in figure 2.

If the PALCE20V8 is configured as a combinatorial de-
vice, the CLK and

pins may be available as inputs to

the array. If the device is configured with registers, the
CLK and

pins cannot be used as data inputs.

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1

. SL1

is an input to

the exclusive-OR gate which is the D input to the flip-
flop. SL1

is programmed as 1 for inverted output or 0

for non-inverted output. The flip-flop is loaded on the
LOW-to-HIGH transition of CLK. The feedback path is
from

on the register. The output buffer is enabled by

Combinatorial Configurations

The PALCE20V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.

Dedicated Output in a Non-Registered
Device

The control settings are SG0 = 1, SG1 = 0, and SL0

= 0.

All eight product terms are available to the OR gate. Al-
though the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 18(21) and
19(23). Pins 18(21) and 19(23) do not use feedback in
this mode.

Dedicated Input in a Non-Registered
Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0

1. The output buffer is disabled. The feedback signal is
an adjacent I/O pin.

Combinatorial I/O in a Non-Registered
Device

The control settings are SG0 = 1, SG1 = 1, and SL0

= 1.

Only seven product terms are available to the OR gate.
The eighth product term is used to enable the output
buffer. The signal at the I/O pin is fed back to the AND
array via the feedback multiplexer. This allows the pin to
be used as an input.

Combinatorial I/O in a Registered Device

The control bit settings are SG0=0,SG1=1 and SL0

=1.

Only seven product terms are available to the OR gate.
The eighth product term is used as the output enable.
The feedback signal is the corresponding I/O signal.

Table 1. Macrocell Configurations

SG0 SG1 SL0

Cell Configuration Devices Emulated

Device has registers

Registered

PAL20R8, 20R6,

Output

20R4

Combinatorial I/O

PAL20R6, 20R4

Device has no registers

Combinatorial

PAL20L2,

Output

18L4,16L6,14L8

Dedicated Input

PAL20L2,18L4,
16L6

Combinatorial I/O

PAL20L8

Programmable Output Polarity

The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save "DeMorganizing"
efforts.

Selection is made through a programmable bit SL1

which controls an exclusive-OR gate at the output of the
AND/OR logic. The output is active high if SL1

is a 0

and active low if SL1

is a 1.

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PALCE20V8 Family

Power-Up Reset

All flip-flops power up to a logic LOW for predictable sys-
tem initialization. Outputs of the PALCE20V8 depend on
whether they are selected as registered or combinato-
rial. If registered is selected, the output will be HIGH. If
combinatorial is selected, the output will be a function of
the logic.

Register Preload

The register on the PALCE20V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load-
ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.

Security Bit

A security bit is provided on the PALCE20V8 as a deter-
rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from com-
petitors. The bit can only be erased in conjunction with
the array during an erase cycle.

Electronic Signature Word

An electronic signature word is provided in the
PALCE20V8. It consists of 64 bits of programmable
memory that can contain any user-defined data. The
signature data is always available to the user independ-
ent of the security bit.

Programming and Erasing

The PALCE20V8 can be programmed on standard logic
programmers. It also may be erased to reset a previ-
ously configured device back to its virgin state. Erasure
is automatically performed by the programming hard-
ware. No special erase operation is required.

Quality and Testability

The PALCE20V8 offers a very high level of built-in qual-
ity. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming and post-programming functional yields in
the industry.

Technology

The high-speed PALCE20V8H is fabricated with AMD's
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.

PCI Compliance

The PALCE20V8H-7/10 is fully compliant with the

PCI

Local Bus Specification published by the PCI Special In-
terest Group. The PALCE20V8H-7/10's predictable tim-
ing ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD
and FPGA architectures without predictable timing, PCI
compliance is dependent upon routing and product term
distribution.

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PALCE20V8H-15/25 Q-15/25 (Com'l)

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

C to +150

. . . . . . . . . . .

Ambient Temperature
with Power Applied

C to +125

. . . . . . . . . . . . .

Supply Voltage with
Respect to Ground

0.5 V to +7.0 V

. . . . . . . . . . . . .

DC Input Voltage

0.5 V to V

+ 0.5 V

. . . . . . . . . . .

DC Output or
I/O Pin Voltage

0.5 V to V

+ 0.5 V

. . . . . . . . . . . . .

Static Discharge Voltage

2001 V

. . . . . . . . . . . . . . . . .

Latchup Current
(T

= 0

C to +75

100 mA

. . . . . . . . . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.

OPERATING RANGES

Commercial (C) Devices
Temperature (T

) Operating

in Free Air

C to +75

. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

)

with Respect to Ground

+4.75 V to +5.25 V

. . . . . . . .

Operating ranges define those limits between which the func-
tionality of the device is guaranteed.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Output HIGH Voltage

= 3.2 mA V

= V

or V

2.4

= Min

Output LOW Voltage

= 24 mA V

= V

or V

0.5

= Min

Input HIGH Voltage

Guaranteed Input Logical HIGH

2.0

Voltage for all Inputs (Note 1)

Input LOW Voltage

Guaranteed Input Logical LOW

0.8

Voltage for all Inputs (Note 1)

Input HIGH Leakage Current

= 5.25 V, V

= Max (Note 2)

Input LOW Leakage Current

= 0 V, V

= Max (Note 2)

100

OZH

Off-State Output Leakage

OUT

= 5.25 V, V

= Max

Current HIGH

= V

or V

(Note 2)

OZL

Off-State Output Leakage

OUT

= 0 V, V

= Max

100

Current LOW

= V

or V

(Note 2)

Output Short-Circuit Current

OUT

= 0.5 V, V

= Max (Note 3)

150

Supply Current

Outputs Open (I

OUT

= 0 mA)

= Max, f = 15 MHz

Notes:

1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

OZL

(or I

and I

OZH

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

OUT

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

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PALCE20V8H-15/25 Q-15/25 (Com'l)

CAPACITANCE (Note 1)

Parameter

Symbol

Parameter Description

Test Conditions

Typ

Unit

Input Capacitance

= 2.0 V

= 5.0 V, T

= 25

OUT

Output Capacitance

OUT

= 2.0 V

f = 1 MHz

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

Symbol

Parameter Description

Min

Max

Min

Max

Unit

Input or Feedback to Combinatorial Output

Setup Time from Input or Feedback to Clock

Hold Time

Clock to Output

LOW

HIGH

External Feedback

1/(t

+ t

)

45.5

MHz

MAX

Internal Feedback (f

CNT

)

1/(t

+ t

) (Note 4)

MHz

No Feedback

1/(t

+ t

)

62.5

41.6

MHz

PZX

to Output Enable

PXZ

to Output Disable

Input to Output Enable Using Product Term Control

Input to Output Disable Using Product Term Control

-15

-25

Clock Width

Maximum
Frequency
(Note 3)

Notes:

2. See Switching Test Circuit for test conditions.

3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified

where frequency may be affected.

4. t

is a calculated value and is not guaranteed. t

can be found using the following equation:

= 1/f

MAX

(internal feedback) t

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PALCE20V8 Family

POWER-UP RESET

The PALCE20V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature pro-
vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.

Due to the synchronous operation of the power-up reset
and the wide range of ways V

can rise to its steady

state, two conditions are required to insure a valid
power-up reset. These conditions are:

The V

rise must be monotonic.

Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.

Parameter

Symbol

Parameter Description

Min

Max

Unit

Power-Up Reset Time

1000

Input or Feedback Setup Time

Clock Width LOW

See Switching

Characteristics

16491D-16

4 V

Power

Registered

Output

Clock

Power-Up Reset Waveforms

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