FINAL

Publication# 18723

Rev: C Amendment/+1

Issue Date: May 1998

AmC0XXCFLKA

1, 2, 4, or 10 Megabyte 5.0 V-only Flash Memory PC Card

DISTINCTIVE CHARACTERISTICS

High performance
-- 150 ns maximum access time

Single supply operation
-- Write and erase voltage, 5.0 V

-- Read voltage, 5.0 V

CMOS low power consumption
-- 45 mA maximum active read current (x8 mode)
-- 65 mA maximum active erase/write current

(x8 mode)

High write endurance
-- Minimum 100,000 erase/write cycles

PCMCIA/JEIDA 68-pin standard
-- Selectable byte- or word-wide configuration

Write protect switch
-- Prevents accidental data loss

Zero data retention power
-- Batteries not required for data storage

Separate attribute memory
-- 512 byte EEPROM

Automated write and erase operations increase
system write performance
-- 64K byte memory sectors for faster automated

erase speed

-- Typically 1.5 seconds per single memory sector

erase

-- Random address writes to previously erased

bytes (16 µs typical per byte)

Total system integration solution
-- Support from independent software and

hardware vendors

Low insertion and removal force
-- State-of-the-art connector allows for minimum

card insertion and removal effort

Sector erase suspend/resume
-- Suspend the erase operation to allow a read

operation in another sector within the same
device

GENERAL DESCRIPTION

AMD's 5.0 V-only Flash Memory PC Card provides the
highest system level performance for data and file stor-
age solutions to the portable PC market segment. Man-
ufactured with AMD's Negative Gate Erase, 5.0 V-only
technology, the AMD 5.0 V-only Flash Memory Cards
are the most cost-effective and reliable approach to
single-supply Flash memory cards. Data files and ap-
plication programs can be stored on the "C" series
cards. This allows OEM manufacturers of portable sys-
tems to eliminate the weight, high power consumption
and reliability issues associated with electromechanical
disk-based systems. The "C" series cards also allow to-
day's bulky and heavy battery packs to be reduced in
weight and size. Typically only two "AA" alkaline batter-
ies are required for total system operation. AMD's
Flash Memory PC Cards provide the most efficient
method to transfer useful work between different hard-
ware platforms. The enabling technology of the "C" se-
ries cards enhances the productivity of mobile workers.

Widespread acceptance of the "C" series cards is as-
sured due to their compatibility with the 68-pin PCM-

CIA/JEIDA international standard. AMD's Flash
Memory Cards can be read in either a byte-wide or
word-wide mode which allows for flexible integration
into various system platforms. Compatibility is assured
at the hardware interface and software interchange
specification. The Card Information Structure (CIS) or
Metaformat, can be written by the OEM at the memory
card's attribute memory address space beginning at
address 00000H by using a format utility. The CIS ap-
pears at the beginning of the Card's attribute memory
space and defines the low-level organization of data on
the PC Card. The "C" series cards contains a separate
512 byte EEPROM memory for the cards' attribute
memory space. This allows all of the Flash memory to
be used for the common memory space.

Third party software solutions such as Microsoft's
Flash File System (FFS), M-System's True FFS, and
SCM's SCM-FFS, enable AMD's Flash Memory PC
Card to replicate the function of traditional disk-based
memory systems.

AmC0XXCFLKA

5/4/98

BLOCK DIAGRAM

Notes:
R = 20 K(min)/140 K

(max)

*1 Mbyte card = S0 + S1, *2 Mbyte card = S0...S3, *4 Mbyte card = S0...S7, *10 Mbyte card = S0...S19

Address

Buffers

and

Decoders

I/O

Transceivers

and

Buffers WP

(Note 1)

A0A8

D0D7

Attribute Memory

Write Protect
Switch

A0A18

CEH0
CEH9

CEL0
CEL9

D0D15

D8D15

D0D7

A1A23*

CE2

CE1

A1A9

CE2

CE1

REG

CD1

CD2

Card Detect

BVD1

BVD2

Battery Voltage

Detect

GND

10K

Am29F040

A0A18 D0D7
CE
WE
OE

S0*

Am29F040

A0A18 D8D15
CE
WE
OE

S1*

A0A18 D0D7
CE
WE
OE

S2*

A0A18 D8D15
CE
WE
OE

S3*

A0A18 D0D7
CE
WE
OE

S18*

A0A18 D8D15
CE
WE
OE

S19*

18723C-1

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AmC0XXCFLKA

PC CARD PIN ASSIGNMENTS

Notes:
I = Input to card, O = Output from card

I/O = Bidirectional

NC = No connect

In systems which switch V

individually to cards, no signal should be directly connected between cards other than ground.

1. V

not required for Programming or Reading operations.

2. BVD = Internally pulled-up.

3. Signal must not be connected between cards.

4. Highest address bit for 1 Mbyte card.

5. Highest address bit for 2 Mbyte card.

6. Highest address bit for 4 Mbyte card.

7. Highest address bit for 10 Mbyte card.

Pin#

Function

Pin#

Signal

I/O

Function

GND

Ground

GND

Ground

I/O

Data Bit 3

CD1

Card Detect 1 (Note 3)

I/O

Data Bit 4

D11

I/O

Data Bit 11

I/O

Data Bit 5

D12

I/O

Data Bit 12

I/O

Data Bit 6

D13

I/O

Data Bit 13

I/O

Data Bit 7

D14

I/O

Data Bit 14

CE1

Card Enable 1 (Note 3)

D15

I/O

Data Bit 15

A10

Address Bit 10

CE2

Card Enable 2 (Note 3)

Output Enable

No Connect

A11

Address Bit 11

No Connect

Address Bit 9

No Connect

Address Bit 8

A17

Address Bit 17

A13

Address Bit 13

A18

Address Bit 18

A14

Address Bit 14

A19

Address Bit 19 (Note 4)

Write Enable

A20

Address Bit 20 (Note 5)

No Connect

A21

Address Bit 21 (Note 6)

CC1

Power Supply

CC2

Power Supply

No Connect (Note 1)

A16

Address Bit 16

A22

Address Bit 22

A15

Address Bit 15

A23

Address Bit 23 (Note 7)

A12

Address Bit 12

No Connect

Address Bit 7

No Connect

Address Bit 6

No Connect

Address Bit 5

No Connect

Address Bit 4

No Connect

Address Bit 3

No Connect

Address Bit 2

REG

Address Bit 1

BVD2

Battery Voltage Detect 2 (Note 2)

Address Bit 0

BVD1

Battery Voltage Detect 1 (Note 2)

I/O

Data Bit 0

I/O

Data Bit 8

I/O

Data Bit 1

I/O

Data Bit 9

I/O

Data Bit 2

D10

I/O

Data Bit 10

Write Protect (Note 3)

CD2

Card Detect 2 (Note 3)

GND

Ground

GND

Ground

5/4/98

AmC0XXCFLKA

PIN DESCRIPTION

A0A23

Address Inputs

These inputs are internally latched during write cycles.

BVD1, BVD2

Battery Voltage Detect

Internally pulled-up.

CD1, CD2

Card Detect

When card detect 1 and 2 = ground the system detects
the card.

CE1, CE2

Card Enable

This input is active low. The memory card is deselected
and power consumption is reduced to standby levels
when CE is high. CE activates the internal memory
card circuitry that controls the high and low byte control
logic of the card, input buffers segment decoders, and
associated memory devices.

D0D15

Data Input/Output

Data inputs are internally latched on write cycles. Data
outputs during read cycles. Data pins are active high.
When the memory card is deselected or the outputs
are disabled the outputs float to tristate.

GND

Ground

No Connect

Corresponding pin is not connected internally to the die.

Output Enable

This input is active low and enables the data buffers
through the card outputs during read cycles.

REG

Attribute Memory Select

This input is active low and enables reading the CIS
from the EEPROM.

PC Card Power Supply

For device operation (5.0 V

5%).

Write Enable

This input is active low and controls the write function
of the command register to the memory array. The

target address is latched on the falling edge of the WE
pulse and the appropriate data is latched on the rising
edge of the pulse.

Write Protect

This output is active high and disables all card write
operations.

MEMORY CARD OPERATIONS

The "C" series Flash Memory Card is organized as an
array of individual devices. Each device is 512K bytes
in size with eight 64K byte sectors. Although the ad-
dress space is continuous each physical device defines
a logical address segment size.

Byte-wide erase operations could be performed in
four ways:

In increments of the segment size

In increments of the sectors in individual segments

All eight sectors in parallel within individual
segments

Selected sectors of the eight sectors in parallel
within individual segments

Multiple segments may be erased concurrently when
additional I

current is supplied to the device. Once a

memory sector or memory segment is erased any ad-
dress location may be programmed. Flash technology
allows any logical "1" data bit to be programmed to a
logical "0". The only way to reset bits to a logical "1" is
to erase the entire memory sector of 64K bytes or
memory segment of 512K bytes.

Erase operations are the only operations that work on
entire memory sectors or memory segments. All other
operations such as word-wide programming are not af-
fected by the physical memory segments.

The common memory space data contents are altered
in a similar manner as writing to individual Flash mem-
ory devices. On-card address and data buffers activate
the appropriate Flash device in the memory array. Each
device internally latches address and data during write
cycles. Refer to Table 1.

Attribute memory is a separately accessed card mem-
ory space. The register memory space is active when
the REG pin is driven low. The Card Information Struc-
ture (CIS) describes the capabilities and specification
of a card. The CIS is stored in the attribute memory
space beginning at address 00000H. The "C" series
cards contain a separate 512 byte EEPROM memory
for the Card Information Structure. D0D7 are active
during attribute memory accesses. D8D15 should be
ignored. Odd order bytes present invalid data. Refer to
Table 2.

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