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PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Publication# 22929

Rev: C Amendment/0

Issue Date: August 2000

Refer to AMD's Website (www.amd.com) for the latest information.

Am79C976

PCnet-PROTM
10/100 Mbps PCI Ethernet Controller

DISTINCTIVE CHARACTERISTICS

Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus

-- 32-bit glueless PCI host interface

-- Supports PCI clock frequency from DC to

33 MHz independent of network clock

-- Supports network operation with PCI clock

from 15 MHz to 33 MHz

-- High performance bus mastering

architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization

-- PCI specification revision 2.2 compliant

-- Supports PCI Subsystem/Subvendor

ID/Vendor ID programming through the
EEPROM interface

-- Supports both PCI 3.3-V and 5.0-V signaling

environments

-- Plug and Play compatible

-- Uses advanced PCI commands (MWI, MRL,

MRM)

-- Optionally supports PCI bursts aligned to

cache line boundaries

-- Supports big endian and little endian byte

alignments

-- Implements optional PCI power management

event (PME) pin

-- Supports 40-bit addressing (using PCI Dual

Address Cycles)

Media Independent Interface (MII) for
connecting external 10/100 megabit per second
(Mbps) transceivers

-- IEEE 802.3-compliant MII

-- Intelligent Auto-PollTM external PHY status

monitor and interrupt

-- Supports both auto-negotiable and non auto-

negotiable external PHYs

-- Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex

Full-duplex operation supported with
independent Transmit (TX) and Receive (RX)
channels

Includes support for IEEE 802.1Q VLANs

-- Automatically inserts, deletes, or modifies

VLAN tag

-- Optionally filters untagged frames

Provides optional flow control features

-- Recognizes and transmits IEEE 802.3x MAC

flow control frames

-- Asserts collision-based back pressure in

half-duplex mode

Provides internal Management Information
Base (MIB) counters for network statistics

Supports PC97, PC98, PC99, and Net PC
requirements

-- Implements full OnNow features including

pattern matching and link status wake-up

-- Implements Magic PacketTM mode

-- Magic Packet mode and the physical address

loaded from EEPROM at power up without
requiring PCI clock

-- Supports PCI Bus Power Management

Interface Specification Version 1.1

-- Supports Advanced Configuration and

Power Interface (ACPI) Specification Version
1.0

-- Supports Network Device Class Power

Management Specification Version 1.0

Large independent external TX and RX FIFOs

-- Supports up to 4 megabytes (Mbytes)

external SSRAM for RX and TX frame storage

-- Programmable FIFO watermarks for both

transmit and receive operations

-- Receive frame queuing for high latency PCI

bus host operation

-- Programmable allocation of buffer space

between transmit and receive queues

Am79C976

8/01/00

P R E L I M I N A R Y

Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards

Programmable internal/external loopback
capabilities

Supports patented External Address Detection
Interface (EADI) with receive frame tagging
support for internetworking applications

EEPROM interface supports jumperless design
and provides through-chip programming

-- Supports full programmability of all internal

registers through EEPROM mapping

Programmable PHY reset output pin capable of
resetting external PHY without needing
buffering

Integrated oscillator circuit is controlled by
external crystal

Extensive programmable LED status support

Supports up to 16 Mbyte optional Boot PROM or
Flash for diskless node application

Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame

Optional delayed interrupt feature reduces CPU
overhead

Programmable Inter Packet Gap (IPG) to
address less aggressive network MAC
controllers

Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect

Optionally sends and receives non-standard
frames of up to 64K octets in length

IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface for board-level
production connectivity test

Provides built-in self test (MBIST) for the
external SSRAM

Software compatible with AMD PCnet Family
and LANCE/C-LANCE register and descriptor
architecture

Compatible with the existing PCnet Family
driver and diagnostic software (except for
statistics)

Available in 208-pin PQFP package

+3.3-V power supply with 5-V tolerant I/Os
enables broad system compatibility

Support for operation in Industrial temperature
range (-40° C to +85

C) available.

8/01/00

Am79C976

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am79C976 controller is a highly-integrated 32-bit
full-duplex, 10/100-Megabit per second (Mbps) Ether-
net controller solution, designed to address high-
performance system application requirements. It is a
flexible bus mastering device that can be used in any
application, including network-ready PCs and bridge/
router designs. The bus master architecture provides
high data throughput and low CPU and system bus uti-
lization. The Am79C976 controller is fabricated with
advanced low-power 3.3-V CMOS process to provide
low operating current for power sensitive applications.

The Am79C976 controller also has several enhance-
m e n t s o ve r i t s p r e d e c e s s o r, t h e A m 7 9 C 9 7 1
PCnet-FAST device. In addition to providing access to
a larger SSRAM, it further reduces system implemen-
tation cost by the addition of a new EEPROM program-
mable pin (PHY_RST) and the integration of the PAL
function needed for Magic Packet application. The
PHY_RST pin is implemented to reset the external
PHY without increasing the load to the PCI bus and to
block RST to the PHY when PG input is LOW.

The 32-bit multiplexed bus interface unit provides a di-
rect interface to the PCI local bus, simplifying the de-
sign of an Ether net node in a PC system. The
Am79C976 controller provides the complete interface
to an Expansion ROM or Flash device allowing add-on
card designs with only a single load per PCI bus inter-
face pin. With its built-in support for both little and big
endian byte alignment, this controller also addresses
non-PC applications. The Am79C976 controller's
advanced CMOS design allows the bus interface to be
connected to either a +5-V or a +3.3-V signaling envi-
ronment. An IEEE 1149.1-compliant JTAG test inter-
face for board-level testing is also provided.

The Am79C976 controller is also compliant with the
PC97, PC98, PC99, and Network PC (Net PC) specifi-
cations. It includes the full implementation of the Mi-
crosoft OnNow and ACPI specifications, which are
backward compatible with the Magic Packet technol-
ogy, and it is compliant with the PCI Bus Power Man-
agement Interface Specification by supporting the four
power management states (D0, D1, D2, and D3), the
optional PME pin, and the necessary configuration and
data registers.

The Am79C976 controller is ideally suited for Net PC,
motherboard, network interface card (NIC), and em-
bedded designs. It is available in a 208-pin Plastic
Quad Flat Pack (PQFP) package.

The Am79C976 controller contains a bus interface unit,
a DMA Buffer Management Unit, an ISO/IEC 8802-3
(IEEE 802.3)-compliant Media Access Controller
(MAC), and an IEEE 802.3-compliant MII. An interface
to an external RAM of up to 4 Mbytes is provided for
frame storage. The MII supports IEEE 802.3-compliant
full-duplex and half-duplex operations at 10 Mbps or
100 Mbps. The MII TX and RX clock signals can be
stopped independently for home networking applica-
tions.

The Am79C976 controller is register compatible with
the LANCETM (Am7990) and C-LANCETM (Am79C90)
Ethernet controllers, and all Ethernet controllers in the
PCnet Family except ILACCTM (Am79C900), including
t h e P C n e t TM - I S A c o n t r o l l e r ( A m 7 9 C 9 6 0 ) ,
P C n e t TM - I S A + ( A m 7 9 C 9 6 1 ) , P C n e t TM - I S A I I
(Am79C961A), PCnetTM-32 (Am79C965), PCnetTM-
PCI (Am79C970), PCnetTM-PCI II (Am79C970A), and
the PCnetTM-FAST (Am79C971).

The Buffer Management Unit supports the LANCE and
PCnet descriptor software models.

The Am79C976 controller supports auto-configuration
in the PCI configuration space. Additional Am79C976
controller configuration parameters, including the
unique IEEE physical address, can be read from an ex-
ternal nonvolatile memory (EEPROM) immediately fol-
lowing system reset.

In addition, the device provides programmable on-chip
LED drivers for transmit, receive, collision, link integrity,
Magic Packet status, activity, address match, full-
duplex, or 100 Mbps status. The Am79C976 controller
also provides an EADI to allow external hardware ad-
dress filtering in internetworking applications and a
receive frame tagging feature.

With the rise of embedded networking applications op-
erating in harsh environments where temperatures
may exceed the normal commercial temperature (0

to +70

C) window, an industrial temperature (-40

C to

+85

C) version is available. This industrial temperature

version of the PCnet-PRO Ethernet controller is char-
acterized across the industrial temperature range (-40

C to +85

C) within the published power supply specifi-

cation (4.75V to 5.25V;

5% Vcc). Thus, conformance

of the PCnet-PRO performance over this temperature
range is guaranteed by a design and characterization
monitor.

8/01/00

Am79C976

P R E L I M I N A R Y

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LIST OF FIGURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CONNECTION DIAGRAM (PQR208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PIN DESIGNATIONS (PQR208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Disconnect When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Disconnect Of Burst Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Basic Non-Burst Read Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Basic Non-Burst Write Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DMA Burst Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Disconnect Without Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Master Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Preemption During Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Descriptor Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

TABLE OF CONTENTS

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