Data Sheet
29319.37C
3959
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
Always order by complete part number:
Part Number
Package
R
JA
*
R
JT
A3959SB
24-pin batwing DIP
38
C/W
6
C/W
A3959SLB
24-lead batwing SOIC
50
C/W
6
C/W
A3959SLP
28-lead thin shrink SOIC
40
C/W
--
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3959SB, A3959SLB, and A3959SLP are capable of
output currents to
3 A and operating voltages to 50 V. Internal fixed
off-time PWM current-control timing circuitry can be adjusted via
control inputs to operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.
The A3959SB/SLB/SLP is a choice of three power packages, a
24-pin plastic DIP with a copper batwing tab (package suffix `B'), a
24-lead plastic SOIC with a copper batwing tab (package suffix `LB'),
and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal
pad (suffix `LP'). In all cases, the power tab is at ground potential and
needs no electrical isolation.
FEATURES
s
3 A, 50 V Output Rating
s Low
r
DS(on)
Outputs (270 m
, Typical)
s Mixed, Fast, and Slow Current-Decay Modes
s Synchronous Rectification for Low Power Dissipation
s Internal UVLO and Thermal-Shutdown Circuitry
s Crossover-Current Protection
s Internal Oscillator for Digital PWM Timing
A3959SLB
(SOIC)
PWM TIMER
V
BB
24
23
22
21
20
19
18
17
16
15
14
13
GROUND
GROUND
SLEEP
NO
CONNECTION
OUT
B
LOAD SUPPLY
SENSE
OUT
A
NO
CONNECTION
EXT MODE
REF
V
REG
Dwg. PP-069-4
1
2
3
4
5
6
7
8
9
12
11
10
9
GROUND
GROUND
CP
CP
2
CP
1
PHASE
V
DD
ENABLE
PFD
2
BLANK
PFD
1
LOGIC SUPPLY
ROSC
LOGIC
NC
NC
CHARGE PUMP
10
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, V
BB
......................... 50 V
Output Current, I
OUT
(Repetitive) ...........
3.0 A
(Peak, <3
s) ...................................
6.0 A
Logic Supply Voltage, V
DD
....................... 7.0 V
Logic Input Voltage Range, V
IN
(Continuous) ............ -0.3 V to V
DD
+ 0.3 V
(t
w
<30 ns) ............... -1.0 V to V
DD
+ 1.0 V
Sense Voltage, V
S
(Continuous) .............. 0.5 V
(t
w
<3
s) ........................................... 2.5 V
Reference Voltage, V
REF
............................ V
DD
Package Power Dissipation (T
A
= 25
C), P
D
A3959SB ........................................ 3.3 W*
A3959SLB ...................................... 2.5 W*
A3959SLP ...................................... 3.1 W*
Operating Temp. Range, T
A
.... -20
C to +85
C
Junction Temperature, T
J
..................... +150
C
Storage Temp. Range, T
S
..... -55
C to +150
C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150
C.
Note that the A3959SLB(SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
* Double-sided board, one square inch copper each side. See also, Layout, page 7.
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Copyright 2001, 2003 Allegro MicroSystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
A3959SB
(DIP)
Note that the A3959SLB (SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
BANDGAP
REGULATOR
V
DD
V
BB
+
LOGIC
SUPPLY
V
REG
CP1
CP
CP2
LOAD
SUPPLY
GATE DRIVE
Dwg. FP-048-2A
CONTROL LOGIC
SENSE
R
S
SLEEP
EXT MODE
PHASE
ENABLE
BLANK
PFD1
PFD2
REFERENCE
BUFFER &
10
CURRENT
SENSE
ZERO
CURRENT
DETECT
OUT
A
OUT
B
REF
PWM
TIMER
V
REF
C
S
OSC
ROSC
TO V
DD
PWM TIMER
10
V
BB
24
23
22
21
20
19
18
17
16
15
14
13
GROUND
GROUND
SLEEP
V
REG
OUT
B
LOAD
SUPPLY
SENSE
OUT
A
EXT MODE
REF
Dwg. PP-069-5A
1
2
3
4
5
6
7
8
9
12
11
10
9
GROUND
GROUND
CP
CP
2
CP
1
PHASE
V
DD
LOGIC
SUPPLY
ENABLE
PFD
2
BLANK
PFD
1
ROSC
LOGIC
CHARGE PUMP
GROUND
GROUND
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
www.allegromicro.com
3
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Limits
Characteristics
Symbol Test Conditions
Min.
Typ. Max.
Units
Output Drivers
Load Supply Voltage Range
V
BB
Operating
9.5
50
V
During sleep mode
0
50
V
Output Leakage Current
I
DSS
V
OUT
= V
BB
<1.0
20
A
V
OUT
= 0 V
<-1.0
-20
A
Output On Resistance
r
DS(on)
Source driver, I
OUT
= -3 A
270
300
m
Sink driver, I
OUT
= 3 A
270
300
m
Crossover Delay
300
600
1000
ns
Body Diode Forward Voltage
V
F
Source diode, I
F
= -3 A
1.6
V
Sink diode, I
F
= 3 A
1.6
V
Load Supply Current
I
BB
f
PWM
< 50 kHz
4.0
7.0
mA
Charge pump on, outputs disabled
2.0
5.0
mA
Sleep Mode
20
A
Control Logic
Logic Supply Voltage Range
V
DD
Operating
4.5
5.0
5.5
V
Logic Input Voltage
V
IN(1)
2.0
V
V
IN(0)
0.8
V
Logic Input Current
I
IN(1)
V
IN
= 2.0 V
<1.0
20
A
(all inputs except ENABLE)
I
IN(0)
V
IN
= 0.8 V
<-2.0
-20
A
ENABLE Input Current
I
IN(1)
V
IN
= 2.0 V
40
100
A
I
IN(0)
V
IN
= 0.8 V
16
40
A
Internal OSC frequency
f
OSC
R
OSC
shorted to GROUND
3.25
4.25
5.25
MHz
R
OSC
= 51 k
3.65
4.25
4.85
MHz
Reference Input Volt. Range
V
REF
Operating
0.0
V
DD
V
Reference Input Current
I
REF
V
REF
= V
DD
1.0
A
Comparator Input Offset Volt.
V
IO
V
REF
= 0 V
5.0
mV
Continued next page ...
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise), continued.
Limits
Characteristics
Symbol Test Conditions
Min.
Typ. Max.
Units
Control Logic
Reference Divider Ratio
10
G
m
Error
E
Gm
V
REF
= V
DD
4.0
%
(Note 3)
V
REF
= 0.5 V
14
%
Propagation Delay Times
t
pd
0.5 E
in
to 0.9 E
out
:
PWM change to source on
600
750
1200
ns
PWM change to source off
50
150
350
ns
PWM change to sink on
600
750
1200
ns
PWM change to sink off
50
100
150
ns
Thermal Shutdown Temp.
T
J
165
C
Thermal Shutdown Hysteresis
T
J
15
C
UVLO Enable ThresholdUVLO
Increasing V
DD
3.90
4.2
4.45
V
UVLO Hysteresis
UVLO
0.05
0.10
V
Logic Supply Current
I
DD
f
PWM
< 50 kHz
6.0
10
mA
Sleep Mode
2.0
mA
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. G
m
error = ([V
REF
/10] V
SENSE
)/(V
REF
/10) where
V
SENSE
= I
TRIP
R
S
.
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
www.allegromicro.com
5
FUNCTIONAL DESCRIPTION
V
REG
. This internally generated voltage is used to operate
the sink-side DMOS outputs. The V
REG
terminal should
be decoupled with a 0.22
F capacitor to ground. V
REG
is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than V
BB
to drive the source-
side DMOS gates. A 0.22
F ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22
F ceramic capacitor should be connected between
CP and V
BB
to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
PHASE Logic. The PHASE input terminal determines if
the device is operating in the "forward" or "reverse" state.
PHASE
OUT
A
OUT
B
0
Low
High
1
High
Low
ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
ENABLE
Outputs
0
Chopped
1
On
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high,
slow decay mode, both sink drivers are on with ENABLE
low.
EXT MODE
Decay
0
Fast
1
Slow
Current Regulation. Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (R
S
) and the
applied analog reference voltage (V
REF
):
I
TRIP
= V
REF
/10R
S
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fixed off-time period. The current path during
recirculation is determined by the configuration of slow/
mixed/fast current-decay mode via PFD1 and PFD2.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the R
OSC
terminal to V
DD
. Typical value of 4 MHz is set with a
51 k
resistor. The allowable range of the resistor is from
20 k
to 100 k
.
f
OSC
= 204 x 10
9
/R
OSC
.
If R
OSC
is not pulled up to V
DD
, it must be shorted to
ground.
Fixed Off Time. The A3959 is set for a fixed off time of
96 cycles of the internal oscillator, typically 24
s with a
4 MHz oscillator.
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