BiMOS II 12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Designed primarily for use with vacuum-fluorescent displays, the
UCN5811A smart power BiMOS II driver features low-output saturation
voltages and high output switching speed. These devices contain CMOS shift
registers, data latches, and control circuitry, and bipolar high-speed sourcing
outputs with DMOS active pull-down circuitry. The high-speed shift register
and data latches allow direct interface with microprocessor-based systems. A
CMOS serial data output enables cascade connections in applications requir-
ing additional drive lines.
The UCN5811A features 60 V and -40 mA output ratings, allowing it to
be used in many other peripheral power driver applications. It can be used as
an improved replacement tor the SN75512B. The Allegro devices do not
require special power-up sequencing.
The UCN5811A has been designed with BiMOS II logic for improved
data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At
12 V, higher speeds are possible. Use of this device with TTL may require
the use of appropriate pull-up resistors to ensure a proper input logic high.
This device is supplied in a 20-pin plastic dual in-line package. It can be
operated over the ambient temperature range of -20
C to +85C. Copper lead
frames and low output saturation voltages allow all outputs to be operated at
25 mA continuously at ambient temperatures of up to 76
C.
FEATURES
I To 3.3 MHz Data Input Rate
I Low-Power CMOS Logic and Latches
I High-Speed Source Drivers
I Active Pull-Downs
I Low-Output Saturation Voltages
I Improved Replacement for SN75512B
Always order by complete part number:
UCN5811A .
Data Sheet
26182.20B
ABSOLUTE MAXIMUM RATINGS
at
T
A
= 25
C
Logic Supply Voltage,V
DD
..................... 15 V
Driver Supply Voltage, V
BB
................... 60 V
Continuous Output Current,
I
OUT
......................... -40 mA to +25 mA
Input Voltage Range,
V
IN
....................... -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation,
P
D
........................................ See Graph
Operating Temperature Range,
T
A
................................. -20
C to +85
C
Storage Temperature Range,
T
S
............................... -55
C to +150
C
13
14
15
16
17
19
12
18
20
11
1
2
3
8
9
4
5
6
7
10
SERIAL
DATA OUT
SERIAL
DATA IN
BLANKING
LOGIC
SUPPLY
STROBE
CLOCK
OUT
1
OUT
2
OUT
11
OUT
12
LOAD
SUPPLY
BB
V
V
DD
ST
GROUND
CLK
BLNK
OUT
9
OUT
10
OUT
3
Dwg. PP-029-5
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
REGISTER
LATCHES
5811
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TYPICAL OUTPUT DRIVER
FUNCTIONAL BLOCK DIAGRAM
Dwg. W-182
TIMING WAVESHAPES
Dwg. W-184
TYPICAL INPUT CIRCUIT
Dwg. EP-010-5
IN
V
DD
50
75
100
125
150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.0
1.5
1.0
AMBIENT TEMPERATURE IN
C
25
Dwg. GS-004-1
R = 55
C/W
JA
MOS
BIPOLAR
OUT
1
OUT
2
GROUND
Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
Copyright 1985, 2000 Allegro MicroSystems, Inc.
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
www.allegromicro.com
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 60 V (unless otherwise noted).
Limits @ V
DD
= 5 V
Limits @ V
DD
= 12 V
Characteristic
Symbol
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
Output Leakage Current
I
CEX
V
OUT
= 0 V, T
A
= +70
C
--
-5.0
-15
--
-5.0
-15
A
Output Voltage
V
OUT(H)
I
OUT
= -25 mA, V
BB
= 60 V
58
58.5
--
58
58.5
--
V
V
OUT(L)
I
OUT
= 1 mA
--
2.0
3.0
--
--
--
V
I
OUT
= 2 mA
--
--
--
--
2.0
3.0
V
Output Pull-Down Current
I
OUT(L)
V
OUT
= 10 V to V
BB
2.5
4.0
--
--
--
--
mA
V
OUT
= 40 V to V
BB
--
--
--
15
18
--
mA
Input Voltage
V
IN(1)
3.5
--
5.3
10.5
--
12.3
V
V
IN(0)
-0.3
--
+0.8
-0.3
--
+0.8
V
Input Current
I
IN(1)
V
IN
= V
DD
--
0.05
0.5
--
0.1
1.0
A
I
IN(0)
V
IN
= 0.8 V
--
-0.05
-0.5
--
-1.0
-1.0
A
Serial Data Output Voltage
V
OUT(H)
I
OUT
= -200
A
4.5
4.7
--
11.7
11.8
--
V
V
OUT(L)
I
OUT
= 200
A
--
200
250
--
100
200
mV
Maximum Clock Frequency
f
clk
3.3*
--
--
--
--
--
MHz
Supply Current
I
DD(H)
All Outputs High
--
3.0
5.0
--
15
20
mA
I
DD(L)
All Outputs Low
--
2.5
4.0
--
7.0
10
mA
I
BB(H)
Outputs High, No Load
--
7.5
12
--
7.5
12
mA
I
BB(L)
Outputs Low
--
10
100
--
10
100
A
Blanking to Output Delay
t
PHL
C
L
= 30 pF
--
300
550
--
125
150
ns
t
PLH
C
L
= 30 pF
--
250
450
--
170
200
ns
Output Fall Time
t
f
C
L
= 30 pF
--
1000
1250
--
250
300
ns
Output Rise Time
t
r
C
L
= 30 pF
--
150
170
--
150
170
ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Serial Data present at the input is transferred
to the shift register on the logic "0" to logic "1"
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
Dwg. No. 12,649A
TIMING REQUIREMENTS
(T
A
= +25
C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Input
Input I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Blanklng
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
H
L
L
L
... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
www.allegromicro.com
0.014
0.008
0.300
BSC
Dwg. MA-001-20 in
0.430
MAX
20
1
10
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
11
1.060
0.980
UCN5811A
Dimensions in Inches
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 18 devices.
PDF 
ZIP