ASAHI KASEI
[AK9813A]
DAD03E-00
1999/05
- 3 -
Pin Description(1)
No.
Pin Name
I/O
Function
20
DI
I
Serial Data Input Pin
SEL=High : 16bit data input format
SEL=Low : 14bit data input format
(SEL=High:CS I/F)
AK9813A reads out the data with LSB first in the 16bit
shift register to DO pin synchronously with falling
edge of CLK.
When the CS pin is high level, the DO pin becomes high
impedance. In STATUS mode, the DO pin outputs Ready/Busy
status.
17
DO
O
(SEL=Low:LD I/F)
AK9813A reads out the data with MSB first in the 14bit
shift register to DO pin synchronously with falling
edge of CLK.
In WRITE mode, the DO pin outputs Ready/Busy status.
19
CLK
I
Shift Clock Input Pin(Schmitt-trigger input)
AK9813A takes in the data from DI pin synchronously with
rising edge of the CLK pin. The data are transferred to
the internal shift register.
Chip Select Input Pin(Schmitt-trigger input)
The CS/LD is internally pulled up to VCC.
(SEL=High:CS I/F)
After the CS pin changes from high level to low level
while the CLK pin is high level, the AK9813A can input
the data to the internal shift register and takes in
the data from the DI pin synchronously with the rising
edge of the CLK pin.
After the CS pin changes from high level to low level
while the CLK pin is low level, the AK9813A becomes the
status mode and reads out the Ready/Busy status to the
DO pin.
When the CS pin changes from low level to high level
regardless of Low/High level of the CLK pin, the AK9813A
removes from the status mode to the normal mode. The CS
pin usually should be kept at high level.
18
CS/LD
I
(SEL=Low:LD I/F)
When the LD pin receives high pulse, the data of the
internal shift register is transferred to the internal
decoder or the register for D/A. The LD pin usually
should be kept at low level.
ASAHI KASEI
[AK9813A]
DAD03E-00
1999/05
- 4 -
Pin Description(2)
No.
Pin Name
I/O
Function
1
|
12
AO1
|
AO12
O
8bit D/A outputs with OP-AMP
14
Vcc
-
Digital section Power Supply Pin
23
GND
-
Digital section Ground Pin
13
Vdd
-
OP-AMP and D/A section Power Supply
24
Vss
-
OP-AMP and D/A section Ground
(SEL=High:CS I/F)
In AUTO READ operation and ECL operation, the address
of EEPROM is selected by the EA0 and the EA1 pins.
21
22
EA0
EA1
I
(SEL=Low:LD I/F)
The address of EEPROM is selected by the EA0 and the
EA1 pins.
16
ECL
I
When the ECL pin receives high pulse, the data in
EEPROM is automatically loaded to each corresponding
D/A, starting from AO1 to AO12 in order. Then each D/A
output is settled to pre-determined value.
15
SEL
I
Input Data Format Select Pin
SEL=High : CS I/F
SEL=Low : LD I/F
After power-up, this pin should be kept either at "high"
or "Low."
ASAHI KASEI
[AK9813A]
DAD03E-00
1999/05
- 5 -
Data Configuration
AK9813A have a shift register in order to control the chip.
When the SEL pin is "H"(CS I/F), the shift register becomes 16bit configuration and the data on the DI pin
should be loaded with LSB first. When the SEL pin is "L"(LD I/F), the shift register becomes 14bit
configuration and the data on the DI pin is loaded with MSB first.
The following description shows the configuration of the shift register.
The data set consist of 2-bits for the control of the internal EEPROM, 2-bits for the address of the EEPROM
(CS I/F only), 4-bits for select of D/A converter and 8-bits for the digital input data of the 8bit D/A converter and
total data set is 16bits or 14bits.
1
{
Shift register configuration : SEL=High(CS I/F)
OUTPUT VOLTAGE FOR D/A CONVERTER
D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE FOR D/A
A1
A0 EEPROM ADDRESS
0
0
0
0
0
0
0
0
=
GND=VSS
0
1 ADDRESS : 0
0
0
0
0
0
0
0
1
=
VDD/255
1
0
1 ADDRESS : 1
0
0
0
0
0
0
1
0
=
VDD/255
2
1
0 ADDRESS : 2
1
1 ADDRESS : 3
1
1
1
1
1
1
1
0
=
VDD/255
254
1
1
1
1
1
1
1
1
=
VDD
D/A CONVERTER CHANNEL SELECTION
D11 D10 D9 D8
D/A CHANNEL
D11 D10 D9 D8
D/A CHANNEL
0
0
0
0
Don't Care
1
0
0
0
AO8
0
0
0
1
AO1
1
0
0
1
AO9
0
0
1
0
AO2
1
0
1
0
AO10
0
0
1
1
AO3
1
0
1
1
AO11
0
1
0
0
AO4
1
1
0
0
AO12
0
1
0
1
AO5
1
1
0
1
Can't use
0
1
1
0
AO6
1
1
1
0
Can't use
0
1
1
1
AO7
1
1
1
1
Don't Care
(NOTE) Above "Don't care" state is valid only when AK9813A is in DAC mode or WRITE mode.
Refer to the following section "Instruction Set" about mode.
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