ASAHI KASEI
[AK5393]
M0038-E-04
2000/4
- 1 -
GENERAL DESCRIPTION
The
AK5393
is
a
24bit,
128x
oversampling
2ch
A/D
Converter
for
professional
digital
audio
systems.
The
modulator
in
the
AK5393
uses
the
new
developed
Enhanced
Dual
Bit
architecture.
This
new
architecture
achieves
the
wide
dynamic
range,
while
keeping
much
the
same
superior
distortion
characteristics
as
conventional
Single
Bit
way.
The
AK5393
performs
117dB
dynamic
range,
so
the
device
is
suitable
for
professional
studio
equipment
such
as
digital
mixer,
digital
VTR
etc.
FEATURES
p
Enhanced Dual Bit ADC
p
Sampling Rate: 1kHz~108kHz
p
Full Differential Inputs
p
S/(N+D): 105dB
p
DR: 117dB
p
S/N: 117dB
p
High Performance Linear Phase Digital Anti-Alias filter
Passband: 0~21.768kHz(@fs=48kHz)
Ripple: 0.001dB
Stopband: 110dB
p
Digital HPF & Offset Calibration for Offset Cancel
p
Power Supply: 5V
5%(Analog), 3~5.25V(Digital)
p
Power Dissipation: 470mW
p
Package: 28pin SOP
p
AK5392 Pin compatible
LRCK
VREFL
GNDL
SCLK
SMODE1
FSYNC
Serial Output
Interface
SMODE2
DGND
VA
AGND
BGND
CAL
RST
VD
Controller
SDATA
MCLK
DFS
HPFE
ZCAL
AINR-
GNDR
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Voltage
Reference
Voltage
Reference
Decimation
Filter
Decimation
Filter
HPF
HPF
Calibration
SRAM
VCOML
AINL+
AINL-
AINR+
VCOMR
VREFR
12
11
14
13
16
15
19
17
18
8
7
10
9
21
22
23
27
28
26
24
25
6
5
4
3
2
1
Enhanced Dual Bit
96kHz 24-Bit ADC
AK5393
ASAHI KASEI
[AK5393]
M0038-E-04
2000/4
- 2 -
n
Ordering Guide
AK5393-VS
10 ~ +70
C
28pin SOP
AKD5393
AK5393 Evaluation Board
n
Pin Layout
6
5
4
3
2
1
VREFL
GNDL
AINL+
VCOML
AINL-
ZCAL
VD
7
DGND
8
Top
View
10
9
CAL
RST
SMODE2
11
SMODE1
12
13
14
LRCK
SCLK
VREFR
GNDR
VCOMR
AINR+
AINR-
VA
AGND
BGND
TEST
HPFE
DFS
MCLK
23
24
25
26
27
28
22
21
19
20
18
17
16
15
FSYNC
SDATA
n
Compatibility with AK5392
AK5392
AK5393
Pin 18
CMODE
DFS
fs (max)
54kHz
108kHz
MCLK (DFS ="L"@fs=48kHz)
256fs/384fs
256fs
MCLK (DFS ="H"@fs=96kHz)
N/A
128fs
ASAHI KASEI
[AK5393]
M0038-E-04
2000/4
- 3 -
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
VREFL
O
Lch Reference Voltage Pin, 3.75V
Normally connected to GNDL with a 10F electrolytic capacitor and
a 0.1F ceramic capacitor.
2
GNDL
-
Lch Reference Ground Pin, 0V
3
VCOML
O
Lch Common Voltage Pin, 2.75V
4
AINL+
I
Lch Analog positive input Pin
5
AINL-
I
Lch Analog negative input Pin
6
ZCAL
I
Zero Calibration Control Pin
This pin controls the calibration reference signal.
"L" :VCOML and VCOMR
"H" : Analog Input Pins (AINL
, AINR
)
7
VD
-
Digital Power Supply Pin, 3.3V
8
DGND
-
Digital Ground Pin, 0V
9
CAL
O
Calibration Active Signal Pin
"H" means the offset calibration cycle is in progress. Offset calibration starts
when RST goes "H". CAL goes "L" after 8704 LRCK cycles for DFS="L",
17408 LRCK cycles for DFS ="H".
10
RST
I
Reset Pin
When "L", Digital section is powered-down. Upon returning "H", an
offset calibration cycle is started. An offset calibration cycle should always
be initiated after power-up.
11
12
SMODE2
SMODE1
I
I
Serial Interface Mode Select Pin
MSB first, 2's compliment.
SMODE2 SMODE1 MODE LRCK
L L Slave mode : MSB justified : H/L
L H Master mode : Similar to I
2
S : H/L
H L Slave mode : I
2
S : L/H
H H Master mode : I
2
S : L/H
13
LRCK
I/O
Left/Right Channel Select Clock Pin
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset
when SMODE1 "H".
ASAHI KASEI
[AK5393]
M0038-E-04
2000/4
- 4 -
14
SCLK
I/O
Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
15
SDATA
O
Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
16
FSYNC
I/O
Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I
2
S mode, FSYNC is
don't care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
17
MCLK
I
Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
18
DFS
I
Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
19
HPFE
I
High Pass Filter Enable Pin
"L": Disable
"H": Enable
20
TEST
I
Test Pin (pull-down pin)
Should be connected to GND.
21
BGND
-
Substrate Ground Pin, 0V
22
AGND
-
Analog Ground Pin, 0V
23
VA
-
Analog Supply Pin, 5V
24
AINR-
I
Rch Analog negative input Pin
25
AINR+
I
Rch Analog positive input Pin
26
VCOMR
O
Rch Common Voltage Pin, 2.75V
27
GNDR
-
Rch Reference Ground Pin, 0V
28
VREFR
O
Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10F electrolytic capacitor and a 0.1F
ceramic capacitor
Note: All digital inputs should not be left floating.
ASAHI KASEI
[AK5393]
M0038-E-04
2000/4
- 5 -
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Symbol
min
max
Units
Power Supplies: Analog
Digital
|BGND-DGND| (Note 2)
VA
VD
GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current, Any Pin Except Supplies
IIN
-
10
mA
Analog Input Voltage
VINA
-0.3
VA+0.3
V
Digital Input Voltage
VIND
-0.3
VD+0.3
V
Ambient Temperature (power applied)
Ta
-10
70
C
Storage Temperature
Tstg
-65
150
C
Notes: 1. All voltages with respect to ground.
2. AGND, BGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supplies: Analog
(Note 3) Digital
VA
VD
4.75
3.0
5.0
3.3
5.25
5.25
V
V
Notes: 1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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