Agilent HSDL-7002
IrDA
3/16 Encode/Decode
Integrated Circuit in QFN Package
Data Sheet
Description
The HSDL-7002 modulates and
demodulates electrical pulses
from HSDL-3201 IrDA
transceiver module and other
IrDA
compliant transceivers.
The HSDL-7002 can be used
with a microcontroller/
microprocessor that has a
serial communication interface
(UART).
Prior to communication, the
processor selects the
transmission baud rate. Serial
data is then transmitted or
received at the prescribed data
rate.
The HSDL-7002 consists or
two state machines the SIR
(Serial InfraRed) Encode and
SIR Decode blocks. It also
contains a sequential block
Clock Divide that synthesizes
the required internal signal.
The HSDL-7002 can be placed
into the Internal Clock Mode
or External Clock Mode. An
external crystal is needed for
the Internal Clock Mode. In
applications where the external
16XCLK signal is provided, a
crystal is not needed.
There are two data
transmission modes. Data can
be transmitter and received in
either a standard 3/16
modulation mode or a 1.63
s
pulse mode.
Features
Fully Compliant to IrDA
Physical
Layer Specification 1.4 from 9.6
kbit/s to 115.2 kbit/s (SIR)
Interfaces with IrDA
Compliant
IR Transceiver
Miniature Module Size with 16-
pin Quad-Flat-No Lead (QFN)
Package
Height : 0.8 mm
Length : 4.0 mm
Depth : 4.0 mm
Used in Conjunction with
Standard 16550 UART
Transmits/Receives either 1.63
s or 3/16 Pulse Mode
Internal or External Clock Mode
Programmable Baud Rate
2.7 5.5 V Operation
Lead Free and Green Product
Applications
Interfaces with IrDA
Transceiver
in:
Telecom Applications:
Mobile Phones
Modems
Pagers
Fax Machines
Computer Applications:
Notebook Computers
Desktop PCs
Dongles or other RS-232
adapters
PDAs
Printers
Handheld Data Collection:
Industrial
Medical
Transportation
Figure 1. Block Diagram of HSDL-7002
SIR
Encode
SIR
Decode
Clock
Divide
/TXD
/NRST
/IR_RXD
HSDL-7002
IR_TXD
A0
A1
A2
16XCLK
PULSEMOD
CLK_SEL
RXD
2
Order Information
Figure 2. HSDL-7002 Pin Configuration
Part Number
Packaging Type
Quantity
HSDL-7002
Tape and Reel
2500
I/O Pins Configuration Table
Marking Information
The unit is marked with A7002
and `yyww' on the chip.
yy = year
ww = work week
Note:
There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLK_SEL pin is asserted high (external clock select)
the oscillator is automatically put in powerdown mode, or whenever the POWERDN pin asserted high.
Pin Name
Type
Function
1
TXD
Digital In
Negative edge triggered input signal that is normally tied to the SOUT signal of
the UART (serial data to be transmitted). Data is modulated and output as
IR_TXD.
2
RXD
Digital Out
Output signal normally tied to SIN signal of a UART (received serial data).
RXD is the demodulated output of IR_RXD.
3
A0
Digital In
Clock Multiplex Signal
4
A1
Digital In
Clock Multiplex Signal
5
A2
Digital In
Clock Multiplex Signal
6
CLK_SEL
Digital In
Used to activate either the internal or external clock. A high on this line activated
the external clock (16XCLK) and a low activates the internal clock. When the
external clock is activated, the internal oscillator is put in POWERDN mode.
7
GND
Chip Ground
8
NRST
Digital In
Activate low signal used to reset the IrDA
SIR Encode & Decode state machine.
This signal can be tied to POR (Power-On-Reset) or Vcc.
9
IR_RXD
Digital In
Input from SIR optoelectronics. Input signal is a 3/16th or 1.63
s pulse that is
demodulated to generate RXD output signal.
10
IR_TXD
Digital Out
This is the modulated TXD signal.
11
PULSEMOD
Digital In
(with pull down)
A high level on this input put the chip into the monoshot transmit mode. In this
mode, when there is a negative transition on the TXD input, a rising edge on the
internal transmit modulation state machine will activate a high pulse on IR_TXD
for 6 crystal clock cycles. With a 3.6864 MHz crystal, this corresponds to 1.63
s.
This mode cannot be used in conjunction with the 16XCLK clock. It is meant to
be used with the external crystal clock. By default, this input pin is pulled to GND
12
POWERDN
Digital In
(with pull down)
A high on this input put only the internal oscillator cell in POWERDN mode. The
cell is normally not powered down.
13
OSCOUT
Analog Out
Oscillator Output
14
OSCIN
Analog In
Oscillator Input
15
Vcc
Power
16
16XCLK
Digital In
Positive edge triggered input clock that is set to 16 times the data transmission
baud rate. The encode and decode schemes require this signal. The signal is
usually tied to a UART's BAUDOUT signal. The 16XCLK may be provided by
application circuitry if BAUDOUT is not available. This signal is required when the
internal clock is not used.
PIN #1
CORNER
Pin 16
Pin 12
Pin 11
Pin 10
Pin 9
Pin 4
Pin 3
Pin 2
Pin 1
Pin 5
Pin 6
Pin 7
Pin 8
Pin 15
Pin 14
Pin 13
3
Absolute Maximum Ratings
Switching Specifications
(Vcc = 2.7 to 5.5 V, T
A
= -20 to +85C)
Notes:
1. Propagation Delay Time in the output buffer is the time taken from the input passing Vcc/2 to the time of the output reaching Vcc/2 with 50 pF as
the output load.
2. The Ouput Rise Time is the time taken for the outputs (RXD, IR_TXD) to rise from 10% of the original value to 90% of the final value.
3. The Output Fall Time is the time taken for the outputs (RXD, IR_TXD) to fall from 90% of the original value to 10% of the final value.
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
T
S
-65
+150
C
Operating Temperature
T
A
-40
+85
C
Output Current
I
O
-20
15
mA
Power Dissipation [1]
P
MAX
0.46
W
Input/Output Voltage [2]
V
I
/V
O
-0.5
Vcc+0.5
V
Power Supply Voltage
V
CC
-0.5
7.0
V
Electrostatic Protection
V
ESD
4000
V
Note: 1. All pins are protected from damage to static discharge by internal diode clamps to Vcc and GND.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Propagation Delay Time [1]
t
pd
45
ns
Output Rise Time [2]
t
rise
13
6
22
11
24
12
ns
V
CC
= 2.7 V, C
L
= 50 pF
VCC = 5.5 V, C
L
= 50 pF
Output Fall Time [3]
t
fall
12
5
14
10
16
11
ns
V
CC
= 2.7 V, C
L
= 50 pF
V
CC
= 5.5 V, C
L
= 50 pF
Output Capacitance on Output
Pads Used for Simulation
C
OUT
50
pF
4
Recommended Operating Conditions
(Vcc = 2.7 to 5.5 V, T
A
= -20 to +85 C)
Notes:
1. IrDA
Parameter. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7002's internal state machine. Under normal
circumstances, the clock input should not exceed 16*115.2 kbit/s or 1.8432 MHz. This product can operate at higher clock rates, but the above is the
recommended rate.
2. The Maximum Pulse Width (t
mpw
) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RXD pulse). As per the IrDA
Physical Layer Specification 1.4, the minimum pulse of the IR_TXD and IR_RXD pulses should be 3*(1/1.8432 MHz) or 1.63
s.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Supply Voltage
V
CC
2.7
5.0
5.5
V
Input Voltage
V
I
0
V
CC
V
Ambient Temperature
T
A
-20
+85
C
High Level Input Voltage
V
IH
0.7 V
CC
V
CC
V
Low Level Input Voltage
V
IL
0
0.3 V
CC
V
Output High Voltage
V
OH
2.6
V
V
CC
= 2.7 V
I
OH
= 2 mA
Output Low Voltage
V
OL
0.1
V
V
CC
= 2.7 V
I
OL
= 2 mA
Output High Voltage
V
OH
5.1
V
V
CC
= 5.5 V
I
OH
= 2 mA
Output Low Voltage
V
OL
0.1
V
V
CC
= 2.7 V
I
OL
= 2 mA
Static Power Dissipation
P
STAT
0.61
mW
Dynamic Power Dissipation
P
DYN
16.5
mW
Static Current Consumption
I
STAT
50
100
A
V
CC
= 2.7 V
V
CC
= 5.5 V
Dynamic Current Consumption
I
DYN
1.08
2.45
3
3
mA
V
CC
= 2.7 V
V
CC
= 5.5 V
Max Clk Frequency
(16XCLK) [1]
f16XCLK
18
MHz
Minimum Pulse Width
(IR_TXD) [2]
tmpw
1628
ns
Pulse Width on Monoshot
(IR_TXD and IR_RXD)
tmpw
1628
ns
Value of Pulldown Resistor used on
POWERDN & PULSEMOD input pins
RDWN
400
213
460
237
510
260
k
V
CC
= 2.7 V
V
CC
= 5.5 V
Trigger Low Level Input Voltage
(For NRST input pin)
VIL_TRIG
0.93
2.11
0.96
2.14
0.98
2.15
V
V
CC
= 2.7 V
V
CC
= 5.5 V
Trigger High Level Input Voltage
(For NRST input pin)
VIH_TRIG
1.68
3.22
1.69
3.23
1.70
3.25
V
V
CC
= 2.7 V
V
CC
= 5.5 V
5
HSDL-7002 Package Dimensions
PIN ASSIGNMENT
PIN 1
/TXD
PIN 9
/IR_RXD
PIN 2
RXD
PIN 10
IR_TXD
PIN 3
A0
PIN 11
PULSEMOD
PIN 4
A1
PIN 12
POWERDN
PIN 5
A2
PIN 13
OSCOUT
PIN 6
CLK_SEL
PIN 14
OSCIN
PIN 7
GND
PIN 15
VCC
PIN 8
/NRST
PIN 16
16XCLK
N
b
D2
E2
e
L
JEDEC
Min. Nom. Max.
Min.
Nom. Max.
Min. Nom. Max.
Min. Nom. Max.
16L
0.25
0.28
0.33
2.05
2.10
2.15
2.05
2.10
2.15
0.650 BSC.
0.55
0.60
0.65
MO-220VGGC
Symbol
Dimension in mm
Dimension in inch
Minimum
Nominal
Maximum
Minimum
Nominal
Maximum
A
-
0.80
0.84
-
0.031
0.033
A1
0.00
0.02
0.04
0.00
0.0008
0.0015
A3
0.20 REF.
0.008 REF.
D
3.85
4.00
4.15
0.152
0.157
0.163
E
3.85
4.00
4.15
0.152
0.157
0.163
JEDEC
MO-220
Figure 3. HSDL-7002 Package Dimensions
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