TACHYON*
Fibre Channel
Interface Controller
Product Overview
Description
TACHYON is a fundamental
building block compatible with
Hewlett-Packard's Fibre Chan-
nel solution which includes
interface controllers, physical
link modules, adapters, switches
and disk drives.
The TACHYON architecture
supports both networking and
mass storage connections to
provide a low cost, high perfor-
mance solution with low host
overhead.
Features
Single chip Fibre Channel
interface (no I/O processor
required)
Supports 1062.5, 531, and 266
MBaud links
Supports 3 topologies; direct
connect, fabric, and Fibre
Channel Arbitrated Loop
(FC-AL)
Supports Fibre Channel Class
1, 2, and 3 Services
Supports up to 2-Kbyte frame
payload for all classes of ser-
vice
Sequence segmentation/
reassembly in hardware
hH
Figure 1. TACHYON Internal Block Diagram
*
TACHYON (tak' - e - n)
1. a subatomic particle that only exists at
speeds faster than the speed of light.
2. HP's Fibre Channel Interface chip.
HPFC-5000
INBOUND
BLOCK
MOVER
SCSI
BUFFER
MANAGER
INBOUND
DATA
MANAGER
INBOUND
SEQUENCE
MANAGER
OS PROCESSOR/
CRC CHECKER
ELASTIC STORE/
SMOOTHING
BUFFER
16B/20B
ENCODER
LOOP/
N_PORT
STATE
MACHINE
20B/10B
MUX
20B/16B
DECODER
10B/20B
DE-MUX
SCSI
EXCHANGE
MANAGER
INBOUND
MESSAGE
CHANNEL
INBOUND
SFS & MFS
BUFFER
CHANNELS
SCSI
READ/WRITE
CHANNEL
SCSI
EXCHANGE
STATE
TABLE
OUTBOUND
BLOCK
MOVER
OUTBOUND
MESSAGE
CHANNEL
BACKPLANE
INTERFACE
DATA STRUCTURES IN THE HOST
FCP ASSISTS
SEQUENCE MANAGEMENT
GIGABIT LINK MODULE
RECEIVE
OUTBOUND
FRAME
FIFO
INBOUND
DATA
FIFO
ACK
FIFO
INBOUND
MESSAGE
QUEUE
MFS
BUFFER
QUEUE
SFS
BUFFER
QUEUE
OUTBOUND
COMMAND
QUEUE
HIGH
PRIORITY
COMMAND
QUEUE
INBOUND
DATA
OUTBOUND
DATA
OS/CRC
GENERATOR
TRANSMIT
ACKs
ACKs
OUTBOUND
SEQUENCE
MANAGER
hH
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
(408) 654-8675
Far East/Australasia: (65) 290-6305
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data Subject to Change
Copyright 1996 Hewlett-Packard Co.
Printed in U.S.A. 5965-1215E (7/96)
Features (continued)
Automatic ACK frame genera-
tion and processing
On-chip support of FCP for
SCSI Initiators and Targets
Supports up to 16,384 concur-
rent SCSI I/O transactions
Compliant with Internet MIB-
II network management
Direct interface to industry
standard 10 and 20-bit Giga-
bit Link Modules (GLM)
Hardware assists for TCP/
UDP/IP networking
Parity protection on internal
data path
Eight internal DMA channels
Full duplex internal architec-
ture that allows TACHYON to
process inbound and outbound
data simultaneously
Specifications
System Clock Frequency:
24-40 MHz backplane
operation
Operating Temperature:
0-50
C @ 0 m/s airflow,
0-70
C @ 1.5 m/s airflow
Testability:
Full internal scan path. IEEE
Standard 1149.1 Boundary
Scan
Packaging:
208-pin metal quad flat pack
Standards:
Intended to be compliant with
ANSI standards and FCSI/
FCA profile definitions
Figure 3. TACHYON Pin-out Block Diagram
Figure 2. System Adapter Card Block Diagram
TACHYON
BACKPLANE
INTERFACE
CHIP
GIGABIT
LINK
MODULE
CLK
TAD [31:0]
PARITY
AVCS_L
TYPE [2:0]
READY_L
PREFETCH_L
RETRY_L
ERROR_L
INT_L
RESET_L
TBR_L [1:0]
TBG_L
SCLK
PAR_ID [1:0]
RX [19:0]
RBC
COM_DET
L_UNUSE
LCKREF_L
EWRAP
FAULT
TX [19:0]
BACKPLANE
INTERFACE
GIGABIT
LINK MODULE
INTERFACE
TBC
TXCLK_SEL
TDI
TDO
TCK
TRST
TMS
BACKPLANE
CLOCK
GENERATOR
SCAN TEST
INTERFACE
GIGABIT
LINK
MODULE
RX
TACHYON
TX
LP2
RC
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