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Электронный компонент: HMMC-3008

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Agilent HMMC-3008
DC 16 GHz GaAs HBT MMIC
Divide-by-8 Prescaler
Data Sheet
Description
The HMMC-3008 GaAs HBT
MMIC prescaler offers DC to
16 GHz frequency translation for
use in communications and EW
systems incorporating high-
frequency PLL oscillator circuits
and signal-path down conversion
applications. The prescaler
provides a large input power
sensitivity window and low
phase noise. In addition to the
features listed above the device
offers an input disable contact
pad to eliminate any self-oscilla-
tion condition.
Features
Wide frequency range:
0.2 16 GHz
High input power sensitivity:
On-chip pre- and post-amps
-20 to +10 dBm (1 10 GHz)
-15 to +10 dBm (10 12 GHz)
-10 to +5 dBm (12 15 GHz)
Dual mode P
out
: (chip form)
+6.0 dBm (0.99 V
p-p
) @ 86 mA
0 dBm (0.5 V
p-p
) @ 66 mA
Low phase noise:
-153 dBc/Hz @ 100 kHz Offset
(+) or (-) single supply bias
operation
Wide bias supply range:
4.5 to 6.5 volt operating range
Differental I/O with on-chip 50
matching
Absolute Maximum Ratings
[1]
(@ T
A
= 25
C, unless otherwise indicated)
Symbol
Parameters/Conditions
Units
Min.
Max.
V
CC
Bias Supply Voltage
V
+7
V
EE
Bias Supply Voltage
V
-7
[V
CC
-V
EE
]
Bias Supply Delta
V
+7
V
Disable
Pre-amp Disable Voltage
V
V
EE
V
CC
V
Logic
Logic Threshold Voltage
V
V
CC
1.5
V
CC
1.2
P
in (CW)
CW RF Input Power
dBm
+10
V
RFin
DC Input Voltage (@ RF
in
or RF
in
Ports)
V
V
CC
0.5
T
BS
[2]
Backside Operating Temperature
C
-40
+85
T
stg
Storage Temperature
C
-65
+165
T
max
Max. Assembly Temp. (60 seconds max.)
C
310
Notes:
1. Operation in excess of any parameter limit (except T
BS
) may result in permanent damage to this
device.
2. MTTF > 2 x10
5
hours @ T
BS
< 85
C. Operation in excess of maximum operating temperature
(T
BS
) will degrade MTTF.
Chip Size:
1330 x 440
m (52.4 x 17.3 mils)
Chip Size Tolerance:
10
m (
0.4 mils)
Chip Thickness:
127
15
m (5.0
0.6 mils)
Pad Dimensions:
70 x 70
m (2.8 x 2.8 mils)
2
HMMC-3008 DC Specifications/Physical Properties
(@ T
A
= 25
C, V
CC
V
EE
= 5.0 volts, unless otherwise indicated)
Symbol
Parameters and Test Conditions
Units
Min.
Typ.
Max.
V
CC
V
EE
Operating bias supply difference
[1]
V
4.5
5.0
6.5
|I
CC
| or |I
EE
|
Bias supply current (High output power configuration
[2]
: V
PwrSel
= V
EE
)
mA
73
86
99
Bias supply current (Low output power configuration: V
PwrSel
= open)
mA
56
66
76
V
RFin(q)
Quiescent DC voltage appearing at all RF ports
V
V
CC
V
RFout(q)
V
Logic
Nominal ECL Logic Level
V
V
CC
1.45
V
CC
1.35
V
CC
1.25
(V
Logic
contact self-bias voltage, generated on-chip)
Notes:
1. Prescaler will operate over full specified supply voltage range. V
CC
or V
EE
not to exceed limits specified in Absolute Maximum Ratings section.
2. High output power configuration: P
out
= +6.0 dBm (V
out
= 0.99 V
p-p
), Low output power configuration: P
out
= 0 dBm (V
out
= 0.5 V
p-p
)
RF Specifications, (T
A
= 25
C, Z
O
= 50
, V
CC
V
EE
= 5.0 volts)
Symbol
Parameters and Test Conditions
Units
Min.
Typ.
Max.
in(max)
Maximum input frequency of operation
GHz
16
18
in(min)
Minimum input frequency of operation
[1]
GHz
0.2
0.5
(P
in
= -10 dBm)
Self-Osc.
Output Self-Oscillation Frequency
[2]
GHz
1.7
@ DC, (Square-wave input)
dBm
-15
>-25
+10
@
in
= 500 MHz, (Sine-wave input)
dBm
-15
> 20
+10
P
in
in
= 1 to 10 GHz
dBm
-15
>-25
+10
in
= 10 to 12 GHz
dBm
-10
>-15
+10
in
= 12 to 15 GHz
dBm
-4
>-10
+4
RL
Small-Signal Input/Output Return Loss
dB
15
(@
in
< 12 GHz)
S
12
Small-Signal Reverse Isolation
dB
30
(@
in
<12 GHz)
N
SSB Phase Noise (@ P
in
= 0 dBm, 100 kHz offset
dBc/Hz
-153
from a
out
= 1.2 GHz Carrier)
Jitter
Input signal time variation @ zero-crossing
ps
1
(
in
= 10 GHz, P
in
= -10 dBm)
r
or
f
Output edge speed (10% to 90% rise/fall time)
ps
70
Notes:
1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate.
2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Pre-amp Disable
(V
Disable
) feature, or the Differental Input de-biasing technique.
3
V
CC
Input Preamplifier Stage
RF
in
50
50
RF
in
V
EE
V
CC
V
EE
V
PwrSel
18/36 mA
Post Amplifier Stage
50
50
RFout
RFout
V
Disable
Divide Cell
8
Figure 1. HMMC-3008 Simplified Schematic.
HMMC-3008 RF Specifications, continued
High Output Power Operating Mode
[1]
(T
A
= 25
C, Z
O
= 50
, V
CC
V
EE
= 5.0V)
Symbol
Parameters and Test Conditions
Units
Min.
Typ.
Max.
@
out
< 1 GHz
dBm
4.0
6.0
P
out
@
out
= 1.25 GHz
dBm
4.0
6.0
@
out
= 1.5 GHz
dBm
3.7
5.7
@
out
< 1 GHz
volts
0.79
0.99
|V
out(p-p)
|
@
out
= 1.25 GHz
volts
0.79
0.99
@
out
= 1.5 GHz
volts
0.76
0.96
out
power level appearing at RF
in
or RF
in
dBm
-55
P
Spitback
(@
in
= 12 GHz, Unused RF
out
or RF
out
unterminated)
out
power level appearing at RF
in
or RF
in
dBm
-75
(@
in
= 12 GHz, Both RF
out
& RF
out
terminated)
P
feedthru
Power level of
in
appearing at RF
out
or RF
out
dBc
-30
(@
in
= 12 GHz, P
in
= 0 dBm, Referred to P
in
(
in
))
H
2
Second harmonic distortion output level
dBc
-30
(@
out
= 1.5 GHz, Referred to P
out
(
out
))
Low Output Power Operating Mode
[2]
@
out
< 1 GHz
dBm
-2
0
P
out
@
out
= 1.25 GHz
dBm
-2
0
@
out
= 1.5 GHz
dBm
-2.3
-0.3
@
out
< 1 GHz
volts
0.39
0.5
|V
out(p-p)
|
@
out
= 1.25 GHz
volts
0.39
0.5
@
out
= 1.5 GHz
volts
0.38
0.48
out
power level appearing at RF
in
or RF
in
dBm
-65
P
Spitback
(@
in
= 12 GHz, Unused RF
out
or RF
out
unterminated)
out
power level appearing at RF
in
or RF
in
dBm
-85
(@
in
= 12 GHz, Both RF
out
& RF
out
terminated)
P
feedthru
Power level of
in
appearing at RF
out
or RF
out
dBc
-30
(@
in
= 12 GHz, P
in
= 0 dBm, Referred to P
in
(
in
))
H
2
Second harmonic distortion output level
dBc
-35
(@
out
= 1.5 GHz, Referred to P
out
(
out
))
Notes:
1. V
PwrSel
= V
EE
.
2. V
PwrSel
= Open Circuit.
4
Applications
The HMMC-3008 is designed for
use in high frequency communi-
cations, microwave instrumenta-
tion, and EW radar systems
where low phase-noise PLL
control circuitry or broad-band
frequency translation is required.
Operation
The device is designed to operate
when driven with either a single-
ended or differential sinusoidal
input signal over a 200 MHz to
16 GHz bandwidth. Below
200 MHz the prescaler input is
"slew-rate" limited, requiring fast
rising and falling edge speeds to
properly divide. The device will
operate at frequencies down to
DC when driven with a square-
wave.
The device may be biased from
either a single positive or single
negative supply bias. The back-
side of the device is not DC
connected to any DC bias point
on the device.
For positive supply operation V
CC
is nominally biased at any
voltage in the +4.5 to +6.5 volt
range with V
EE
(or V
EE
& V
Pwr-Sel
)
grounded. For negative bias
operation V
CC
is typically
grounded and a negative voltage
between -4.5 to -6.5 volts is
applied to V
EE
(or V
EE
& V
PwrSel
).
Several features are designed
into this prescaler:
1) Dual-Output Power Feature
Bonding both V
EE
and V
PwrSel
pads to either ground (positive
bias mode) or the negative
supply (negative bias mode), will
deliver ~0 dBm [0.5V
p-p
] at the
RF output port while drawing
~40 mA supply current. Elimi-
nating the V
PwrSel
connection
results in reduced output power
and voltage swing, -6.0 dBm
[0.25V
p-p
] but at a reduced
current draw of ~30 mA result-
ing in less over-all power dissipa-
tion. (NOTE: V
EE
must ALWAYS
be bonded and V
PwrSel
must
NEVER be biased to any poten-
tial other than V
EE
or open-
circuited.)
2) V
Logic
ECL Contact Pad
Under normal conditions no
connection or external bias is
required to this pad and it is self-
biased to the on-chip ECL logic
threshold voltage (V
CC
1.35V).
The user can provide an external
bias to this pad (1.5 to 1.2 volts
less than V
CC
) to force the
prescaler to operate at a system
generated logic threshold voltage.
3) Input Disable Feature
If an RF signal with sufficient
signal to noise ratio is present at
the RF input, the prescaler will
operate and provide a divided
output equal to the input fre-
quency divided by the divide
modulus. Under certain "ideal"
conditions where the input is
well matched at the right input
frequency, the device may "self-
oscillate", especially under small
signal input powers or with only
noise present at the input. This
"self-oscillation" will produce an
undesired output signal also
known as a false trigger. By
applying an external bias to the
input disable contact pad (more
positive than V
CC
1.35V), the
input preamplifier stage is locked
into either logic "high" or logic
"low" preventing frequency
division and any self-oscillation
frequency which may be present.
4) Input DC Offset
Another method used to prevent
false triggers or self-oscillation
conditions is to apply a 20 to
100 mV DC offset voltage be-
tween the RF
in
and RF
in
ports.
This prevents noise or spurious
low level signals from triggering
the divider.
Adding a 10K
resistor between
the unused RF input to a contact
point at the V
EE
potential will
result in an offset of
25mV
between the RF inputs. Note
however, that the input sensitiv-
ity will be reduced slightly due to
the presence of this offset.
Assembly Techniques
Figure 3 shows the chip assembly
diagram for single-ended I/O
operation through 12 GHz for
either positive or negative bias
supply operation. In either case
the supply contact to the chip
must be capacitively bypassed to
provide good input sensitivity
and low input power feedthrough.
Independent of the bias applied
to the device, the backside of the
chip should always be connected
to both a good RF ground plane
and a good thermal heat sinking
region on the mounting surface.
All RF ports are DC connected
on-chip to the V
CC
contact
through on-chip 50
resistors.
Under any bias conditions where
V
CC
is not DC grounded, the RF
ports should be AC coupled via
series capacitors mounted on the
thin-film substrate at each RF
port. Only under bias conditions
where V
CC
is DC grounded (as is
typical for negative bias supply
operation) may the RF ports be
direct coupled to adjacent cir-
cuitry or in some cases, such as
level shifting to subsequent
stages. In the latter case the
device backside may be "floated"
and bias applied as the difference
between V
CC
and V
EE
.
All bonds between the device and
this bypass capacitor should be
as short as possible to limit the
inductance. For operation at
frequencies below 1 GHz, a large
value capacitor must be added to
provide proper RF bypassing.
5
Figure 2. Pad Locations and Chip Dimensions.
0
440
0
RF
in
220
70
370
70
650
800
950
1090
1260
350
230
900
260
500
1330
RF
in
V
CC
V
CCBypass
No Connection
V
PwrSel
V
Logic
V
Disable
V
EE
V
CC
V
CC
RF
out
RF
out
V
CC
Notes:
All dimensions in microns.
All Pad Dim: 70 x 70
m
(except where noted)
Tolerances:
10
m
Chip Thickness: 127
15
m
Due to on-chip 50
matching
resistors at all four RF ports, no
external termination is required
on any unused RF port. However,
improved "Spitback" perfor-
mance (~20 dB) and input sensi-
tivity can be achieved by termi-
nating the unused RFout port to
V
CC
through 50
(positive
Optional DC Operating Values/Logic Levels (T
A
= 25
C)
Function
Symbol
Conditions
Min.
Typical
Max.
(volts/mA)
(volts/mA)
(volts/mA)
Logic Threshold
[1]
V
Logic
V
CC
1.5
V
CC
1.35
V
CC
1.2
V
Disable(High)
[Disable]
V
Logic
+ 0.25
V
Logic
V
CC
Input Disable
V
Disable(Low)
[Enable]
V
EE
V
Logic
V
Logic
0.25
I
Disable
V
D
> V
EE
+ 3
(V
Disable
V
EE
3)/500
(V
Disable
V
EE
3)/500
(V
Disable
V
EE
3)/500
V
D
< V
EE
+ 3
0
0
0
Note:
1. Acceptable voltage range when applied from external source.
supply) or to ground via a 50
termination (negative supply
operation).
GaAs MMICs are ESD sensitive.
ESD preventive measures must
be employed in all aspects of
storage, handling, and assembly.
MMIC ESD precautions, handling
considerations, die attach and
bonding methods are critical
factors in successful GaAs MMIC
performance and reliability.
Agilent application note #54,
"GaAs MMIC ESD, Die Attach
and Bonding Guidelines" pro-
vides basic information on these
subjects.