eroflex Circuit T

echnology

 Data Bus Modules For The Future © SCDCT2566 REV B 8/10/99

Features

· Second Source

Compatible to the

BUS-66300

· PGA Version available, (second source to the BUS-66312)
· Compatible with MIL-STD-1750 CPUs
· Compatible with MOTOROLA, INTEL, and ZILOG CPUs
· Compatible with Aeroflex's CT2565 BC/RT/MT and CT2512 RT
· Minimizes CPU overhead
· Signal controls for shared memory implementation
· Transfers complete messages to shared memory
· Provides memory mapped 1553 interface
· Packaging Hermetic Metal

· 78 Pin, 2.1" x 1.87" x .25" PGA type package
· 82 Lead, 2.2" x 1.61 x .18" Flat Package

Description

Aeroflex CT2566 MIL-STD-1553 to Microprocessor Interface Unit simplifies the CPU to 1553 Data

Bus interface. The CT2566 provides an interface by using RAM allowing the CPU to transmit or
receive 1553 traffic simply by accessing the memory. All 1553 message transfers are entirely
memory or I/O mapped. The CT2566 supports 1553 interface devices such as Aeroflex's CT2512
dual RT or the CT2565 dual BC, RT, and MT. The CT2566 operates over the full military -55°C to
+125°C temperature range.

Figure 1 Functional Block Diagram

CT2566

MIL-STD-1553 to Microprocessor

CIRCUIT TECHNOLOGY

www.aeroflex.com

Interface Unit

R T

L E

X L A

ISO

9001

CLOCK IN

MSTRCLR

SELECT

STRBD

READYD

RD/WR

MEM/REG

EXTEN
EXTLD

INT

IOEN
BUSREQ
BUSGRNT
BUSACK

OE
WR

MEMOE

MEMCS

MEMWR
ADRINC
NBGRNT
BCSTART
TAGEN

EOM
SOM

MSGERR
TIMEOUT
STATERR
LOOPERR
CHB/CHA

CTLINB/A
CTLOUT B/A
RTU/BC
MT
DBAC
SSBUSY
SSFLAG
SVCREQ
RESET

OPERATION

CONTROL

REGISTERS

CONFIGURATION

REGISTER

START / RESET

REGISTER

INTERRUPT

MASK

REGISTER

INTERRUPT

GENERATOR

BLOCK

STATUS

WORD

MICROCODE

CONTROLLER

CONTENTION

RESOLVER

MEMORY

TIMING

CPU

A15-A00

D15-D00

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

GENERAL

The CT2566 was designed to perform required

handshaking to the 1553 interface device, storing
or retrieving message(s) from a user supplied
RAM and notifying the CPU that a 1553
transaction has occurred. The CPU uses this
RAM to read the received data as well as to store
messages to be transmitted onto the Bus.

The CT2566 can be used to implement BC, RT,

or MT operation and can be either memory
mapped or I/O mapped to CPU address space.
Registers internal to the CT2566 control its
operation.

The CT2566 can access up to four external,

user supplied registers and can address up to
64K words of RAM. The RAM selected must be a
non-latched static RAM (capable of meeting the
timing constraints for the CT2566). A double

buffering architecture is provided to prevent
incomplete or partially updated information from
being transmitted onto the 1553 Data Bus.

The CT2566 requires an external, user supplied

clock.

COMPATIBLE MICROPROCESSOR TYPES

The CT2566 may be used with most common

microprocessors, including, the Motorola 68000
family, the Intel 8080 family, Zilog Z8000
products, and available MIL-STD-1750
processors.

Interfacing the CT2566 to the 1553 Data Bus

requires external circuitry such as Aeroflex's
CT2565(BC/RT/MT) and ACT4489D
transceivers. Figure 2 shows the interconnection
for these components.

Specifications at Nominal Power Supply Voltages

PARAMETER

VALUE

UNITS

Logic

(With V

= 2.7V)

630

µA

(With V

= 0.0V)

700

µA

4.0 min

4.0

2.0

0.8

3.7

0.4

Clock

MHz

Power Supplies

Voltage

5.0±10%

Current Drain

10 typ

Temperature Range

Operating (Case)

55 to +125

°C

Storage

65 to +150

°C

Physical Characteristics

Size

78 pin DIP

2.1 x 1.87 x 0.25

(53 x 47.5 x 6.4)

(mm)

82 pin flatpack

2.1 x 1.87 x 0.25

(55.6 x 40.6 x 3.71)

(mm)

Weight

78 pin DIP

1 (28)

oz (g)

82 pin flatpack

1 (28)

oz (g)

Table 1 Specifications

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

PIN NO.

NAME

I/O

DESCRIPTION

SELECT

Select. When active, selects CT2566 for operation.

RD/WR

Read/Write. Controls CPU bus data direction.

READYD

Ready Data. When active indicates data has been received
from, or is available to the CPU.

EXTEN

External Enable. Output from CT2566 to enable output from
external devices. Same timing as MEMOE.

TAGEN

Tag Enable. Enables an external time tag counter for
transferring the time tag word into memory.

EOM

End of Message. Input from 1553 device indicating end of
message.

SOM

Start of Message. Input from 1553 device indicating start of
message in RTU mode.

STATERR

Status Error. Input from 1553 device when status word has
either a bit set or unexpected RT address (in BC mode only).

ADRINC

Address Increment. Sent from 1553 device to increment
address counter following word transfer.

MEM/REG

Memory/Register. Input from CPU to select memory or
register data transfer.

CLOCK IN

Clock input; 50% duty cycle, 12MHz, max.

LOOPERR

Loop Error. Input from 1553 device if short loop BIT fails.

BUSREQ

Bus Request. When active, indicates 1553 device requires
use of the address/data bus.

BUSGRNT

Bus Grant. Handshake output to 1553 device in response to
BUS REQUEST indicating address/data bus available to
1553 device.

Not Used

MEMCS

Memory Chip Select. Low from CT2566 to enable external
RAM. Used with 4K x 4 RAM type device to read RAM or
used in conjunction with MEMWR to write data into RAM.

Output Enable. Input from 1553 device used to enable
memory on the parallel bus.

N/C

Not Used.

NBGRNT

Low pulse from 1553 device preceding start of received new
protocol sequence. Used with superseding command to reset
DMA in progress.

+ 5 Volt

Logic power supply.

D15

I/O

Data Bus Bit 15 (MSB).

D13

I/O

Data Bus Bit 13.

D11

I/O

Data Bus Bit 11.

D09

I/O

Data Bus Bit 9.

D07

I/O

Data Bus Bit 7.

D05

I/O

Data Bus Bit 5.

D03

I/O

Data Bus Bit 3.

Table 2 Pin Functions (78 Pin DIP)

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

D01

I/O

Data Bus Bit 1.

SSFLAG

Subsystem Flag. Output to 1553 device to set RT subsystem
flag status bit.

SSBUSY

Subsystem Busy. Output to 1553 device to set RT subsystem
busy flag.

RTU/BC

Output to 1553 device used in conjunction with MT to set
operating mode.

A14

Address Bit 14.

A12

Address Bit 12.

A10

Address Bit 10.

A08

Address Bit 8.

A06

Address Bit 6.

A04

Address Bit 4.

A02

I/O

Address Bit 2.

A00

I/O

Address Bit 0 (LSB).

GND

Signal Return.

STRBD

Strobe Data. Used in conjunction with SELECT to indicate a
data transfer cycle to/from CPU.

IOEN

Input/Output Enable. Output from CT2566 to enable external
buffers/latches connecting the hybrid to the address/data
bus.

EXTLD

External Load. Used to load data into external device via the
CT2566 data bus. Same timing as MEMWR.

CHB/CHA

Input from 1553 in RT mode used to indicate received 1553
message came in either Channel A or B.

INT

Interrupt. Interrupt pulse line to CPU.

BCSTART

Bus Controller Start. Outputs to 1553 in initiate BC cycle.

RESET

Reset. Output to external device from CT2566 consisting of
the OR condition of CPU reset and CPU Master Clear.

MSGERR

Message Error. Input from 1553 device when an error occurs
in message sequence.

CTLIN B/A

Input to change active memory map area (0 = area A).

CTLOUT B/A

Output from CT2566 selecting which area is to be active (0 =
area A).

TIMEOUT

Input from 1553 device indicating no response time-out.

MSTRCLR

Master Clear. Power-on reset from CPU. Resets DMA in
progress and internal registers to logic "0".

BUSACK

Bus Acknowledge. Input from 1553 device acknowledge
receipt of BUSGRNT.

Write. Input from 1553 device for writing data into memory.

Chip Select. Input from 1553 device that is routed to
MEMCS.

PIN NO.

NAME

I/O

DESCRIPTION

Table 2 Pin Functions (78 Pin DIP) (Cont.)

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

MEMOE

Memory Output Enable. Output from CT2566 to enable
memory output data.

MEMWR

Memory Write. Output pulse from CT2566 to write data bus
data into memory.

Not Used

Bus Monitor. Used in conjunction with RTU/BC to set
operating mode.

D14

I/O

Data Bus Bit 14.

D12

I/O

Data Bus Bit 12.

D10

I/O

Data Bus Bit 10.

D08

I/O

Data Bus Bit 8.

D06

I/O

Data Bus Bit 6.

D04

I/O

Data Bus Bit 4.

D02

I/O

Data Bus Bit 2.

D00

I/O

Data Bus Bit 0 (LSB).

SVCREQ

Service Request. Used to set service request bit in RT Status
Word.

DBAC

Dynamic Bus Acceptance. Used to set status bit in RT Status
Word.

A15

Address Bit 15 (MSB).

A13

Address Bit 13.

A11

Address Bit 11.

A09

Address Bit 9.

A07

Address Bit 7.

A05

Address Bit 5.

A03

Address Bit 3.

A01

I/O

Address Bit 1.

GND

Chassis Ground.

PIN NO.

FUNCTION

PIN NO.

FUNCTION

N/C

SELECT

GROUND

STRBD

CHASSIS GROUND

RD/WR

A00 (LSB)

IOENBL

A01

READYD

A02

EXTLD

A03

Table 3 CT2566FP Pin Functions (82 Pin Flat Package)

PIN NO.

NAME

I/O

DESCRIPTION

Table 2 Pin Functions (78 Pin DIP) (Cont.)

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

EXTEN

A04

CHB/CHA

A05

TAGEN

A06

INT

A07

EOM

A08

BCSTART

A09

SOM

A10

RESET

A11

STATERR

A12

MSGERR

A13

ADRINC

A14

CTLIN B/A

A15

MEM/REG

RTU/BC

CTLOUT B/A

DBAC

CLOCK IN

SSBUSY

TIMEOUT

SVCREQ

LOOPERR

SSFLAG

MSTRCLR

D00

BUSYREQ

D01

BUSACK

D02

BUSGRNT

D03

D04

N/C

D05

D06

MEMCS

D07

MEMOE

D08

D09

MEMWR

D10

Not Used

D11

N/C

D12

NBGRNT

D13

D14

+5V

D15

N/C

PIN NO.

FUNCTION

PIN NO.

FUNCTION

Table 3 CT2566FP Pin Functions (82 Pin Flat Package) (Cont.)

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

MEMORY MANAGEMENT

The RAM used by the CT2566 can be any standard

static memory with a WRITE STROBE pulse width
requirement less than 70ns. The RAM area is broken
down into pointers, look-up tables, and data blocks. All
1553 operation control is accomplished through the
RAM, including fault monitoring and data block
transfers.

For most applications, a 4K x 16 memory is sufficient

to store the number of messages, but the CT2566 can
access up to 64K words.

DOUBLE BUFFERING

A Double Buffering system is available to prevent

partially updated data blocks from being read by the
CPU or transferred onto the 1553 Data Bus. To use
Double Buffering the CPU must divide the RAM into
two areas: "current" and "non-current". Two Stack
Pointers, Descriptor Stacks, and Look-Up Tables are
required to be used by the CPU.

The 1553 device has access only to the current area

of RAM, and will use the current Descriptor Stack and
Look-Up Table. While the 1553 device is processing
messages using the current area pointers, the CPU
can be setting up the next set of messages in the
non-current area of RAM.

Once an EOM or BCEOM occurs, the CPU can swap

the current and non-current areas by toggling bit 13 of
the Configuration Register (See register section for
description). The 1553 device will then have access to
the new current area. Meanwhile, the CPU can begin
processing the data received during the previous
transfer or can begin setting up the next set of 1553
messages.

An external circuit (shown in Figure 3) can be added

to ensure that the swapping of the current and
non-current areas doesn't occur while the CT2566 is
processing a message from the 1553 device. During
message processing, the INCMD is a logic "0" and the
CPU's map area selection is inhibited. CTLIN B/A will
be automatically latched back into the CT2566 when
INCMD and NODT change to a logic "1".

DESCRIPTOR STACK

The CT2566 uses a Descriptor Stack in BC and RTU

modes. Each stack entry contains four words which
refer to one 1553 message (See Figure 4). The Block
Status Word, shown in Figure 5, indicates the physical
bus which received the message (RTU mode), reports
whether or not an error was detected during message
transfer, and indicates whether the message was
completed (SOM replaced with EOM).

The user-supplied Time-Tag word is loaded at the

start of a message transfer and is updated at the end of
the transfer.

The contents of the fourth word in the Descriptor

Stack depends on the operating mode. In BC mode, it
contains the address of the message data block
containing the 1553 message formatted as shown in
Figure 6. In RTU mode, the word contains the received
1553 Command Word as shown in Figure 7.

A Stack Pointer must be initialized by the CPU. The

Descriptor Stack contains 64, four word entries, and

automatically wraps around (the 64th entry is followed
by the first entry). The 1553 device uses the current
area Stack Pointer to determine the address of the
Stack entry to be used for the current 1553 message.
The CT2566 automatically increments the current area
Stack Pointer by four upon the completion of each

-
6

Figure 3 Synchronized map switching u

the CT2566

INCMD
NODT
12 MHz

50 CTLOUT B/A

49 CTLIN B/A

Notes:
(1) INCMD is from the BUS-65600 or BUS-65112.
(2) CTLOUT B/A reflects bit 13 of the Configuration Register.
(3) CTLIN B/A is used to select the current area.

LS74

BLOCK STATUS WORD

TIME TAG WORD

RESERVED

MESSABE BLOCK ADDRESS

BC DESCRIPTION BLOCK

BLOCK STATUS WORD

TIME TAG WORD

RESERVED

RECEIVED COMMAND WORD

RTU DESCRIPTION BLOCK

Figure 4 Descriptor Stack Entries

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

message regardless of whether or not an error was
detected during the processing of that message.

LOOK-UP TABLES

In RTU mode a Look-Up Table is provided to allow

the CT2566 to store messages in distinct areas of RAM
based upon the subaddress of the received command
word. See RTU operation for details.

The CT2566 uses the T/R and the five subaddress

bits to form a pointer into the "current area" Look-Up
Table. The first 32 words of this table are initialized by
the user with the addresses of the data blocks to be
used for receiving data into subaddress 0,1,2,...31.
The next 32 words are initialized by the user with the
address of the data blocks to be used when
transmitting data from subaddress 0,1,2,...31.

CT2566 REGISTERS

The CT2566 is controlled through the use of three

internal registers: the Interrupt Mask Register,
Configuration Register, and Start/Reset Register. In

addition, the CT2566 can access up to four external,
user supplied registers. Possible external register
applications include: defining the RTU address, storing
a CPU Time Tag, and reading a captured Built-In-Test
(BIT) Word from the 1553 interface unit. For further
information, consult factory.

Table 2 Internal Registers Address Definition

CT2566
Address Bits

Definition

Interrupt Mask Register

Configuration Register

Not Used

Start/Reset Register (write
only)

External Register

15 14 13 12 11 10

SUBSYSTEM FLAG

SERVICE REQUEST

BUSY

DB ACCEPT

STOP ON ERROR

CONTROL AREA BIT B/A

RTU/BC

BIT

DEFINITIONS

SUBSYSTEM FLAG

1553 status word bit.

SERVICE REQUEST

1553 status word bit.

BUSY

1553 status word bit.

DB ACCEPT

1553 status word bit.

STOP ON ERROR

Causes BC to stop at the end of current data block if an error is detected.

CONTROL AREA B/A

Used for double buffering (See Double Buffering).

RTU/BC/MT

Operating Mode.

Bit 15 Bit 14

Mode

RTU

ILLEGAL

Figure 8 Configuration Register

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

15 14 13 12 11 10

LOOP TEST FAIL

RESPONSE TIME OUT (BC ONLY)

FORMAT ERROR

STATUS SET (BC ONLY)

ERROR FLAG

CHB/CHA (RTU ONLY)

SOM

EOM

Note: In BC mode Bit 13, CHB/CHA contains a logic "0" regardless of which channel is used.

Note: (1) User may opt to share memory block(s).
(2) See Figure 19.

Figure 5 Block Status Word

Figure 6 Use of Descriptor Stack BC Mode

Note: User may opt to share memory block(s).

Figure 7 Use of Descriptor Stack RTU Mode

DESCRIPTOR

STACKS

STACK

POINTERS

CONFIGURATION

REGISTER

CURRENT
AREA B/A

DATA

BLOCKS

DATA BLOCK

BLOCK STATUS WORD

RESERVED

TIME TAG WORD

MESSAGE

BLOCK ADDR

DESCRIPTOR

STACKS

STACK

POINTERS

CONFIGURATION

REGISTER

CURRENT
AREA B/A

DATA

BLOCKS

DATA BLOCK

LOOK-UP TABLE

(DATA BLOCK ADDR)

LOOK-UP

TABLE ADDR

(2)

(1)

BLOCK STATUS WORD

RESERVED

TIME TAG WORD

RECEIVED COMMAND

WORD

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

INTERRUPT MASK REGISTER

This register is an eight bit read/write register used to enable the interrupt conditions. All interrupts are enabled

with a logic "1" (See Figure 9).

START/RESET REGISTER

Only two bits of this write only register are used, as illustrated in Figure 10.

NOT USED

BC EOM

FORMAT ERROR/STATUS SET

NOT USED

EOM

INTERRUPT

DEFINITION

EOM

End of Message. Set by CT2566 (during BC or RTU mode) every time a
1553 message is transferred (regardless of validity).

FORMAT ERROR/

Set by CT2566 for these conditions:

STATUS SET

Loop Test Failure: Last transmitted word did not match received word.

Message Error: Received message contained an address error, one of
eight 1553 status bits set, or 1553 specification violated (parity error,
Manchester error, etc).

Time-Out: Expected transmission was not received during allotted time

Status Set: Received status word contained status bit(s) set or address
error.

BC EOM

Bus Controller End of Message. Set by CT2566 (in BC mode) when all
messages have been transferred.

Figure 9 Interrupt Mask Register

NOT USED

CONTROLLER START

RESET

BIT

DEFINITION

RESET

Issued by the CPU to place the CT2566 in the power-on condition;
Configuration, and Interrupt Mask registers are reset to logic "0".

CONTROLLER START

Issued by the CPU (BC mode) to start message transmission. The CPU
must first load the number of messages to transfer (256, max) in the
message count location of RAM (area A or B). Value is loaded in 1's
complement (load FFFE to transmit one message). In MT mode it is
used to begin reception of 1553 messages. Issued by CPU in MT mode
to enable monitor operation.

Figure 10 Start/Reset Register

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

BC Operation

The BC mode is selected by setting the two MSBs of

the Configuration Register to logic "0". This can be done
by writing directly to the register or by issuing a
MSTRCLR or RESET command. Note that a RESET
will also clear the Interrupt Mask Register.

BC Initialization.
For BC operation, the user initializes the RAM as

shown in Table 3 and follows the steps in Figure 11, BC
Initialization. The CPU loads the data blocks with 1553
messages (See Figure 12). The first word of each data
block must contain the Control Word (shown in Figure
13) for the message. The starting addresses of the data
blocks are placed in the fourth word of the Descriptor
Stack in the order the messages are to be transmitted
(i.e. the address of the first message is loaded into the
fourth location of the Stack, the address of the second
message is placed into the eighth location, etc). Once
the data blocks and the Descriptor Stack have been
initialized, the CPU loads the current area message
count with the number of messages to transfer (load in
1's complement).

Table 3 - Typical BC Memory Map

(4K memory)]

HEX ADDRESS

FUNCTION

Fixed Areas

0100

Stack Pointer A

0101

Message Count A

0104

Stack Pointer B

0105

Message Count B

User Defined Areas

0108-013F

Not Used

0140-017F

Data Block 1

0180-01BF

Data Block 2

01C0-01FF

Data Block 3

0F00-0FFF

Descriptor Stack A

0000-00FF

Descriptor Stack B

CONTROL

WORD

CONTROL

WORD

CONTROL

WORD

CONTROL

WORD

CONTROL

WORD

CONTROL

WORD

RECEIVE

COMMAND

TRANSMIT

COMMAND

RECEIVE

COMMAND

MODE

COMMAND

TRANSMIT

COMMAND

BROADCAST

COMMAND

CONTROL

WORD

MODE

COMMAND

MODE

COMMAND

DATA WORD

LAST

STATUS

WORD

STATUS

WORD

STATUS

WORD

DATA WORD

LAST

DATA WORD

LAST

STATUS

RECEIVE

DATA WORD

1 RECEIVED

DATA WORD

2 RECEIVED

DATA WORD

RECEIVED

STATUS

RECEIVED

STATUS

WORD 1

FROM XMTR

STATUS

WORD 2

RECEIVER

FROM

TERMINAL TO

TERMINAL

LAST DATA

WORD

RECEIVED

DATA WORD

LOOPED

CT2565

BACK BY

REMOTE

DATA BLOCK

COMMAND

BACK BY

TRANSMIT

LOOPED

CT2565

COMMAND

BACK BY

BROADCAST

LOOPED

CT2565

COMMAND

BACK BY

MODE

LOOPED

CT2565

COMMAND

BACK BY

MODE

LOOPED

CT2565

DATA WORD

BACK BY

LOOPED

CT2565

LAST

BACK BY

DATA WORD

LOOPED

CT2566

TRANSMIT

DATA BLOCK

RECEIVE

DATA BLOCK

WITH DATA

DATA BLOCK

MODE CODE

TRANSMIT

FORMAT

COMMAND

BACK BY

TRANSMIT

LOOPED

CT2565

WITH DATA

DATA BLOCK

MODE CODE

RECEIVE

FORMAT

MODE CODE

WITHOUT

DATA

BROADCAST

COMMAND
WITH DATA

BROADCAST

COMMAND

(NO DATA)

BROADCAST

COMMAND

(NO DATA)

Figure 12 BC Message Data Block Formats

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

The CPU selects an internal register by asserting

MEM/REG and the A2 bit to logic "0" (See Table 2).
External registers are selected by asserting MEM/REG
logic "0" and A2 bit to a logic "1". The signals EXTEN
and EXTLD are used to read and write from the
external registers (See Figures 26 to 28).

Configuration Register

The Configuration Register is an eight bit read/write

register used to define the 1553 operating mode (BC,
MT, or RTU) and the associated RTU status bits. The
four MSBs define the mode of operation; the four LSBs
define the RTU status bits (See Figure 8).

All bits in the Configuration Register (except bit 12)

will be present on the respective CT2566 output pins to
the 1553 device. The MT bit is inverted at the output.

To begin transferring messages onto the bus, the

CPU must issue a Controller Start Command (See
Figure 14). This is done by setting bit 1 of the
Start/Reset Register to a logic "1". An EOM interrupt
will be generated each time a message transfer has
been completed. A BCEOM will be generated once the
specified number of messages has been transferred
(message counter = FFFF).

A Format Error Status Set Interrupt will be generated

at the end of a message if a timeout condition or error
condition was detected. If the STOP ON ERROR bit in
the Configuration Register is set, the CT2566 will stop
bus transactions until a new Controller Start command
is issued by the CPU. These interrupts may be masked
by the CPU through the Interrupt Mask Register.

BC START SEQUENCE

After setting the CONTROLLER START bit in the

Start/Reset Register, the CT2566 takes the following
actions:

1. Reads the Stack Pointer to get the address of the

current Descriptor Stack Entry.

2. Stores an SOM flag in the Block Status Word to

indicate a transfer operation is in progress.

3. Stores the Time Tag if used.
4. Reads the Data Block Address from the fourth

location of the Descriptor Stack and transfers the
Data Block Address into an internal Address
Register.

5. Issues a BCSTART pulse to the associated 1553

device to start the message transfers.

Note that data words are transferred to an from

memory by the associated 1553 interface unit using the
internal Address Register.

BC EOM Sequence.

Upon completion of a 1553 message (valid or invalid)

the 1553 interface unit issues an EOM pulse to the
CT2566 which takes the following actions:

1. Reads the Stack Pointer to get the address of the

current Descriptor Stack Entry.

NOT USED

BUS CHANNEL A/B

NOT USED

MASK BROADCAST BIT

NOT USED

MODE CODE

BROADCAST

RTU TO RTU

Note: When the BC expects the BROADCAST bit set in the status

word, a logic "1" will mask the status interrupt error flag. A
FORMAT error will be generated if the MASK BROADCAST bit
is not set.

ISSUE RESET COMMAND

INITIALIZE STACK POINTER

LOAD MESSAGE COUNTER

LOAD MESSAGES

ISSUE START COMMAND

SET CONFIGURATION

RESISTER TO BC MODE

INITIALIZE INTERRUPT

MASK REGISTER

LOAD EVERY FOURTH

LOCATION OF STACK WITH

STARTING ADDRESS

START

Figure 11

BC Initialization (under user control)

Figure 13 BC Control Word

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

CONTROLLER START

COMMAND RECEIVED

READS STACK POINTER

LOAD BLOCK STATUS WORD

INTO FIRST WORD OF

DESCRIPTOR STACK ENTRY

(SET SOM BIT IN BLOCK

STATUS WORD)

LOAD TIME TAG INTO

SECOND WORD OF

DESCRIPTOR

STACK ENTRY

ADDRESS FROM FOURTH WORD

OBTAIN DATA BLOCK

ISSUE BC START TO 1553 DEVICE

DETERMINE TYPE OF TRANSFER

READ CONTROL WORD TO

UPDATE BLOCK STATUS WORD

UPDATE TIME TAG

INCREMENT STACK
POINTER BY FOUR.

DECREMENT

MESSAGE COUNT

TRANSFERRED OK

DATA BLOCK

TRANSFERRED OK

STOP ON

ERROR SET

YES

MORE MESSAGES

TO SEND

YES

ISSUE BC EOM

STOP

Figure 14 BC Sequence of Operation (Under CT2566 Control)

TRANSFER DATA TO/FROM

1553 BUS (NOTE: RAM NOW

CONTROLLED BY INPUT PINS

CS AND OE

After controller start is issued the subsystem must wait until BCEOM is active

before issuing the next controller start.

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

2. Updates the Block Status Word by resetting the

SOM and setting EOM and any error bits.

3. Updates the Time Tag if used.
4. Increments the contents of the Stack Pointer by

four and increments the Message Counter by
one.

5. Initiates a message transfer beginning with new

Controller Start sequence if more messages are
to be transmitted.

6. Generates a BCEOM interrupt if enabled and no

further messages are to be transmitted.

Note that if an error is received and STOP ON

ERROR is set, the CT2566 completes the current
BCEOM sequence and then stops. The Stack Pointer
will point to the next message to be transmitted.

RTU Operation

The RTU mode is selected by setting bit 15 of the

Configuration Register to logic "1" and bit 14 to
logic "0".

RTU Initialization

For RTU operation, the user initializes the RAM as

shown in Table 4 and follows the steps shown in Figure
15, RTU Initialization Chart.

Look-Up Tables
The first 32 words of the Look-Up Table are initialized

with the addresses of the data blocks to be used when
received data from subaddress 0, 1, 2,...31. The next
32 table locations should be initialized with the address
of the data blocks to be used when the RTU is
instructed to transmit data from subaddress 0, 1,
2,...31. The data blocks may be any length sufficient to
contain the particular message as long as the data
block does not cross a 256 word boundary. Data blocks
may be shared by Look-Up Tables A and B, if desired
by the user (See Figure 16). The 1553 device can only
access the current Look-Up Table and the current
Descriptor Stack. The CPU selects the current area
through bit 13 of the Configuration Register.

Once in the RTU mode, the CT2566 will store the

command word in the fourth location of the current area
Descriptor Stack. The status of the message will be
recorded in the first location of the stack.

The data associated with the message will be

transferred to/from the data block indicated by the
Look-Up Table entry for that subaddress. If a system
Time Tag is provided by the user the CT2566 will
record the time of the SOM sequence in the second
word of the Stack entry.

When the CT2566 received an EOM pulse from the

1553 device, it resets the SOM bit in the Block Status
Word and sets the EOM bit and any error bits as
necessary. The Time Tag entry will be updated and an
EOM interrupt will be generated by the CPU, if enabled.

RTU SOM Sequence

Initiated when 1553 terminal puts a 1553 command

word on D00-D15 and pulses SOM low. The CT2566
saves the command received in an internal register.
Figure 17 illustrates the RTU Sequence of Operation
once a 1553 command word is received. Once the
command word is received, the CT2566 performs the
following steps:

1. Reads the Stack Pointer to get the address of the

current Descriptor Stack Entry.

2. Stores a SOM flag in the Block Status Word to

indicate a transfer operation is in progress.

3. Stores the Time Tag if used.

Table 4 Typical RTU memory map (4K memory)

HEX ADDRESS

FUNCTION

Fixed Areas

0100

Descriptor Stack Pointer A

0101

Reserved

0104

Descriptor Stack Pointer B

0105

Reserved

0108-013F

Spare

0140-017F

Look-Up Table A

01C0-01FF

Look-Up Table B

User Defined Areas

0180-019F

Data Block 1

01A0-01BF

Data Block 2

0200-021F

Data Block 3

0220-023F

Data Block 4

0240-025F

Data Block 5

0260-027F

Data Block 6

0EE0-0EFF

Data Block 107

0000-00FF

Descriptor Stack A

0F00-0FFF

Descriptor Stack B

8 7 6 5 4

0 0 0 0 0 0 0 0

CURRENT AREA B/A
(CONFIG. REG BIT 13)

TR (FROM COMMAND
WORD)

RTU SUBADDRESS BITS
(FROM COMMAND WORD)

RTU LOOK-UP TABLE ADDRESS

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

4. Stores the Command Word received.
5. Reads a Block address from the Look-Up Table

using the T/R bit and the subaddress from the
Command Word; transfers the Block address into
the address register. Data words are transferred
to/from memory by the associated 1553 interface
unit using the address register.

RTU EOM Sequence

At the end of a 1553 message (valid or invalid) the

CT2566 received an EOM pulse and then performs the
following:

1. Updates the Block Status Word.
2. Updates the Time Stage if used.
3. Increments the Stack Pointer by four.
4. Generates an Error Interrupt if enabled.

Figure 17 RTU Sequence of Operation

(under CT2566 control)

MESSAGE COMPLETE

GENERATE EOM INTERRUPT AND

CONDITION DETECTED

ERROR INTERRUPT IF ERROR

INCREMENT STACK POINTER

BY FOUR

UPDATE BLOCK STATUS WORD

AND TIME TAG

TRANSFER DATA TO/FROM

1553 INTERFACE DEVICE

READ LOOK-UP TABLE USING

AREA BIT B/A

T/R SUBADDRESS CURRENT

UPDATE DESCRIPTOR STACK

TAG AND COMMAND WORD

BLOCK STATUS WORD, TIME

READ STACK POINTER

1553 COMMAND WORD

RECEIVED

EXIT

YES

RECEIVED COMMAND WORD

LOOK-UP TABLE

RTU

ADDR T/R SUBADD

WORD

COUNT

XXXXX

00000

XXXXX

USER DEFINED 0140

LOCATIONS

USER DEFINED

XXXXX

00001

XXXXX

0141

USER DEFINED

XXXXX

00010

XXXXX

0142

XXXXX

11110

XXXXX

USER DEFINED 017E

USER DEFINED

XXXXX

11111

XXXXX

017F

}

Figure 16 RTU Look-up Table

START

ISSUE RESET COMMAND

INITIALIZE STACK POINTER

SET UP DATA BLOCKS

WAIT FOR 1553 COMMAND

SET UP LOOK-UP TABLE(S)

DATA BLOCK ASSIGNMENTS

Figure 15

RTU Initialization (under user control)

INITIALIZE INTERRUPT

MASK REGISTER

SET CONFIGURATION

REGISTER TO RTU MODE

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

MT Operation

The MT mode is selected by setting bit 15 of the

Configuration Register to logic "0" and bit 14 to a
logic "1" along with issuing a Controller Start
Command.

MT Initialization

For MT operations, the entire RAM is used as the MT

Stack (See Table 5) and the setups shown in Figure 18
are followed. The user instructs the CT2566 where to
store the first received 1553 word by loading the
starting word address in the Stack Pointer. Once a
Controller Start command is issued, the CT2566 will
store this value in the internal Address Register.

The identification Word provides the CPU with

additional information regarding the received 1553
word, its format is shown in Figure 19. This information
allows the user to develop algorithms to restructure the
message transfers. External Logic can be used for
triggering on specific commands or subaddresses. For
further information, consult factory.

The 1553 device will generate an Identification Word

for every word that is transferred across the 1553 Data
Bus. The CT2566 stores the received 1553 word in the
RAM location indicated by the internal Address
Register. The contents of this register are incremented
by one so that it points to the next word in RAM, and
the Identification Word is stored at that location. The
internal Address Register is then incremented by one
again, in preparation for storing the next Identification

Word. The RAM automatically wraps around (from
location FFFF to location 0000), shown in Figure 20.

Bit 7 of the Identification Word can be reset by the

CPU each time it reads the associated data word into
CPU memory. This provides a simple method of
keeping track of words that have been processed by
the CPU.

START

ISSUE RESET COMMAND

CLEAR RAM

INITIALIZE STACK POINTER

SET CONFIGURATION REGISTER

TO MT MODE

ISSUE START COMMAND

Figure 18 MT Initialize

(under user control)

8 7

1 1 1

GAP TIME

SET TO "1"

ERROR (1 = ERROR, 0 = GOOD STATUS)

COMMAND SYNC

1553 CHANNEL A/B

WORD GAP

SET TO "0"

Note: Each bit of the GAP TIME field
represents .5µs.

Figure 19 MT Identification Word

GET STACK POINTER FROM

WORD 100 IN RAM AND

STORE IN INTERNAL REGISTER

START COMMAND ISSUED

STORE RETREIVED 1553 WORD

IN RAM, INCREMENTS INTERNAL

ADDRESS REGISTER

Figure 20 MT Sequence of Operation

(under CT2566 control)

STORE IDENTIFICATION WORD

IN RAM, INCREMENT INTERNAL

ADDRESS REGISTER

WORD TRANSFERRED

ACROSS 1553 BUS

YES

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

CT2566 Timing Clock in at 12 MHz

Figures 21 through 37 illustrate the timing for the CT2566 and its operation. All timing definitions are listed in the

tables below and the appropriate definitions are repeated with each diagram.

Table 5 Typical MT memory map (4K memory)

HEX ADDRESS

FUNCTION

0000

First Received 1553 Word

MODE CODES

All mode codes applicable to dual redundant

systems are recognized by the CT2566. Mode
codes can be illegalized by the 1553 BC or
RTU device. Refer to the CT2565 or CT2512
data sheets for more information.

0001

First Identification Word

0002

Second Received 1553 Word

0003

Second Identification Word

0004

0005

0006

0007

0008

0100

Stack Pointer A (Fixed location)*

0104

Stack Pointer B

FFFF

Word stored at FFFF will be followed by
the word stored at 0000.

* The Stack Pointer is loaded into an internal Address
Register upon receipt of a Controller Start command. This
location is overwritten by data once monitor operation
begins.

Delay Timing

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

td3

CPU MEMWR low delay

120

td4

CPU MEMOE low delay

115

td5

EXTLD low delay

130

td6

RESET low delay

td7

Internal Register delay (read)

td8

Internal Register delay (write)

td9

td10

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

td11

BC SOM Cycle DMA delay

120

td12

INT low delay

td13

RTU SOM Cycle DMA delay

200

td14

1553 Command Word set-up time

td15

1553 Command Word hold time

td16

MT SOM Cycle DMA delay

120

td17

CS low to MEMCS low delay

td18

OE low to MEMOE low delay

td19

WR low to MEMWR low delay

td20

BUSGRNT high delay

td21

BUSACK low Address delay

td22

BUSACK high Address delay

td23

Address increment delay

200

Pulse Width Timing

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

tpw1

READYD pulse width (CPU Handshake)

tpw2

CPU MEMWR low pulse width

tpw3

CPU MEMCS low pulse width

tpw4

EXTLD low pulse width

tpw5

RESET low pulse width

tpw6

DMA MEMWR low pulse width

tpw7

DMA MEMCS low pulse width

tpw8

BCSTART low pulse width

tpw9

EOM low pulse width

200

tpw10

INT low pulse width

tpw9

tpw11

INT low (BCEOM) pulse width

tpw12

SOM low pulse width

200

tpw13

NBGRNT low pulse width

200

tpw14

ADRINC low pulse width

200

tpw15

MSTRCLR low pulse width

150

*The min value of tpw10 equals tpw9 minus 30 ns.

Delay Timing (Cont.)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

A02 (38)

A01 (77)

A00 (39)

SSFLAG, SSBUSY, SVCRQST

DBAC, RTU/BC, MT, CTLIN B/A

MEM/REG (10)

D15-D00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

DATA VALID

td1

tpw1

td2

td7

Figure 21 CPU reads from internal register

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Reads from Internal Register

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

td7

Internal Register delay (read)

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

A02 (38)

A01 (77)

A00 (39)

SSFLAG, SSBUSY, SVCRQST

DBAC, RTU/BC, MT, CTLIN B/A

MEM/REG (10)

D15-D00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

td2

td9

tpw1

td8

td10

DATA LATCHED

Configuration Register Only

DATA VALID

Figure 22 CPU writes to internal register

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Writes to Internal Register

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

td8

Internal Register delay (write)

td9

td10

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

A02 (38)

A01 (77)

A00 (39)

MEM/REG (10)

D15-D00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

td9

tpw1

DATA FROM EXTERNAL REGISTER

EXTEN (4)

td2

Figure 23 CPU reads from external register

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Reads from External Register Timing

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

td9

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

A02 (38)

A01 (77)

A00 (39)

MEM/REG (10)

D15-D00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

td9

tpw1

CPU DATA

EXTLD (43)

td10

VALID

tpw4

td5

td2

Figure 24 CPU writes to external register

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Writes to External Register

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

td5

EXTLD low delay

130

td9

td10

tpw4

EXTLD low pulse width

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

MEMOE (56)

MEM/REG (10)

A15-A00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

tpw1

D15-D00

td2

RAM ADDRESS VALID

td4

RAM DATA VALID

MEMCS (16)

Figure 25 CPU reads from RAM

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Reads from Ram

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

td9

CPU MEMOE low delay

115

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

MEMWR (57)

MEM/REG (10)

A15-A00

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

tpw1

D15-D00

td2

RAM ADDRESS VALID

td3

RAM DATA VALID

MEMCS (16)

tpw2

tpw3

Figure 26 CPU writes to RAM

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Writes To Ram

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

td3

CPU MEMWR low delay

120

tpw2

CPU MEMWR low pulse width

tpw3

CPU MEMCS low pulse width

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

td2

BUSGRNT (14)

td22

td20

A15-A00

BUSACK (53)

BUSREQ (13)

CS (55)

MEMCS (16)

OE (17)

MEMOE (56)

WR (54)

MEMWR (57)

td18

td19

td17

Figure 27 MIL-STD-1553 to CT2566 Handshaking

Figure 28 MIL-STD-1553 terminal I/O delay

MIL-STD-1553 TO CT2566 Handshaking

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td20

BUSGRNT high delay

td21

BUSACK low Address delay

td22

BUSACK high Address delay

MIL-STD-1553 Terminal to Delay

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td17

CS low to MEMCS low delay

td18

OE low to MEMOE low delay

td19

WR low to MEMWR low delay

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

td23

A15-A00

BUSACK (53)

ADRINC (9)

ADDRESS

ADDRESS + 1

td14

MSTRCLR (52)

RESET (47)

tpw15

td6

See Note

Figure 29 CT2566 Unit Address Increment

Figure 30 CT2566 direct reset

CT2566 Direct Increment

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td6

RESET low delay

tpw15

MSTRCLR low pulse width

150

CT2566 Address Increment

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

tpw14

ADRINC low pulse width

200

td23

Address increment delay

200

NOTE: The RESET (low) pulse width will be approximately equal to that of MSTRCLR (low).

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

A02 (38)

A01 (77)

IOEN (42)

SELECT (1)

STRBD (41)

(Internal)

12MHz Clock

RD/WR (2)

READYD (3)

See Note

td1

tpw1

td2

RESET (47)

D00 (67)

A00 (39)

MEM/REG 10)

tpw5

Figure 31 Programmed CT2566 reset

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

Programmed CT2566 Reset

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

200

td2

IOEN high delay (CPU Handshake)

tpw1

READYD pulse width (CPU Handshake)

tpw5

RESET low pulse width

r
o

f
l
e

i
r
c

i
t

T

l
o

/
1

/
9

l
a

i
n

i
e

(
5

)

6

-
6

A15-A00

td10

td11

td9

STACK ADDRESS

STACK ADDRESS + 1

D15-D00

BCSTART (46)

TAGEN (5)

MEMOE (56)

MEMWR (57)

MEMCS (16)

READYD (3)

IOEN (42)

SELECT (1)

A00 (39)

A01 (77)

A02 (38)

RD/WR (2)

MEM/REG (10)

D01 (28)

STRBD (41)

(Internal)

12 MHz Clock

BLOCK STATUS WORD

TIME TAG

TRI-STATE

STACK ADDRESS + 2

STACK POINTER

STACK ADDRESS

BLOCK ADDRESS

STACK ADDRESS + 3

tpw8

Figure 32 BC SOM timing (no contention)

BC SOM Timing (No Contention)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td9

td10

td11

BC SOM Cycle DMA delay

120

tpw8

BCSTART low pulse width

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

Figure 33 BC EOM timing (no contention)

(Internal)

12 MHz Clock

A15-A00

STACK ADDRESS + 2

STACK ADDRESS + 3

STACK ADDRESS + 1

STACK ADDRESS

STACK POINTER

TRI-STATE

TIME TAG

BLOCK STATUS WORD

STACK ADDRESS

td12

tpw10

D15-D00

INT (45)

TAGEN (5)

MEMOE (56)

MEMWR (57)

MEMCS (16)

EOM (6)

tpw9

EOM/Error

Figure 33 BC EOM timing (no contention) con't

TRI-STATE

STACK ADDRESS + 4

tpw11

MESSAGE COUNT

STACK POINTER

STACK POINTER + 1

STACK POINTER + 2

STACK POINTER + 1

MESSAGE COUNT + 1

EOM

BC EOM Timing (No Contention)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td9

INT low delay

tpw9

INT low pulse width

200

tpw10

INT low pulse width

tpw9

tpw11

INT low delay

* The min value of tpw10 equals tpw9 minus 30ns.

r
o

f
l
e

i
r
c

i
t

T

l
o

/
1

/
9

l
a

i
n

i
e

(
5

)

6

-
6

BCSTART (46)

TAGEN (5)

MEMOE (56)

MEMWR (57)

MEMCS (16)

SOM (7)

td13

A15-A00

STACK POINTER

D15-D00

STACK ADDRESS + 1

STACK ADDRESS + 3

STACK ADDRESS + 2

STACK ADDRESS

LOOK-UP ADDRESS

STACK ADDRESS

BLOCK STATUS WORD

TIME TAG

TRI-STATE

COMMAND

BLOCK ADDRESS

1553 COMMAND

WORD

tpw8

tpw12

tpw13

td15

td14

NBGRNT (19)

Figure 34 RTU SOM (no contention)

RTU SOM Timing (No Contention)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td13

RTU SOM Cycle DMA delay

200

td14

1553 Command Word set-up time

td15

1553 Command Word hold time

tpw8

BCSTART low pulse width

tpw12

SOM low pulse width

200

tpw13

NBGRNT low pulse width

200

r
o

f
l
e

i
r
c

i
t

T

l
o

/
1

/
9

l
a

i
n

i
e

(
5

)

6

-
6

Figure 35 RTU EOM timing (no contention)

(Internal)

12 MHz Clock

tpw10

INT (45)

TAGEN (5)

MEMOE (56)

MEMWR (57)

MEMCS (16)

EOM (6)

tpw9

A15-A00

STACK ADDRESS + 2

STACK ADDRESS + 3

STACK ADDRESS + 1

STACK ADDRESS

STACK POINTER

TRI-STATE

TIME TAG

BLOCK STATUS WORD

STACK ADDRESS

D15-D00

STACK ADDRESS + 4

STACK POINTER

RTU EOM Timing (No Contention)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

tpw9

RESET low delay

200

tpw10

MSTRCLR low pulse width

tpw9

* The min value of tpw10 equals tpw9 minus 30ns.

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

Figure 37 DMA Read/Write timing (SOM/EOM cycles)

DMA Read/Write Timing (SOM/EOM Cycles)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

tas1

DMA Address set-up time

tah1

DMA Address hold time

tds1

DMA Address set-up time

tdh1

DMA Address hold time

tas2

DMA Address set-up time

tah2

DMA Address hold time

tds2

DMA Address set-up time

tdh2

DMA Address hold time

tpw6

DMA MEMWR low pulse width

tpw7

DMA MEMCS low pulse width

DMA READ

DMA WRITE

tdh2

A15-A00

tds2

tas2

12 MHz Clock

MEMWR (57)

MEMOE (56)

MEMCS (16)

(Internal)

D15-D00

tah2

tas1

tpw7

tpw6

tah1

tdh1

tds1

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

21
60
22
61
23
62
24
63
25
64
26
65
27
66
28
67
29
68
30
69
31
70
32
71
33
72
34
73
35
74
36
75
37
76
38
77
39
78
40

49
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
20

SELECT

STRBD
RD/WR
IOEN
READYD
EXTLD
EXTEN
CHB/CHA
TAGEN
INT
EOM
BCSTART
SOM
RESET
STATERR
MSGERR
ADRINC
CTLIN B/A
MEM/REG
CTLOUT B/A
CLOCK IN
TIMEOUT
LOOPERR
MSTRCLR
BUSREQ
BUSACK
BUSGRNT
WR
N/C
CS
MEMCS
MEMOE
OE
MEMWR

N/C

N/C
NBGRNT
MT
+5 Volt

D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00

SSFLAG

SVCREQ

SSBUSY

DBAC

RTU/BC

A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00

GND
GND

CT2566

MIL-STD-1553

to µPROCESSOR
INTERFACE UNIT

DDIP Pin Connection Diagram, CT2566 and Pinout

Table 6 CT2566 Pin Out Description

(DDIP)

Pin

Function

Pin

Function

SELECT

GND

RD/WR

STRBD

READYD

IOEN

EXTEN

EXTLD

TAGEN

CHB/CHA

EOM

INT

SOM

BCSTART

STATERR

RESET

ADRINC

MSGERR

MEM/REG

CTLIN B/A

CLOCK IN

CTLOUT B/A

LOOPERR

TIMEOUT

BUSREQ

MSTRCLR

BUSGRNT

BUSACK

N/C

MEMCS

MEMOE

N/C

MEMWR

NBGRNT

N/C

+ 5 Volt

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

SSFLAG

SVCREQ

SSBUSY

DBAC

RTU/BC

A15

A14

A13

A12

A11

A10

A09

A08

A07

A06

A05

A04

A03

A02

A01

A00

GND

Aeroflex Circuit Technology

SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700

3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

SELECT
STRBD
RD/WR
IOENBL
READYD
EXTLD
EXTEN
CHB/CHA
TAGEN
INT
EOM
BCSTART
SOM
RESET
STATERR
MSGERR
ADRINC
CTLIN B/A
MEM/REG
CTLOUT B/A
CLOCK IN
TIMEOUT
LOOPERR
MSTRCLR
BUSYREQ
BUSACK
BUSGRNT
WR
N/C
CS
MEMCS
MEMOE
OE
MEMWR
N/C
N/C
NBGRNT
MT
+5V

D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00

SSFLAG

SVCREQ

SSBUSY

DBAC

RTU/BC

A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01

A00 (LSB)

CASE GND

GROUND

Table 7 CT2566 Pin Out Description

(FP)

Pin

Function

Pin

Function

N/C

SELECT

GROUND

STRBD

CASE GND

RD/WR

A00 (LSB)

IOENBL

A01

READYD

A02

EXTLD

A03

EXTEN

A04

CHB/CHA

A05

TAGEN

A06

INT

A07

EOM

A08

BCSTART

A09

SOM

A10

RESET

A11

STATERR

A12

MSGERR

A13

ADRINC

A14

CTLIN B/A

A15

MEM/REG

RTU/BC

CTLOUT B/A

DBAC

CLOCK IN

SSBUSY

TIMEOUT

SVCREQ

LOOPERR

SSFLAG

MSTRCLR

D00

BUSYREQ

D01

BUSACK

D02

BUSGRNT

D03

D04

N/C

D05

D06

MEMCS

D07

MEMOE

D08

D09

MEMWR

D10

N/C

D11

N/C

D12

NBGRNT

D13

D14

+5V

D15

N/C

CT2566FP

MIL-STD-1553

to µPROCESSOR
INTERFACE UNIT

Flat Package Pin Connection Diagram, CT2566 and Pinout

1
2

N/C

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42

82
81

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CT2566

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CT2566