Document Outline
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-
- GENERAL DESCRIPTION
-
-
-
-
-
- ELECTRICAL CHARACTERISTICS3 V OPERATION
- ELECTRICAL CHARACTERISTICSMIXED 5 V/3 V OR 3 V/5 V OPERATION
- PACKAGE CHARACTERISTICS
-
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- DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
- RECOMMENDED OPERATING CONDITIONS
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-
-
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Dual-Channel, Digital Isolators,
Enhanced System-Level ESD Reliability
ADuM3200/ADuM3201
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x
Narrow body, 8-lead SOIC, Pb-free package
Low power operation
5 V operation
1.6 mA per channel maximum @ 0 Mbps to 2 Mbps
3.7 mA per channel maximum @ 10 Mbps
7.5 mA per channel maximum @ 25 Mbps
3 V operation
1.4 mA per channel maximum @ 0 Mbps to 2 Mbps
2.4 mA per channel maximum @ 10 Mbps
4.6 mA per channel maximum @ 25 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105C
High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics
3 ns maximum pulse-width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/s
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000
V
IORM
= 560 V peak
APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation
GENERAL DESCRIPTION
The ADuM320x
1
are dual-channel, digital isolators based on
Analog Devices' iCoupler technology. Combining high speed
CMOS and monolithic transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM320x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. The
ADuM320x isolators have a patented refresh feature that ensures
dc correctness in the absence of input logic transitions and
during power-up/power-down conditions.
In comparison to the ADuM120x isolators, the ADuM320x
isolators contain various circuit and layout changes to provide
increased capability relative to system-level IEC 61000-4-x
testing (ESD, burst, surge). The precise capability in these tests
for either the ADuM120x or ADuM320x products is strongly
determined by the design and layout of the user's board or
module. For more information, see
Application Note AN-793,
ESD/Latch-Up Considerations with iCoupler Isolation Products
.
1
Protected by U.S. Patents 5,952,849; 6,873,065; and other pending patents.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE
DECODE
ENCODE
DECODE
V
DD1
V
IA
V
IB
GND
1
V
DD2
V
OA
V
OB
GND
2
1
2
3
4
8
7
6
5
0
5927
-
001
Figure 1. ADuM3200 Functional Block Diagram
ENCODE
DECODE
DECODE
ENCODE
V
DD1
V
OA
V
IB
GND
1
V
DD2
V
IA
V
OB
GND
2
1
2
3
4
8
7
6
5
0
5927
-
002
Figure 2. ADuM3201 Functional Block Diagram
ADuM3200/ADuM3201
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics--5 V Operation................................ 3
Electrical Characteristics--3 V Operation................................ 5
Electrical Characteristics--Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 14
Application Information................................................................ 15
PC Board Layout ........................................................................ 15
System-Level ESD Considerations and Enhancements ........ 15
Propagation Delay-Related Parameters................................... 15
DC Correctness and Magnetic Field Immunity........................... 15
Power Consumption .................................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
7/06--Revision 0: Initial Version
ADuM3200/ADuM3201
Rev. 0 | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V OPERATION
All voltages are relative to their respective ground. 4.5 V V
DD1
5.5 V, 4.5 V V
DD2
5.5 V. All minimum/maximum specifications
apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T
A
= 25C, V
DD1
= V
DD2
= 5 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
I
DDI (Q)
0.4
0.8
mA
Output Supply Current, per Channel, Quiescent
I
DDO (Q)
0.5
0.6
mA
ADuM3200, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
1.3
1.7
mA
DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
1.0
1.6
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current
I
DD1 (10)
3.5
4.6
mA
5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
1.7
2.8
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current
I
DD1 (25)
7.7
10.0
mA
12.5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (25)
3.1
3.9
mA
12.5 MHz logic signal freq.
ADuM3201, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
1.1
1.5
mA
DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
1.3
1.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current
I
DD1 (10)
2.6
3.4
mA
5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
3.1
4.0
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current
I
DD1 (25)
5.3
6.8
mA
12.5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (25)
6.4
8.3
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
I
IA
, I
IB
-10
+0.01
+10
A
0 V
IA
, V
IB
V
DD1
or V
DD2
Logic High Input Threshold
V
IH
0.7 V
DD1
,
V
DD2
V
Logic Low Input Threshold
V
IL
0.3 V
DD1,
V
DD2
V
Logic High Output Voltages
V
OAH
V
DD1
,
V
DD2
- 0.1
5.0
V
I
Ox
= -20 A, V
Ix
= V
IxH
V
OBH
V
DD1
,
V
DD2
- 0.5
4.8
V
I
Ox
= -4 mA, V
Ix
= V
IxH
Logic Low Output Voltages
V
OAL
0.0
0.1
V
I
Ox
= 20 A, V
Ix
= V
IxL
V
OBL
0.04
0.1
V
I
Ox
= 400 A, V
Ix
= V
IxL
0.2
0.4
V
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM320xAR
Minimum Pulse Width
2
PW
1000
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
150
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
4
PWD
40 ns
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
100
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD/OD
50
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
10
ns
C
L
= 15 pF, CMOS signal levels
ADuM3200/ADuM3201
Rev. 0 | Page 4 of 20
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM320xBR
Minimum Pulse Width
2
PW
100 ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
50
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
2.5
ns
C
L
= 15 pF, CMOS signal levels
ADuM320xCR
Minimum Pulse Width
2
PW
20
40
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 50
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
45
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
2.5
ns
C
L
= 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25
35
kV/s V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25
35
kV/s V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate
f
r
1.2
Mbps
Input Dynamic Supply Current, per Channel
8
I
DDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current, per Channel
8
I
DDO (D)
0.05
mA/Mbps
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total I
DD1
and I
DD2
supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
ADuM3200/ADuM3201
Rev. 0 | Page 5 of 20
ELECTRICAL CHARACTERISTICS--3 V OPERATION
All voltages are relative to their respective ground. 2.7 V V
DD1
3.6 V, 2.7 V V
DD2
3.6 V. All minimum/maximum specifications
apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T
A
= 25C,
V
DD1
= V
DD2
= 3.0 V.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
I
DDI (Q)
0.3
0.5
mA
Output Supply Current, per Channel, Quiescent
I
DDO (Q)
0.3
0.5
mA
ADuM3200, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
0.8
1.3
mA
DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current
I
DD1 (10)
2.0
3.2
mA
5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
1.1
1.7
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current
I
DD1 (25)
4.3
6.4
mA
12.5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (25)
1.8
2.4
mA
12.5 MHz logic signal freq.
ADuM3201, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
0.7
1.3
mA
DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
0.8
1.6
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current
I
DD1 (10)
1.5
2.1
mA
5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
1.9
2.4
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current
I
DD1 (25)
3.0
4.2
mA
12.5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (25)
3.6
5.1
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
I
IA
, I
IB
-10
+0.01
+10
A
0 V
IA
, V
IB
, V
DD1
or V
DD2
Logic High Input Threshold
V
IH
0.7 V
DD1,
V
DD2
V
Logic Low Input Threshold
V
IL
0.3 V
DD1
,
V
DD2
V
Logic High Output Voltages
V
OAH
V
DD1
,
V
DD2
- 0.1
3.0
V
I
Ox
= -20 A, V
Ix
= V
IxH
V
OBH
V
DD1
,
V
DD2
- 0.5
2.8
V
I
Ox
= -4 mA, V
Ix
= V
IxH
Logic Low Output Voltages
V
OAL
0.0
0.1
V
I
Ox
= 20 A, V
Ix
= V
IxL
V
OBL
0.04
0.1
V
I
Ox
= 400 A, V
Ix
= V
IxL
0.2
0.4
V
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM320xAR
Minimum Pulse Width
2
PW
1000
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
150
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
4
PWD
40
ns
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
100
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD/OD
50
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
10
ns
C
L
= 15 pF, CMOS signal levels
ADuM3200/ADuM3201
Rev. 0 | Page 6 of 20
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM320xBR
Minimum Pulse Width
2
PW
100
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
60
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
-t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
22
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
3.0
ns
C
L
= 15 pF, CMOS signal levels
ADuM320xCR
Minimum Pulse Width
2
PW
20
40
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25
50
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
55
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
16
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
16
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
3.0
ns
C
L
= 15 pF, CMOS signal levels
For All Models
Common Mode Transient Immunity
at Logic High Output
7
|CM
H
|
25
35
kV/s
V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common Mode Transient Immunity
at Logic Low Output
7
|CM
L
|
25
35
kV/s
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate
f
r
1.1
Mbps
Input Dynamic Supply Current, per Channel
8
I
DDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current, per Channel
8
I
DDO (D)
0.03
mA/Mbps
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total I
DD1
and I
DD2
supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
ADuM3200/ADuM3201
Rev. 0 | Page 7 of 20
ELECTRICAL CHARACTERISTICS--MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V V
DD1
5.5 V, 2.7 V V
DD2
3.6 V. 3 V/5 V operation:
2.7 V V
DD1
3.6 V, 4.5 V V
DD2
5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at T
A
= 25C; V
DD1
= 3.0 V, V
DD2
= 5.0 V; or V
DD1
= 5.0 V, V
DD2
= 3.0 V.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
I
DDI (Q)
5 V/3 V Operation
0.4
0.8
mA
3 V/5 V Operation
0.3
0.5
mA
Output Supply Current, per Channel, Quiescent
I
DDO (Q)
5 V/3 V Operation
0.3
0.5
mA
3 V/5 V Operation
0.5
0.6
mA
ADuM3200, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
5 V/3 V Operation
1.3
1.7
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.8
1.3
mA
DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
5 V/3 V Operation
0.7
1.0
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.0
1.6
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current
I
DD1 (10)
5 V/3 V Operation
3.5
4.6
mA
5 MHz logic signal freq.
3 V/5 V Operation
2.0
3.2
mA
5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
5 V/3 V Operation
1.1
1.7
mA
5 MHz logic signal freq.
3 V/5 V Operation
1.7
2.8
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current
I
DD1 (25)
5 V/3 V Operation
7.7
10.0
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
4.3
6.4
mA
12.5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (25)
5 V/3 V Operation
1.8
2.4
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
3.1
3.9
mA
12.5 MHz logic signal freq.
ADuM3201, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
5 V/3 V Operation
1.1
1.5
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.3
mA
DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
5 V/3 V Operation
0.8
1.6
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.3
1.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current
I
DD1 (10)
5 V/3 V Operation
2.6
3.4
mA
5 MHz logic signal freq.
3 V/5 V Operation
1.5
2.1
mA
5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
5 V/3 V Operation
1.9
2.4
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.1
4.0
mA
5 MHz logic signal freq.
ADuM3200/ADuM3201
Rev. 0 | Page 8 of 20
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
25 Mbps (CR Grade Only)
V
DD1
Supply Current
I
DD1 (25)
5 V/3 V Operation
5.3
6.8
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
3.0
4.2
mA
12.5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (25)
5 V/3 V Operation
3.6
5.1
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
6.4
8.3
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
I
IA
, I
IB
-10
+0.01
+10
A
0 V
IA
, V
IB
V
DD1
or V
DD2
Logic High Input Threshold
V
IH
0.7 V
DD1
,
V
DD2
V
Logic Low Input Threshold
V
IL
0.3 V
DD1
,
V
DD2
V
5 V/3 V Operation
0.8
V
3 V/5 V Operation
0.4
V
Logic High Output Voltages
V
OAH
, V
OBH
V
DD1
,
V
DD2
- 0.1
V
DD1
,
V
DD2
V I
Ox
= -20 A, V
Ix
= V
IxH
V
DD1
,
V
DD2
- 0.5
V
DD1
,
V
DD2
- 0.2
V I
Ox
= -4 mA, V
Ix
= V
IxH
Logic Low Output Voltages
V
OAL
, V
OBL
0.0
0.1
V
I
Ox
= 20 A, V
Ix
= V
IxL
0.04
0.1
V
I
Ox
= 400 A, V
Ix
= V
IxL
0.2
0.4
V
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM320xAR
Minimum Pulse Width
2
PW
1000
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
15
150
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
4
PWD
40
ns
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
50
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD/OD
50
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
10
ns
C
L
= 15 pF, CMOS signal levels
ADuM320xBR
Minimum Pulse Width
2
PW
100
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
15
55
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
- t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
22
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
f
5 V/3 V Operation
3.0
ns
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation
2.5
ns
C
L
= 15 pF, CMOS signal levels
ADuM3200/ADuM3201
Rev. 0 | Page 9 of 20
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM320xCR
Minimum Pulse Width
2
PW
20
40
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25
50
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20
50
ns
C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t
R
/t
f
5 V/3 V Operation
3.0
ns
C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation
2.5
ns
C
L
= 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
|
25
35
kV/s
V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
|
25
35
kV/s
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate
f
r
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current,
per Channel
8
I
DDI (D)
5 V/3 V Operation
0.19
mA/Mbps
3 V/5 V Operation
0.10
mA/Mbps
Output Dynamic Supply Current,
per Channel
8
I
DDO (D)
5 V/3 V Operation
0.03
mA/Mbps
3 V/5 V Operation
0.05
mA/Mbps
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total I
DD1
and I
DD2
supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
ADuM3200/ADuM3201
Rev. 0 | Page 10 of 20
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input to Output)
1
R
I-O
10
12
Capacitance (Input to Output)
1
C
I-O
1.0
pF
f = 1 MHz
Input Capacitance
C
I
4.0
pF
IC Junction-to-Case Thermal Resistance, Side 1
JCI
46
C/W
Thermocouple located at center
of package underside
IC Junction-to-Case Thermal Resistance, Side 2
JCO
41
C/W
1
The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM3200/ADuM3201 is approved by the following organizations.
Table 5.
UL CSA
VDE
Recognized under 1577 Component
Recognition Program
1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2):
2003-01
2
2500 V rms isolation voltage
Basic insulation, 560 V peak
File E214100
File 205078
File 2471900-4880-0001
1
In accordance with UL1577, each ADuM320x is proof-tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 5 A).
2
In accordance with DIN EN 60747-5-2, each ADuM320x is proof-tested by applying an insulation test voltage 1050 V peak for 1 second (partial discharge detection
limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration
Minimum External Air Gap (Clearance)
L(I01)
4.90 min
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
4.01 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance)
0.017 min
mm
Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM3200/ADuM3201
Rev. 0 | Page 11 of 20
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description
Symbol
Characteristic
Unit
Installation Classification Per DIN VDE 0110
For Rated Mains Voltage 150 V rms
I-IV
For Rated Mains Voltage 300 V rms
I-III
For Rated Mains Voltage 400 V rms
I-II
Climatic Classification
40/105/21
Pollution Degree (DIN VDE 0110, Table 1)
2
Maximum Working Insulation Voltage
V
IORM
560
V peak
Input-to-Output Test Voltage, Method b1
V
PR
1050
V peak
V
IORM
1.875 = V
PR
, 100% Production Test, t
m
= 1 sec, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method a
V
PR
After Environmental Tests Subgroup 1
V
IORM
1.6 = V
PR
, t
m
= 60 sec, Partial Discharge < 5 pC
896
V peak
After Input and/or Safety Test Subgroup 2/3
V
IORM
1.2 = V
PR
, t
m
= 60 sec, Partial Discharge < 5 pC
672
V peak
Highest Allowable Overvoltage (Transient Overvoltage, t
TR
= 10 sec)
V
TR
4000
V peak
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; also See Figure 3)
Case Temperature
T
S
150
C
Side 1 Current
I
S1
160
mA
Side 2 Current
I
S2
170
mA
Insulation Resistance at T
S
, V
IO
= 500 V
R
S
>10
9
Note that the "*" marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
CASE TEMPERATURE (C)
S
A
FE
TY
-
L
IM
IT
IN
G
C
U
R
R
E
N
T
(
m
A
)
0
0
200
180
100
80
60
40
20
50
100
150
200
SIDE #1
SIDE #2
120
140
160
05
92
7-
00
3
Figure 3. Thermal Derating Curve, Dependence of Safety-
Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-40
+105
C
Supply Voltages
1
V
DD1
, V
DD2
2.7
5.5
V
Input Signal Rise and Fall Times
1.0
ms
1
All voltages are relative to their respective ground. See the DC Correctness and
Magnetic Field Immunity section for information on immunity to external
magnetic fields.
ADuM3200/ADuM3201
Rev. 0 | Page 12 of 20
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25C, unless otherwise noted.
Table 9.
Parameter
Symbol
Min
Max
Unit
Storage Temperature
T
ST
-55
+150
C
Ambient Operating Temperature
T
A
-40
+105
C
Supply Voltages
1
V
DD1
, V
DD2
-0.5
+7.0
V
Input Voltage
1, 2
V
IA
, V
IB
-0.5
V
DDI
+ 0.5
V
Output Voltage
1, 2
V
OA
, V
OB
-0.5
V
DDO
+ 0.5
V
Average Output Current, per Pin
3
I
O
-35
+35
mA
Common-Mode Transients
4
CM
H
, CM
L
-100 +100
kV/s
1
All voltages are relative to their respective ground.
2
V
DDI
and V
DDO
refer to the supply voltages on the input and output sides of a given channel, respectively.
3
See Figure 3 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating can cause latch-up or
permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 10. ADuM3200 Truth Table (Positive Logic)
V
IA
Input
V
IB
Input
V
DD1
State
V
DD2
State
V
OA
Output
V
OB
Output
Notes
H
H
Powered
Powered
H
H
L
L
Powered
Powered
L
L
H
L
Powered
Powered
H
L
L
H
Powered
Powered
L
H
X
X
Unpowered
Powered
H
H
Outputs return to the input state within
1 s of V
DDI
power restoration.
X
X
Powered
Unpowered
Indeterminate
Indeterminate
Outputs return to the input state within
1 s of V
DDO
power restoration.
Table 11. ADuM3201 Truth Table (Positive Logic)
V
IA
Input V
IB
Input V
DD1
State
V
DD2
State
V
OA
Output
V
OB
Output
Notes
H
H
Powered
Powered
H
H
L
L
Powered
Powered
L
L
H
L
Powered
Powered
H
L
L
H
Powered
Powered
L
H
X
X
Unpowered
Powered
Indeterminate
H
Outputs return to the input state within
1 s of V
DDI
power restoration.
X
X
Powered
Unpowered
H
Indeterminate
Outputs return to the input state within
1 s of V
DDO
power restoration.
ADuM3200/ADuM3201
Rev. 0 | Page 13 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
05
92
7-
00
4
V
DD1
1
V
IA 2
V
IB 3
GND
1
4
V
DD2
8
V
OA
7
V
OB
6
GND
2
5
ADuM3200
TOP VIEW
(Not to Scale)
Figure 4. ADuM3200 Pin Configuration
Table 12. ADuM3200 Pin Function Descriptions
Pin
No. Mnemonic
Function
1
V
DD1
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2
V
IA
Logic Input A.
3
V
IB
Logic Input B.
4
GND
1
Ground 1. Ground reference for Isolator Side 1.
5
GND
2
Ground 2. Ground reference for Isolator Side 2.
6
V
OB
Logic Output B.
7
V
OA
Logic Output A.
8
V
DD2
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
05
92
7-
00
5
V
DD1
1
V
OA 2
V
IB 3
GND
1
4
V
DD2
8
V
IA
7
V
OB
6
GND
2
5
ADuM3201
TOP VIEW
(Not to Scale)
Figure 5. ADuM3201 Pin Configuration
Table 13. ADuM3201 Pin Function Descriptions
Pin
No. Mnemonic Function
1
V
DD1
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2
V
OA
Logic Output A.
3
V
IB
Logic Input B.
4
GND
1
Ground 1. Ground reference for Isolator Side 1.
5
GND
2
Ground 2. Ground reference for Isolator Side 2.
6
V
OB
Logic Output B.
7
V
IA
Logic Input A.
8
V
DD2
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
ADuM3200/ADuM3201
Rev. 0 | Page 14 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RATE (Mbps)
C
URRE
N
T
/
CHA
NNE
L
(
m
A)
0
0
6
2
8
10
10
20
30
5V
3V
4
0
59
27
-
00
6
Figure 6. Typical Input Supply Current per Channel vs.
Data Rate for 5 V and 3 V Operation
DATA RATE (Mbps)
C
URRE
N
T
/
CHA
NNE
L
(
m
A)
0
0
3
2
1
4
10
20
30
5V
3V
0
59
27
-
00
7
Figure 7. Typical Output Supply Current per Channel vs.
Data Rate for 5 V and 3 V Operation (No Output Load)
DATA RATE (Mbps)
CURR
E
NT
/
C
HANNE
L
(
m
A)
0
0
3
2
1
4
10
20
30
5V
3V
05
92
7-
00
8
Figure 8. Typical Output Supply Current per Channel vs.
Data Rate for 5 V and 3 V Operation (15 pF Output Load)
DATA RATE (Mbps)
CURRE
NT
(
m
A
)
0
0
15
10
5
20
10
20
30
5V
3V
05
92
7-
00
9
Figure 9. Typical ADuM3200 V
DD1
Supply Current vs.
Data Rate for 5 V and 3 V Operation
DATA RATE (Mbps)
CUR
RE
NT
(
m
A)
0
0
3
2
1
4
10
20
30
5V
3V
059
27
-
01
0
Figure 10. Typical ADuM3200 V
DD2
Supply Current vs.
Data Rate for 5 V and 3 V Operation
DATA RATE (Mbps)
CURRE
NT
(
m
A
)
0
0
6
2
8
10
10
20
30
5V
3V
4
05
92
7-
01
1
Figure 11. Typical ADuM3201 V
DD1
or V
DD2
Supply Current vs.
Data Rate for 5 V and 3 V Operation
ADuM3200/ADuM3201
Rev. 0 | Page 15 of 20
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM320x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins. The
capacitor value should be between 0.01 F and 0.1 F. The total
lead length between both ends of the capacitor and the input
power supply pin should not exceed 20 mm.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design which varies widely by
application. The ADuM320x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices minimized by use
of guarding and isolation technique between PMOS and
NMOS devices.
Areas of high electric field concentration eliminated using
45 corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
While the ADuM320x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See
Application Note AN-793, ESD/Latch-Up Considerations with
iCoupler Isolation Products
for detailed recommendations on
board layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (V
IX
)
OUTPUT (V
OX
)
t
PLH
t
PHL
50%
50%
05
92
7-
01
2
Figure 12. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal's timing is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM320x component.
Propagation delay skew refers to the maximum amount that the
propagation delay differs between multiple ADuM320x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is therefore either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions of more than 2 s at the input, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than about 5 s, the input side is
assumed to be unpowered or nonfunctional, in which case,
the isolator output is forced to a default state (see Table 8) by
the watchdog timer circuit.
The ADuM320x are extremely immune to external magnetic
fields. The limitation on the ADuM320x's magnetic field
immunity is set by the condition in which induced voltage in
the transformer's receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM320x is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (-d/dt) r
n
2
, n = 1, 2, . . . , N
where:
is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
r
n
is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM320x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
ADuM3200/ADuM3201
Rev. 0 | Page 16 of 20
MAGNETIC FIELD FREQUENCY (Hz)
100
MA
XI
M
U
M A
L
L
O
W
A
B
L
E
MA
G
N
ET
I
C
F
L
U
X
DE
NS
I
T
Y
(
k
g
a
u
ss)
0.001
1M
10
0.01
1k
10k
10M
0.1
1
100M
100k
05
92
7-
0
13
Figure 13. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and had the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V--still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM320x transformers. Figure 14 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen, the ADuM320x are extremely immune and
can be affected only by extremely large currents operated at
high frequency and very close to the component. For the 1 MHz
example, one would have to place a 0.5 kA current 5 mm away
from the ADuM320x to affect the component's operation.
MAGNETIC FIELD FREQUENCY (Hz)
M
A
X
I
M
U
M
AL
L
O
W
A
BL
E
C
URRE
NT
(
k
A)
1000
100
10
1
0.1
0.01
1k
10k
100M
100k
1M
10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
05
92
7-
01
4
Figure 14. Maximum Allowable Current for Various
Current-to-ADuM320x Spacings
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
threshold of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM320x
isolator is a function of the supply voltage, the channel's data
rate, and the channel's output load.
For each input channel, the supply current is given by
I
DDI
= I
DDI (Q)
f 0.5f
r
I
DDI
= I
DDI (D)
(2f f
r
) + I
DDI (Q)
f > 0.5f
r
for each output channel, the supply current is given by
I
DDO
= I
DDO (Q)
f 0.5f
r
I
DDO
= (I
DDO (D)
+ (0.5 10
-3
) C
L
V
DDO
) (2f f
r
) + I
DDO (Q)
f > 0.5f
r
where:
I
DDI (D)
, I
DDO (D)
are the input and output dynamic supply currents
per channel (mA/Mbps).
C
L
is the output load capacitance (pF).
V
DDO
is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
f
r
is the input stage refresh rate (Mbps).
I
DDI (Q)
, I
DDO (Q)
are the specified input and output quiescent
supply currents (mA).
To calculate the total I
DD1
and I
DD2
supply current, the supply
currents for each input and output channel corresponding to
I
DD1
and I
DD2
are calculated and totaled. Figure 6 provides per-
channel input supply currents as a function of data rate. Figure 7
and Figure 8 provide per-channel output supply currents as a
function of data rate for an unloaded output condition and for a
15 pF output condition, respectively. Figure 9 through Figure 11
provide total I
DD1
and I
DD2
supply current as a function of data
rate for ADuM3200 and ADuM3201 channel configurations.
ADuM3200/ADuM3201
Rev. 0 | Page 17 of 20
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 15. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model
Number
of Inputs,
V
DD1
Side
Number
of Inputs,
V
DD2
Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse-Width
Distortion (ns)
Temperature
Range (C)
Package
Option
1
ADuM3200ARZ
2
2
0
1
150
40
-40 to +105
R-8
ADuM3200ARZ-RL7
2
2
0
1
150
40
-40 to +105
R-8
ADuM3200BRZ
2
2
0
10
50
3
-40 to +105
R-8
ADuM3200BRZ-RL7
2
2
0
10
50
3
-40 to +105
R-8
ADuM3200CRZ
2
2
0
25
45
3
-40 to +105
R-8
ADuM3200CRZ-RL7
2
2
0
25
45
3
-40 to +105
R-8
ADuM3201ARZ
2
1
1
1
150
40
-40 to +105
R-8
ADuM3201ARZ-RL7
2
1
1
1
150
40
-40 to +105
R-8
ADuM3201BRZ
2
1
1
10
50
3
-40 to +105
R-8
ADuM3201BRZ-RL7
2
1
1
10
50
3
-40 to +105
R-8
ADuM3201CRZ
2
1
1
25
45
3
-40 to +105
R-8
ADuM3201CRZ-RL7
2
1
1
25
45
3
-40 to +105
R-8
1
R-8 = 8-lead narrow body SOIC_N.
2
Z = Pb-free part.
ADuM3200/ADuM3201
Rev. 0 | Page 18 of 20
NOTES
ADuM3200/ADuM3201
Rev. 0 | Page 19 of 20
NOTES
ADuM3200/ADuM3201
Rev. 0 | Page 20 of 20
T
NOTES
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05927-0-
7/06(0)
TTT
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