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ADP3605 Data Sheet
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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3605
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
120 mA Switched Capacitor
Voltage Inverter with Regulated Output
FUNCTIONAL BLOCK DIAGRAM
S
D
OSC
CLOCK
GEN
FEEDBACK
CONTROL
LOOP
SD
S
D
B
S
D
S
D
N
C
P
+
C
P
P
N
N
S1
S3
V
IN
V
OUT
V
SENSE
GND
S2
S4
ADP3605
+
3.0V
V
IN
*C
O
4.7 F
+
*C
IN
4.7 F
+
ADP3605-3
*C
P
4.7 F
OFF
ON
0
V
SENSE
V
IN
C
P
+
C
P
SD
V
OUT
*FOR BEST PERFORMANCE, 10 F IS RECOMMENDED
C
P
: SPRAGUE, 293D475X0010B2W
C
IN
, C
O
: TOKIN, 1E475ZY5UC205F
GND
Figure 1. Typical Application Circuit
FEATURES
Fully Regulated Output Voltage (3 V and Adjustable)
High Output Current: 120 mA
Output Accuracy: 3%
250 kHz Switching Frequency
Low Shutdown Current: 2 A Typical
Input Voltage Range from 3 V to 6 V
SO-8 and RU-14 Packages
40 C to +85 C Ambient Temperature Range
APPLICATIONS
Voltage Inverters
Voltage Regulators
Computer Peripherals and Add-On Cards
Portable Instruments
Battery Powered Devices
Pagers and Radio Control Receivers
Disk Drives
Mobile Phones
GENERAL DESCRIPTION
The ADP3605 is a 120 mA regulated output switched capacitor
voltage inverter. It provides a regulated output voltage with
minimum voltage loss and requires a minimum number of ex-
ternal components. In addition, the ADP3605 does not require
the use of an inductor.
Pin-for-pin and functionally compatible with the ADP3604, the
internal oscillator of the ADP3605 runs at 500 kHz nominal
frequency which produces an output switching frequency of
250 kHz. This allows for the use of smaller charge pump and
filter capacitors.
The ADP3605 provides an accuracy of
3% with a typical shut-
down current of 2
A. It can also operate from a single positive
input voltage as low as 3 V. The ADP3605 is offered with the
regulation fixed at 3 V or adjustable via external resistors over
a 3 V to 6 V range.
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2
REV. A
ADP3605SPECIFICATIONS
1, 2, 3
Parameter
Symbol
Conditions
Min
Typ
Max
Units
OPERATING SUPPLY RANGE
V
S
3
5
6
V
SUPPLY CURRENT
I
S
40
C < T
A
< +85
C
3
6
mA
Shutdown Mode
V
SD
= V
IN
2
15
A
40
C < T
A
< +85
C
OUTPUT VOLTAGE
4
V
O
I
O
= 60 mA
3.09
3.0
2.91
V
I
O
= 10 mA120 mA,
3.15
3
2.85
V
40
C
T
A
+85
C
4.75 V
V
S
6.0 V
LOAD REGULATION
V
O
/I
O
I
O
= 10 mA60 mA
0.3
mV/mA
I
O
= 10 mA120 mA
0.25
mV/mA
OUTPUT RESISTANCE
Open Loop
R
O
9
OUTPUT RIPPLE VOLTAGE
V
RIPPLE
C
IN
= C
O
= 4.7
F,
I
LOAD
= 60 mA
38
mV
I
LOAD
= 120 mA
75
mV
SWITCHING FREQUENCY
F
S
V
IN
= 5 V
212
250
288
kHz
40
C < T
A
< +85
C
SHUTDOWN
Logic Input High
V
IH
2.4
V
Input Current
I
IH
1
A
Logic Input Low
V
IL
0.4
V
Input Current
I
IL
1
A
NOTES
1
Capacitors C
IN,
C
O
and C
P
in the test circuit are 4.7
F with 0.1
ESR.
2
See Figure 1 Conditions.
3
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
4
For the adjustable device, a 1% resistor should be used to maintain output voltage tolerance. For both device types, tolerances can be improved by >1% using larger
value and lower ESR capacitors for C
O
and C
P
.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25
C unless otherwise noted)
Input Voltage (V+ to GND, GND to OUT) . . . . . . . . +7.5 V
Input Voltage (V+ to OUT) . . . . . . . . . . . . . . . . . . . . . +11 V
Output Short Circuit Protection . . . . . . . . . . . . . . . . . . . 1 sec
Power Dissipation, SO-8 . . . . . . . . . . . . . . . . . . . . . . 660 mW
JA
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
C/W
Power Dissipation, RU-14 . . . . . . . . . . . . . . . . . . . . . 600 mW
JA
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
C/W
Operating Temperature Range . . . . . . . . . . . 40
C to +85
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
NOTES
1
This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
2
JA
is specified for worst case conditions with device soldered on a circuit board.
ORDERING GUIDE
Model
Output Voltage
Package Description
Package Options*
ADP3605AR-3
3 V
Small Outline
SO-8
ADP3605AR
ADJ
Small Outline
SO-8
ADP3605ARU-3
3 V
Thin Shrink Small Outline Package (TSSOP)
RU-14
*Contact the factory for the availability of other output voltage options.
(V
IN
= 5.0 V @ T
A
= +25 C, C
P
= C
O
= 4.7 F unless otherwise noted)
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ADP3605
3
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3605 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges larger than 600 V HBM.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss
of functionality.
WARNING!
ESD SENSITIVE DEVICE
Table I. Other Members of ADP36xx Family
1
Output
Package
Model
Current
Option
2
Comments
ADP3603AR
50 mA
SO-8
Nom.3
3% Inverter
ADP3604AR
120 mA
SO-8
Nom.3
3% Inverter
ADP3610ARU 320 mA
TSSOP-16 Nom. 3.3 V
IN
Doubler
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline; TSSOP = Thin Shrink Small Outline Package.
Table II. Alternative Capacitor Technologies
High
Type
Life
Freq
Temp
Size
Cost
Aluminum
Electrolytic
Capacitor
Fair
Fair
Fair
Small
Low
Multilayer
Ceramic
Capacitor
Long
Good
Poor
Fair
1
High
Solid
Tantalum
Above
Capacitor
Avg
Avg
Avg
Avg
Avg
OS-CON
Above
Capacitor
Avg
Good
Good
Good
Avg
NOTE
1
Refer to capacitor manufacturer's data sheet for operation below 0
C.
Table III. Recommended Capacitor Manufacturers
Manufacturer
Capacitor
Capacitor Type
Sprague
672D, 673D,
674D, 678D
Aluminum Electrolytic
Sprague
675D, 173D,
199D
Tantalum
Nichicon
PF and PL
Aluminum Electrolytic
Mallory
TDC and TDL
Tantalum
TOKIN
MLCC
Multilayer Ceramic
MuRata
GRM
Multilayer Ceramic
PIN FUNCTION DESCRIPTIONS
Pin
Pin
SO-8 TSSOP Name
Function
1
4
C
P
+
Positive Terminal for the Pump
Capacitor.
2
5
GND
Device Ground.
3
6
C
P
Negative Terminal for the Pump
Capacitor.
4
7
SD
Logic Level Shutdown Pin. Apply a
logic high or connect to V
IN
to shut-
down the device. In shutdown mode,
the charge pump is turned off and
quiescent current is reduced to 2
A
(typical). Apply a logic low or con-
nect to ground for normal operation.
5
8
V
SENSE
Output Voltage Sense Line. This is
used to improve load regulation by
eliminating IR drop on the high
current carrying output traces. For
normal operation, connect V
SENSE
to
V
OUT
. See Application section for
more detail.
6
1, 2, 3,
9, 12,
13, 14
NC
No Connection.
7
10
V
OUT
Regulated Negative Output Voltage.
Connect a low ESR, 4.7
F or larger
capacitor between this pin and de-
vice GND.
8
11
V
IN
Positive Supply Input Voltage. Con-
nect a low ESR bypass capacitor
between this pin and device ground
to minimize supply transients.
PIN CONFIGURATIONS
RU-14
SO-8
ADP3605
NC
NC
NC
V
IN
V
OUT
NC
V
SENSE
NC
NC
NC
SD
C
P
GND
C
P
+
NC = NO CONNECT
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
NC = NO CONNECT
C
P
+
GND
C
P
V
IN
V
OUT
NC
V
SENSE
SD
ADP3605
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ADP3605
4
REV. A
SUPPLY VOLTAGE Volts
OSCILLATOR FREQUENCY kHz
270
260
250
3
3.5
6
4
4.5
5
5.5
Figure 2. Oscillator Frequency vs.
Supply Voltage
TEMPERATURE C
OSCILLATOR FREQUENCY kHz
300
280
200
40
15
85
10
35
60
260
240
220
Figure 5. Oscillator Frequency vs.
Temperature
SUPPLY VOLTAGE Volts
SUPPLY CURRENT mA
IN NORMAL MODE
3.5
3
0
3
4
6
5
2
1.5
1
SHUTDOWN MODE
(V
SD
= V
IN
)
0.5
2.5
7
6
0
4
3
1
2
5
SUPPLY CURRENT
A
IN SHUTDOWN MODE
NORMAL MODE
(V
SD
= 0V)
Figure 8. Supply Current vs. Supply
Voltage
Typical Performance Characteristics
SUPPLY CURRENT mA
IN NORMAL MODE
4.5
4
3.5
3
2.5
2
1.5
40
15
10
35
60
85
TEMPERATURE C
SUPPLY CURRENT
A
IN SHUTDOWN MODE
3
0
2
1
2.5
1.5
0.5
V
IN
= +5V
SHUTDOWN MODE
(V
SD
= V
IN
)
NORMAL MODE
(V
SD
= 0V)
Figure 3. Supply Current vs.
Temperature
LOAD CURRENT mA
INPUT CURRENT mA
140
0
10
30
130
50
70
90
110
120
100
80
40
20
60
Figure 6. Average Input Current
vs. Output Current
Figure 9 . Start-Up Under Full Load
TEMPERATURE C
OUTPUT VOLTAGE Volts
2.96
2.97
3.03
40
15
85
10
35
60
2.99
3.00
3.01
3.02
2.98
I
L
= 120mA
I
L
= 60mA
I
L
= 10mA
Figure 4. Output Voltage vs.
Temperature
LOAD CURRENT mA
OUTPUT VOLTAGE Volts
2.5
2.6
3.2
0
40
200
80
120
160
2.7
2.8
2.9
3.0
3.1
240
280
V
IN
= +6V
V
IN
= +5V
V
IN
= +4.75V
V
IN
= +3.5V
V
IN
= +3V
Figure 7. Output Voltage vs. Load
Current
Figure 10. Enable/Disable Time
Under Full Load
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ADP3605
5
REV. A
THEORY OF OPERATION
The ADP3605 uses a switched capacitor principle to generate a
negative voltage from a positive input voltage. An onboard
oscillator generates a two phase clock to control a switching
network that transfers charge between the storage capacitors.
The switches turn on and off at a 250 kHz rate, which is gener-
ated from an internal 500 kHz oscillator. The basic principle
behind the voltage inversion scheme is illustrated in Figures 11
and 12.
S2
S1
V
IN
V
OUT
S3
S4
C
O
+
C
P
Figure 11. ADP3605 Switch Configuration Charging the
Pump Capacitor
During phase one, S1 and S2 are ON, charging the pump ca-
pacitor to the input voltage. Before the next phase begins, S1
and S2
are turned OFF as well as S3 and S4 to prevent any
overlap. S3 and S4
are turned ON during the second phase (see
Figure 12) and charge stored in the pump capacitor is trans-
ferred to the output capacitor.
+
S2
S1
S3
S4
C
O
C
P
V
IN
V
OUT
Figure 12. ADP3605 Switch Configuration Charging the
Output Capacitor
During the second phase, the positive terminal of the pump
capacitor is connected to ground through variable resistance
switch, S3, and the negative terminal is connected to the out-
put, resulting in a voltage inversion at the output terminal.
The ADP3605 block diagram is shown on the front page.
APPLICATION INFORMATION
Capacitor Selection
The ADP3605's high internal oscillator frequency permits the
use of small capacitors for both the pump and the output ca-
pacitors. For a given load current, factors affecting the output
voltage performance are:
Pump (C
P
) and output (C
O
) capacitance.
ESR of the C
P
and C
O
.
When selecting the capacitors, keep in mind that not all manu-
facturers guarantee capacitor ESR in the range required by the
circuit. In general, the capacitor's ESR is inversely proportional
to its physical size, so larger capacitance values and higher volt-
age ratings tend to reduce ESR. Since the ESR is also a function
of the operating frequency, when selecting a capacitor, make
sure its value is rated at the circuit's operating frequency.
Temperature is another factor affecting capacitor performance.
Figure 13 illustrates the temperature effect on various capaci-
tors. If the circuit has to operate at temperatures significantly
different from 25
C, the capacitance and ESR values must be
carefully selected to adequately compensate for the change.
Various capacitor technologies offer improved performance over
temperature; for example, certain tantalum capacitors provide
good low-temperature ESR but at a higher cost. Table II pro-
vides the ratings for different types of capacitor technologies to
help the designer select the right capacitors for the applica-
tion. The exact values of C
IN
and C
O
are not critical. How-
ever, low ESR capacitors such as solid tantalum and multilayer
ceramic capacitors are recommended to minimize voltage loss at
high currents. Table III shows a partial list of the recommended
low ESR capacitor manufacturers.
Input Capacitor
A small 1
F input bypass capacitor, preferably with low ESR,
such as tantalum or multilayer ceramic, is recommended to
reduce noise and supply transients and supply part of the peak
input current drawn by the ADP3605. A large capacitor is rec-
ommended if the input supply is connected to the ADP3605
through long leads, or if the pulse current drawn by the device
might affect other circuitry through supply coupling.
Output Capacitor
The output capacitor (C
O
) is alternately charged to the C
P
volt-
age when C
P
is switched in parallel with C
O
. The ESR of C
O
introduces steps in the V
OUT
waveform whenever the charge
pump charges C
O
, which contributes to V
OUT
ripple. Thus,
ceramic or tantalum capacitors are recommended for C
O
to
minimize ripple on the output. Figure 14 illustrates the output
ripple voltage effect for various capacitance and ESR values.
Note that as the capacitor value increases beyond the point
where the dominant contribution to the output ripple is due to
the ESR, no significant reduction in V
OUT
ripple is achieved by
added capacitance. Since output current is supplied solely by
the output capacitor, C
O
,
during one-half of the charge-pump
cycle, peak-to-peak output ripple voltage is calculated by using
the following formula.
V
I
F
C
I
ESR
RIPPLE
L
S
O
L
CO
=
+
2
2
where:
I
L
= Load Current
F
S
= 250 kHz nominal switching frequency
C
O
= 10
F with an ESR of 0.15
V
mA
kHz
F
mA
mV
RIPPLE
=
+
=
120
2
250
10
2
120
0 15
60
.
Multiple smaller capacitors can be connected in parallel to yield
lower ESR and lower cost. For lighter loads, proportionally
smaller capacitors are required. To reduce high frequency
noise, bypass the output with a 0.1
F ceramic capacitor in
parallel with the output capacitor.
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ADP3605
6
REV. A
Pump Capacitor
The ADP3605 alternately charges C
P
to the input voltage when
C
P
is switched in parallel with the input supply, and then trans-
fers charge to C
O
when C
P
is switched in parallel with C
O
.
During the time C
P
is charging, the peak current is approxi-
mately two times the output current.
During the time C
P
is delivering charge to C
O
, the supply cur-
rent drops down to about 3 mA.
A low ESR capacitor has much greater impact on performance
for C
P
than C
O
since current through C
P
is twice the C
O
cur-
rent. Therefore, the voltage drop due to C
P
is about four times
the ESR of C
P
times the load current. While the ESR of C
O
affects the output ripple voltage, the voltage drop generated by
the ESR of C
P
, combined with the voltage drop due to the output
source resistance, determines the maximum available V
OUT
.
TEMPERATURE C
10
1.0
0.01
50
100
0
ESR
50
0.1
ALUMINUM
CERAMIC
TANTALUM
ORGANIC SEMIC
Figure 13. ESR vs. Temperature
CAPACITANCE F
100
80
0
0
160
20
OUTPUT RIPPLE mV
40
60
80
100
120
140
60
40
20
ADP3605-3
150m
100m
50m
Figure 14. Output Ripple Voltage (mV) vs. Capacitance
and ESR
Improved Load Regulation
In most applications, the IR drop from printed circuit board
traces is not critical. V
SENSE
should be connected to the output
at a convenient PCB location close to the load. However, if a
reduction in IR drop or improvement in load regulation is de-
sired, the sense line can be used to monitor the output voltage
at the load. To avoid excessive noise pickup, keep the V
SENSE
line as short as possible and away from any noisy line.
Shutdown Mode
The ADP3605's output can be disabled by pulling the SD pin
(Pin 4) high to a TTL/CMOS logic compatible level which will
stop the internal oscillator. In shutdown mode, the quiescent
current is reduced to 2
A (typical). Applying a digital low level
or tying the SD Pin to ground will turn on the output. If the
shutdown feature is not used, Pin 4 should be tied to the
ground pin.
Power Dissipation
The power dissipation of the ADP3605 circuit must be limited
such that the junction temperature of the device does not exceed
the maximum junction temperature rating. Total power dissipa-
tion is calculated as follows:
P = (V
IN
|
V
OUT
|)
I
OUT
+ (
V
IN
)
I
S
Where
I
OUT
and
I
S
are output current and supply current,
V
IN
and
V
OUT
are input and output voltages respectively.
For example: assuming worst case conditions, V
IN
= 6 V,
V
OUT
= 2.9 V, I
OUT
= 120 mA and I
S
= 5 mA. Calculated
device power dissipation is:
P
(6
V|2.9 V|)(0.12) + (6 V)(0.005 A) = 402 mW
This is far below the 660 mW power dissipation capability of the
ADP3605 in SO-8 or 600 mW in RU-14
General Board Layout Guidelines
Since the ADP3605's internal switches turn on and off very fast,
good PC board layout practices are critical to ensure optimal
operation of the device. Improper layouts will result in poor load
regulation, especially under heavy loads. Following these simple
layout guidelines will improve output performance.
1. Use adequate ground and power traces or planes.
2. Use single point ground for device ground and input and
output capacitor grounds.
3. Keep external components as close to the device as possible.
4. Use short traces from the input and output capacitors
to the input and output pins respectively.
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ADP3605
7
REV. A
Maximum Output Voltage
Maximum unregulated output voltage can be obtained on the
ADP3605-3 by connecting the V
SENSE
pin to ground instead of
to the V
OUT
pin. Under this condition, the magnitude of the
unregulated output voltage depends on the load current. V
OUT
is inversely proportional to the load current as illustrated in
Figure 15.
LOAD CURRENT mA
5.0
3.0
0
120
V
OUT
Volts
20
40
60
80
100
4.0
ADP3605-3
V
IN
= +5.0V
Figure 15. Maximum Unregulated Output Voltage
Regulated Adjustable Output Voltage
For the adjustable version of the ADP3605, the regulated out-
put voltage is programmed by a resistor which is inserted be-
tween the V
SENSE
and V
OUT
pins, as illustrated in Figure 16.
The inherent limit of the output voltage of a single inverting
charge pump stage is 1 times the input voltage. The inverse
(i.e., negative) scaling factor of 1.00 is reduced somewhat due to
losses that increase with output current. To increase the scaling
factor to attain a more negative output voltage, an external
pump stage can be added with just passive components as
shown in Figure 17. That single stage increases the inverse
scaling factor to a limit of two, although the diode drops will
limit the ability to attain that exact 2.00 scaling factor notice-
ably. Even further increases can be achieved with more external
pump stages.
LOAD CURRENT mA
5.0
3.0
0
120
V
OUT
Volts
20
40
60
80
100
4.0
ADP3605
V
IN
= +5.0V
V
OUT
R
R = 29k
R = 24k
Figure 16. Adjustable Regulated Output Voltage
High accuracy on the adjustable output voltage is achieved with
the use of precision trimmed internal resistors, which eliminates
the need to trim the external resistor or add a second resistor to
form a divider. The adjustable output voltage is set using the
following formula:
V
OUT
=
1.5
9.5
k
R
where
V
OUT
is in volts and
R is in k
.
Regulated Dual Supply System
The circuit in Figure 18 provides regulated positive and negative
voltages for systems that require dual supplies from a single
battery or power supply.
ADP3605
V
IN
C
P
+
C
P
SD
V
SENSE
V
OUT
GND
+
C
P
4.7 F
C
IN
4.7 F
V
IN
= +5V
C
O
4.7 F
+
+
10 F
C1
4.7 F
D2
1N5817
D1
1N5817
+
+
R1
44.2k
Figure 17. Regulated 7 V from a 5 V Input
ADP3607-5
V
IN
C
P
+
C
P
SD
V
SENSE
V
OUT
GND
+
C
P1
10 F
10 F
C
O1
10 F
+
+
+5V
ADP3605
V
IN
C
P
+
C
P
SD
V
SENSE
V
OUT
GND
+
C
P2
10 F
C
O2
10 F
+
R1
16.5k
1%
1N5817
V
IN
= +3.3V
2.6V
Figure 18. Dual Supply System
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ADP3605
8
REV. A
C3325a07/99
PRINTED IN U.S.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Small Outline IC
(SO-8)
14-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-14)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
14
8
7
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0