6-Bit, Programmable 2-/3-/4-Phase,
Synchronous Buck Controller
ADP3190
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
9.5 mV worst-case differential sensing error
over temperature
Logic-level PWM outputs for interface to external
high power drivers
PWM Flex-Mode
TM
architecture for excellent load
transient performance
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next-generation Intel processors
VRM modules
Games consoles
GENERAL DESCRIPTION
The ADP3190/ADP3190A
1
are highly efficient, multiphase,
synchronous buck switching regulator controllers optimized for
converting a 5 V or 12 V main supply into the core supply voltage
required by high performance Intel processors. They use an
internal 6-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 0.8375 V and 1.6 V. The devices use a multimode
PWM architecture to drive the logic-level outputs at a
programmable switching frequency that can be optimized for
VR size and efficiency. The phase relationship of the output
signals can be programmed to provide 2-, 3-, or 4-phase
operation, allowing for the construction of up to four
complementary buck switching stages.
The ADP3190/ADP3190A also include programmable, no-load
offset and slope functions to adjust the output voltage as a function
of the load current, so it is always optimally positioned for a
system transient. The ADP3190/ADP3190A also provide
accurate and reliable short-circuit protection, adjustable current
limiting, and a delayed power good output that accommodates
on-the-fly output voltage changes requested by the CPU.
1
Protected by U. S. Patent Number 6,683,441; other patents pending.
FUNCTIONAL BLOCK DIAGRAM
VCC
PRECISION
REFERENCE
SOFT
START
DELAY
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
GND
ADP3190
DELAY
ILIMIT
PWRGD
RT
RAMPADJ
PWM2
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
COMP
VID
DAC
DAC
+150mV
DAC
250mV
CSREF
EN
CURRENT
LIMIT
CIRCUIT
CROWBAR
CURRENT
LIMIT
CMP
CMP
CURRENT
BALANCING
CIRCUIT
CMP
CMP
2-/3-/4-PHASE
DRIVER LOGIC
EN
SET
RESET
RESET
RESET
RESET
SHUNT
REGULATOR
(ADP3190 ONLY)
18
20
21
22
23
24
25
26
27
13
14
28
EN
11
19
10
15
12
FBRTN
7
VID4
1
VID3
2
VID2
3
VID1
4
VID0
5
VID5
6
FB
8
9
17
16
05
384
-
00
1
Figure 1.
The ADP3190 is a replacement for the
ADP3188
. A built-in
shunt regulator allows the part to be connected to the 12 V
system supply through a series resistor.
The devices are specified over the commercial temperature
range of 0C to +85C and are available in a 28-lead TSSOP and
a 28-lead QSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
ADP3190
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics and Test Circuits............... 7
Theory of Operation ........................................................................ 8
Startup Sequence .......................................................................... 8
Master Clock Frequency.............................................................. 8
Output Voltage Differential Sensing .......................................... 8
Output Current Sensing .............................................................. 8
Active Impedance Control Mode............................................... 9
Current-Control Mode and Thermal Balance.......................... 9
Voltage Control Mode.................................................................. 9
Soft Start ........................................................................................ 9
Current-Limit, Short-Circuit, and Latch-Off Protection...... 10
Dynamic VID.............................................................................. 10
Power Good Monitoring ........................................................... 12
Output Crowbar ......................................................................... 12
Output Enable and UVLO ........................................................ 12
Application Information................................................................ 14
Setting the Clock Frequency..................................................... 14
Soft Start and Current-Limit Latch-Off Delay Times ........... 14
Inductor Selection ...................................................................... 14
Designing an Inductor............................................................... 15
Output Droop Resistance.......................................................... 15
Inductor DCR Temperature Correction ................................. 16
Output Offset .............................................................................. 16
C
OUT
Selection ............................................................................. 17
Power MOSFETs......................................................................... 18
Ramp Resistor Selection............................................................ 19
COMP Pin Ramp ....................................................................... 19
Current-Limit Setpoint.............................................................. 19
Feedback Loop Compensation Design.................................... 19
C
IN
Selection and Input Current di/dt Reduction.................. 21
Tuning the ADP3190/ADP3190A............................................ 22
Replacing the ADP3188 with the ADP3190........................... 24
Choosing Between the ADP3190 and the ADP3190A ........ 24
Layout and Component Placement.............................................. 25
General Recommendations....................................................... 25
Power Circuitry Recommendations ........................................ 25
Signal Circuitry Recommendations......................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
1/06--Revision 0: Initial Version
ADP3190
Rev. 0 | Page 3 of 28
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, T
A
= 0C to +85C, unless otherwise noted.
1
Table 1.
Parameter Symbol
Conditions
Min
Typ
Max
Units
ERROR AMPLIFIER
Output Voltage Range
V
COMP
0
VCC
V
Accuracy V
FB
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP, V
OUT
< 1 V
-8.0
+8.0 mV
Accuracy V
FB
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP, V
OUT
> 1 V
-9.5
+9.5 mV
Line Regulation
V
FB
VCC = 4.75 V to 5.25 V
0.05
%
Input Bias Current
I
FB
14
15.5
17
A
FBRTN Current
I
FBRTN
100
140
A
Output Current
I
O(ERR)
FB forced to V
OUT
3%
500
A
Gain Bandwidth Product
GBW
(ERR)
COMP = FB
20
MHz
Slew Rate
C
COMP
= 10 pF
25
V/s
VID INPUTS
Input Low Voltage
V
IL(VID)
0.4
V
Input High Voltage
V
IH(VID)
0.8
V
Input Current, Input Voltage Low
I
IL(VID)
VID(X) = 0 V
25
35
A
Input Current, Input Voltage High
I
IH(VID)
VID(X) = 1.25 V
5
15
A
Pull-up Resistance
R
VID
35
60
85
k
Internal Pull-up Voltage
1.0
1.2
V
VID Transition Delay Time
2
VID code change to FB change
400
ns
No CPU Detection Turn-off Delay
Time
2
VID code change to 11111 to PWM going low
400
ns
OSCILLATOR
Frequency Range
2
f
OSC
0.25
4
MHz
Frequency Variation
f
PHASE
T
A
= +25C, R
T
= 225 k, 4-phase
155
200
245
kHz
T
A
= +25C, R
T
= 100 k, 4-phase
400
kHz
T
A
= +25C, R
T
= 30 k, 4-phase
600
kHz
Output Voltage
V
RT
R
T
= 100 k to GND
1.8
2.0
2.3
V
RAMPADJ Output Voltage
V
RAMPADJ
RAMPADJ FB
50
+50
mV
RAMPADJ Input Current Range
I
RAMPADJ
0
100
A
CURRENT SENSE AMPLIFIER
Offset Voltage
V
OS(CSA)
CSSUM CSREF
1.5
+1.5
mV
Input Bias Current
I
BIAS(CSSUM)
10
+10
nA
Gain Bandwidth Product
GBW
(CSA)
10
MHz
Slew Rate
C
CSCOMP
= 10 pF
10
V/s
Input Common-Mode Range
CSSUM and CSREF
0
3
V
Positioning Accuracy
V
FB
See Figure 5
77 80 83 mV
Output Voltage Range
0.05
VCC
V
Output Current
I
CSCOMP
500
A
CURRENT BALANCE CIRCUIT
Common-Mode Range
V
SW(X)CM
600
+200
mV
Input Resistance
R
SW(X)
SW(X) = 0 V
12
20
28
k
Input Current
I
SW(X)
SW(X) = 0 V
5
11
17
A
Input Current Matching
3
I
SW(X)
SW(X) = 0 V
5
+5
%
ADP3190
Rev. 0 | Page 4 of 28
Parameter Symbol
Conditions
Min
Typ
Max
Units
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
V
ILIMIT(NM)
EN > 0.8 V, R
ILIMIT
= 250 k
2.8
3
3.3
V
In Shutdown
V
ILIMIT(SD)
EN < 0.4 V, I
ILIMIT
= 100 A
400
mV
Output Current, Normal Mode
I
ILIMIT(NM)
EN > 0.8 V, R
ILIMIT
= 250 k
12
A
Maximum Output Current
2
60
A
Current Limit Threshold Voltage
V
CL
V
CSREF
V
CSCOMP
, R
ILIMIT
= 250 k
105
125
145
mV
Current Limit Setting Ratio
V
CL
/I
ILIMIT
10.4
mV/A
DELAY Normal Mode Voltage
V
DELAY(NM)
R
DELAY
= 250 k
2.8
3
3.3
V
DELAY Overcurrent Threshold
V
DELAY(OC)
R
DELAY
= 250 k
1.6
1.9
2.2
V
Latch-Off Delay Time
t
DELAY
R
DELAY
= 250 k, C
DELAY
= 12 nF
1.5
ms
SOFT START
Output Current, Soft Start Mode
I
DELAY(SS)
During startup, DELAY < 2.8 V
15
20
25
A
Soft Start Delay Time
t
DELAY(SS)
R
DELAY
= 250 k, C
DELAY
= 12 nF,
VID code = 011111
1
ms
ENABLE INPUT
Input Low Voltage
V
IL(EN)
0.4
V
Input High Voltage
V
IH(EN)
0.8
V
Input Current
I
IL(EN)
1
+1
A
POWER GOOD COMPARATOR
Undervoltage Threshold
V
PWRGD(UV)
Relative to nominal DAC output
180
250
300
mV
Overvoltage Threshold
V
PWRGD(OV)
Relative to nominal DAC output
90
150
200
mV
Output Low Voltage
V
OL(PWRGD)
I
PWRGD(SINK)
= 4 mA
225
400
mV
Power Good Delay Time
During Soft Start
R
DELAY
= 250 k, C
DELAY
= 12 nF,
VID code = 011111
1 ms
VID Code Changing
100
250
s
VID Code Static
200
ns
Crowbar Trip Point
V
CROWBAR
Relative to nominal DAC output
90
150
200
mV
Crowbar Reset Point
Relative to FBRTN
450
550
650
mV
Crowbar Delay Time
t
CROWBAR
Overvoltage to PWM going low
VID Code Changing
Blanking time
100
250
s
VID Code Static
400
ns
PWM OUTPUTS
Output Low Voltage
V
OL(PWM)
I
PWM(SINK)
= 400 A
160
500
mV
Output High Voltage
V
OH(PWM)
I
PWM(SOURCE)
= +400 A
4.0
5
V
SUPPLY--ADP3190
V
SYSTEM
= 12 V, R
SHUNT
= 240 , see Figure 4
VCC VCC
5
V
DC Supply Current
20
30
mA
UVLO Threshold Voltage
V
UVLO
VCC rising
6.3
7
8.0
V
UVLO Hysteresis
0.9
V
SUPPLY--ADP3190A
V
SYSTEM
= 5V, R
SHUNT
= 10 , see Figure 4
VCC VCC
5
V
DC Supply Current
7
12
mA
UVLO Threshold Voltage
V
UVLO
VCC rising
3.7
4.0
4.3
V
UVLO Hysteresis
0.9
V
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2
Guaranteed by design, not production tested. Specifications subject to change without notice.
3
Relative current matching from each phase to the average of all four phases.
ADP3190
Rev. 0 | Page 5 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC
0.3 V to +6 V
VID Pins
0.3 V to +6 V
FBRTN
0.3 V to +0.3 V
SW1 to SW4
-5 V to +25 V
All Other Inputs and Outputs
0.3 V to VCC + 0.3 V
Storage Temperature Range
65C to +150C
Operating Ambient Temperature Range
0C to +85C
Operating Junction Temperature
125C
Thermal Impedance (
JA
)
100C/W
Lead Temperature
Soldering (10 sec)
300C
Vapor Phase (60 sec)
215C
Infrared (15 sec)
220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADP3190
Rev. 0 | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
(Not to Scale)
ADP3190
VID3
VID2
VID1
FBRTN
VID5
VID0
VID4
PWM1
PWM2
PWM3
SW2
SW1
PWM4
FB
COMP
PWRGD
RAMPADJ
DELAY
EN
SW3
SW4
GND
ILIMIT
RT
CSREF
CSSUM
CSCOMP
VCC
05
38
4-
0
05
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 6
VID4 to VID0,
VID5
Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from
0.8375 V to 1.6 V (see Table 2). Leaving all the VID pins open results in ADP3190/ADP3190A going into a
"No CPU" mode, shutting off their PWM outputs and pulling the PWRGD output low.
7
FBRTN
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
9 COMP
Error
Amplifier
Output and Compensation Point.
10 PWRGD
Power Good Output. Open drain output that signals when the output voltage is outside of the proper
operating range.
11 EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output
low.
12 DELAY
Soft start Delay and Current-Limit Latch-off Delay Setting Input. An external resistor and capacitor
connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay
time.
13 RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device.
14 RAMPADJ
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
15 ILIMIT
Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit
threshold of the converter. This pin is actively pulled low when the ADP3190/ADP3190A EN input is low or
when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side
outputs should go low.
16 CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.
17 CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
18 CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of
the load line and the positioning loop response time.
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23
SW4 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
24 to 27
PWM4 to PMW1
Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3120A
. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3190/ADP3190A to operate as a 2-, 3-, or 4-phase controller.
28
VCC
ADP3190: A 240 resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V.
ADP3190A: A 10 resistor should be placed between the 5 V system supply and the VCC pin to ensure 5 V.
ADP3190
Rev. 0 | Page 7 of 28
TYPICAL PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
2.8
0
M
A
S
T
E
R
CL
O
CK F
R
E
Q
UE
N
C
Y (
M
H
z
)
R
T
(k
)
0
50
100
150
200
250
300
05
38
4-
00
6
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Figure 3. Master Clock Frequency vs. R
T
250k
1.25V
1
F
100nF
100nF
ADP3190
ADP3190A
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
COMP
PWRGD
EN
DELAY
RT
RAMPADJ
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
1
2
3
28
27
26
4
8
10
12
14
5
6
7
21
24
23
22
9
11
17
18
19
13
15
16
20
25
6-BIT CODE
250k
20k
1k
12nF
0
538
4-
002
12V
+
240
5V
ADP3190A
ADP3190
Figure 4. Closed-Loop Output Voltage Accuracy
CSSUM
CSCOMP
VCC
CSREF
GND
39k
100nF
1k
1.0V
ADP3190
V
OS
=
CSCOMP 1V
40
05
38
4-
00
3
12V
300
18
17
28
16
19
Figure 5. Current Sense Amplifier V
OS
CSSUM
18
CSCOMP
17
28
VCC
CSREF
16
GND
19
200k
100nF
1.0V
ADP3190/ADP3190A
05
38
4-
00
4
V
12V
240
5V
ADP3190A
ADP3190
200k
V
FB
= FB
V
= 80mV FB
V
= 0mV
Figure 6. Positioning Voltage
ADP3190
Rev. 0 | Page 8 of 28
THEORY OF OPERATION
The ADP3190/ADP3190A combine a multimode, fixed frequency
PWM control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
6-bit VRD/VRM 10- and 10.1-compatible CPUs. Multiphase
operation is important for producing the high currents and
low voltages demanded by today's microprocessors. Handling
the high currents in a single-phase converter places high thermal
demands on the components in the system, such as the inductors
and MOSFETs.
The multimode control of the ADP3190/ADP3190A ensures
a stable, high performance topology for
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
Minimizing thermal switching losses due to lower
frequency operation
Tight load line regulation and accuracy
High current output for up to 4-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
Flexibility in operation for tailoring design to low cost or
high performance
STARTUP SEQUENCE
During startup, the number of operational phases and their phase
relationship is determined by the internal circuitry that monitors
the PWM outputs. Normally, the ADP3190/ADP3190A operate
as a 4-phase PWM controller. Grounding the PWM4 pin programs
3-phase operation, and grounding the PWM3 pin and the
PWM4 pin programs 2-phase operation.
When the ADP3190/ADP3190A are enabled, the controller
outputs a voltage on PWM3 and PWM4, which is approxi-
mately 675 mV. An internal comparator checks each pin's
voltage vs. a threshold of 300 mV. If the pin is grounded, it
is below the threshold, and the phase is disabled. The output
resistance of the PWM pins is approximately 5 k during this
detection time. Any external pull-down resistance connected
to the PWM pins should not be less than 25 k to ensure
proper operation. PWM1 and PWM2 are disabled during
the phase detection interval, which occurs during the first
two clock cycles of the internal oscillator.
After this time, if the PWM output is not grounded, the 5 k
resistance is removed, and it switches between 0 V and 5 V.
If the PWM output is grounded, it remains off. The PWM out-
puts are logic-level devices intended for driving external gate
drivers, such as the
ADP3120A
. Because each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3190/ADP3190A is set with
an external resistor connected from the RT pin to ground.
The frequency follows the graph in Figure 3. To determine
the frequency per phase, the clock is divided by the number of
phases in use. If PWM4 is grounded, divide the master clock by 3
for the frequency of the remaining phases. If PWM3 and PWM4
are grounded, divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3190/ADP3190A differential sense compares a high
accuracy VID DAC and a precision reference to implement a low
offset error amplifier. This maintains a worst-case specification
of 9.5 mV differential sensing error over their full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and the FBRTN pin. FB should be
connected through a resistor to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN should be
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 100 A to allow accurate
remote sensing. The internal error amplifier compares the
output of the DAC to the FB pin to regulate the output voltage.
OUTPUT CURRENT SENSING
The ADP3190/ADP3190A provide a dedicated current sense
amplifier (CSA) to monitor the total output current for proper
voltage positioning vs. load current and for current-limit detec-
tion. Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element, such as the low-side MOSFET.
This amplifier can be configured several ways, depending on the
objectives of the system:
Output inductor DCR sensing without a thermistor for
lowest cost
Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements
ADP3190
Rev. 0 | Page 9 of 28
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor.
The current information is then given as the difference of
CSREF - CSCOMP. This difference signal is used internally to
offset the VID DAC for voltage positioning and as a differential
input for the current-limit comparator.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors, so it can be made
extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of
output current, a signal proportional to the total output current at
the CSCOMP pin can be scaled to equal the droop impedance of
the regulator multiplied by the output current. This droop voltage
is then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input voltage
directly to tell the error amplifier where the output voltage should
be. This differs from previous implementations and allows
enhanced feed-forward response.
CURRENT-CONTROL MODE AND
THERMAL BALANCE
The ADP3190/ADP3190A have individual inputs for each phase,
which are used for monitoring the current in each phase. This
information is combined with an internal ramp to create a
current balancing feedback system, which has been optimized
for initial current balance accuracy and dynamic thermal
balancing during operation. This current-balance information
is independent of the average output current information used
for positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the
supply voltage for feed-forward control for changes in the supply.
A resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given in
the Application Information section.
External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance such as
when one phase may have better cooling and can support higher
currents. Resistor R
SW1
through Resistor R
SW4
(see the typical
application circuit in Figure 9) can be used for adjusting
thermal balance. It is best to have the ability to add these resistors
during the initial design, so make sure that placeholders are
provided in the layout.
To increase the current in any given phase, make R
SW
for this
phase larger (make R
SW
= 0 for the hottest phase, and do not
change during balancing). Increasing R
SW
to only 500 makes
a substantial increase in phase current. Increase each R
SW
value
by small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi-
nation voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor (R
B
) and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through R
B
B
B
is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect
to the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current-limit latch-off
time. In UVLO, or when EN is a logic low, the DELAY pin is held
at ground. After the UVLO threshold is reached and EN is a logic
high, the DELAY capacitor is charged with an internal 20 A
current source. The output voltage follows the ramping voltage on
the DELAY pin, limiting the inrush current. The soft start time
depends on the value of the VID DAC and C
DLY
, with a secondary
effect from R
DLY
. Refer to the Application Information section for
detailed information on setting C
DLY
.
If EN is taken low or if VCC drops below UVLO, the DELAY
capacitor is reset to ground to be ready for another soft start
cycle. Figure 7 shows a typical soft start sequence for the
ADP3190/ADP3190A.
ADP3190
Rev. 0 | Page 10 of 28
05
38
4-
0
08
Figure 7. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3190/ADP3190A compare a programmable current-
limit setpoint to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current-limit threshold of
10.4 mV/A. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops below
1.8 V. The current-limit latch-off delay time is, therefore, set by the
RC time constant discharging from 3 V to 1.8 V. The Application
Information section discusses the selection of C
DLY
and R
DLY
.
Because the controller continues to cycle the phases during the
latch-off delay time, the controller returns to normal operation
if the short is removed before the 1.8 V threshold is reached.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft start cycle is initiated.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3190/ADP3190A or by pulling the
EN pin low for a short time. To disable the short-circuit latch-
off function, the external resistor to ground should be left open,
and a high value (>1 M) resistor should be connected from
DELAY to VCC.
This prevents the DELAY capacitor from discharging, so the
1.8 V threshold is never reached. The resistor has an impact on
the soft start time because the current through it adds to the
internal 20 A current source.
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
An inherent per phase current limit protects individual phases,
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal
mode COMP voltage.
0
53
84
-
00
9
Figure 8. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3190/ADP3190A have the ability to dynamically
change the VID input while the controller is running. This
allows the output voltage to change while the supply is running
and supplying current to the load. This is commonly referred to
as VID on-the-fly (OTF). A VID OTF can occur under either
light or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from the
start code to the finish code. This change can be positive or
negative.
When a VID input changes state, the ADP3190/ADP3190A
detect the change and ignore the DAC inputs for a minimum of
400 ns. This time prevents a false code due to logic skew while
the six VID inputs are changing. Additionally, the first VID
change initiates the PWRGD and crowbar blanking functions
for a minimum of 100 s to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.
ADP3190
Rev. 0 | Page 11 of 28
Table 4. VID Codes for the ADP3190/ADP3190A
VID4 VID3 VID2 VID1 VID0 VID5 Output
1 1 1 1 1 1 No
CPU
1 1 1 1 1 0 No
CPU
0 1 0 1 0 0 0.8375
V
0 1 0 0 1 1 0.8500
V
0 1 0 0 1 0 0.8625
V
0 1 0 0 0 1 0.8750
V
0 1 0 0 0 0 0.8875
V
0 0 1 1 1 1 0.9000
V
0 0 1 1 1 0 0.9125
V
0 0 1 1 0 1 0.9250
V
0 0 1 1 0 0 0.9375
V
0 0 1 0 1 1 0.9500
V
0 0 1 0 1 0 0.9625
V
0 0 1 0 0 1 0.9750
V
0 0 1 0 0 0 0.9875
V
0 0 0 1 1 1 1.0000
V
0 0 0 1 1 0 1.0125
V
0 0 0 1 0 1 1.0250
V
0 0 0 1 0 0 1.0375
V
0 0 0 0 1 1 1.0500
V
0 0 0 0 1 0 1.0625
V
0 0 0 0 0 1 1.0750
V
0 0 0 0 0 0 1.0875
V
1 1 1 1 0 1 1.1000
V
1 1 1 1 0 0 1.1125
V
1 1 1 0 1 1 1.1250
V
1 1 1 0 1 0 1.1375
V
1 1 1 0 0 1 1.1500
V
1 1 1 0 0 0 1.1625
V
1 1 0 1 1 1 1.1750
V
1 1 0 1 1 0 1.1875
V
1 1 0 1 0 1 1.2000
V
VID4 VID3 VID2 VID1 VID0 VID5 Output
1 1 0 1 0 0 1.2125
V
1 1 0 0 1 1 1.2250
V
1 1 0 0 1 0 1.2375
V
1 1 0 0 0 1 1.2500
V
1 1 0 0 0 0 1.2625
V
1 0 1 1 1 1 1.2750
V
1 0 1 1 1 0 1.2875
V
1 0 1 1 0 1 1.3000
V
1 0 1 1 0 0 1.3125
V
1 0 1 0 1 1 1.3250
V
1 0 1 0 1 0 1.3375
V
1 0 1 0 0 1 1.3500
V
1 0 1 0 0 0 1.3625
V
1 0 0 1 1 1 1.3750
V
1 0 0 1 1 0 1.3875
V
1 0 0 1 0 1 1.4000
V
1 0 0 1 0 0 1.4125
V
1 0 0 0 1 1 1.4250
V
1 0 0 0 1 0 1.4375
V
1 0 0 0 0 1 1.4500
V
1 0 0 0 0 0 1.4625
V
0 1 1 1 1 1 1.4750
V
0 1 1 1 1 0 1.4875
V
0 1 1 1 0 1 1.5000
V
0 1 1 1 0 0 1.5125
V
0 1 1 0 1 1 1.5250
V
0 1 1 0 1 0 1.5375
V
0 1 1 0 0 1 1.5500
V
0 1 1 0 0 0 1.5625
V
0 1 0 1 1 1 1.5750
V
0 1 0 1 1 0 1.5875
V
0 1 0 1 0 1 1.6000
V
ADP3190
Rev. 0 | Page 12 of 28
POWER GOOD MONITORING
The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in
Table 4
. These limits are based on the VID voltage setting.
PWRGD goes low if the output voltage is outside of this
specified range, if all of the VID DAC inputs are high, or
whenever the EN pin is pulled low. PWRGD is blanked during
a VID OTF event for a period of 250 s to prevent false signals
during the time the output is changing.
The PWRGD circuitry also incorporates an initial turn-on
delay time based on the DELAY ramp. The PWRGD pin is held
low until the DELAY pin reaches 2.6 V. The time between when
the PWRGD undervoltage threshold is reached and when the
DELAY pin reaches 2.6 V provides the turn-on delay time. This
time is incorporated into the soft start ramp. To ensure a 1 ms
delay time on PWRGD, the soft start ramp must also be >1 ms.
Refer to the Application Information section for detailed
information on setting C
DLY
.
OUTPUT CROWBAR
As part of the protection for the load and output components
of the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 550 mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from being destroyed.
OUTPUT ENABLE AND UVLO
For the ADP3190/ADP3190A to begin switching, the input
supply (VCC) to the controller must be higher than the UVLO
threshold, and the EN pin must be higher than its logic threshold.
If UVLO is less than the threshold or the EN pin is a logic low, the
ADP3190/ADP3190A are disabled. This holds the PWM outputs
at ground, shorts the DELAY capacitor to ground, and holds the
ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
to the OD pins of the
ADP3120A
drivers. The ILIMIT being
grounded disables the drivers, so that both the DRVH and DRVL
are grounded. This feature is important in preventing the dis-
charge of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated during output due to the high current discharge of
the output capacitors through the inductors.
ADP3190
Rev. 0 | Page 13 of 28
V
IN
12V
V
IN
RT
N
EN
A
B
LE
PO
W
E
R
GOOD
R
LI
M
15
0k
1%
R
PH
4
158
k
1%
FROM
CP
U
R2
357k
1%
R
1k
Q3
NT
D
1
1
0
N
0
2
Q1
NT
D4
0N03
Q7
NT
D
1
10N
0
2
Q5
NT
D4
0N03
Q1
1
NT
D
1
10
N02
Q9
NT
D4
0N03
Q4
N
T
D1
10N
02
C
DL
Y
39n
F
V
CC(
C
O
RE
)
0.
83
75V
1.
6
V
95
A
T
D
C
,
1
19
A
P
K
V
CC(
C
O
RE
)
RTN
560
F
/
4V
8
SA
N
YO
SE
PC
S
ER
IES
5m
EACH
L2
320
n
H
/
1.
4m
L1
370
n
H
18
A
C
0.
1
F
C1
R
T
13
0k
1%
C1
0
10n
F
C2
2
C3
1
L3
320n
H
/
1.
4m
U3
A
D
P
312
0A
1
2
3
8
7
6
4
5
DR
V
H
SW
PG
N
D
DR
V
L
C9
4.
7
F
D2
1N
4148
D3
1N
4148
D4
1N
4148
C6
10n
F
C5
4.
7
F
C7
4.
7
F
C1
1
4.
7
F
U2
A
D
P
312
0A
1
2
3
8
7
6
4
5
BS
T
IN
OD
VC
C
DR
V
H
SW
PG
N
D
DR
V
L
VI
D4
VI
D3
VI
D2
VI
D1
VI
D0
VI
D5
FB
R
T
N
FB
CO
M
P
PW
RG
D
EN
DEL
A
Y
RT
RA
M
P
ADJ
VCC
PW
M
1
PW
M
2
PW
M
3
PW
M
4
SW
1
SW
2
SW
3
SW
4
GN
D
CS
CO
M
P
CSS
U
M
CSRE
F
I
L
IMIT
3
1
4
5
26
25
24
2
28
27
6
10
14
7
8
9
19
22
21
20
23
11
12
13
15
18
17
16
U1
A
D
P
3190
C14
10n
F
L4
320n
H
/
1.
4
m
U4
A
D
P
312
0A
1
2
3
8
7
6
4
5
DR
V
H
SW
PG
N
D
DR
V
L
C13
4.
7
F
C4
1
F
C3
10
0
F
(O
P
T
I
O
N
A
L
)
R
A
12
.
1
k
C
FB
22p
F
C
A
470p
F
C
CS
1
560p
F
C
CS
2
1.
5n
F
C2
27
00
F
/
1
6V
/
3.
3 A
2
SA
N
YO
MV
-WX SE
R
I
E
S
+
+
1
0
F
1
8
MLC
C
IN
SO
C
K
ET
RT
H1
100
k
, 5
%
NT
C
C8
15
n
F
R3
2.
2
C1
2
15
n
F
R4
2.
2
C2
0
15
n
F
R6
2.
2
C1
6
15
n
F
R5
2.
2
R
10
R
10
R
10
R
10
D1
1N4
1
48
R
B
1.
21k
R
CS
1
35
.
7
k
C
B
47
0
p
F
R
PH
3
158
k
1%
R
PH
2
158
k
1%
R
PH
1
158k
1%
R
DL
Y
4
70k
Q1
2
NT
D
1
10N02
Q1
0
NT
D4
0N03
Q6
NT
D40N
03
Q2
NT
D40
N
03
Q1
4
NT
D4
0N03
Q1
5
NT
D
1
1
0
N0
2
Q1
3
NT
D40
N
03
D5
1
N
4148
C19
4.
7
F
C15
4.
7
F
C1
8
10n
F
L5
320n
H
/
1.
4m
U5
A
D
P
312
0A
1
2
3
8
7
6
4
5
DR
V
H
SW
PG
N
D
DR
V
L
C1
7
4.
7
F
Q1
6
NT
D
1
1
0
N0
2
Q8
NT
D
1
10N0
2
R
SW
1
1
R
SW
2
1
R
SW
3
1
R
SW
4
1
+
+
R
CS
2
8
4.
5
k
C2
1
10
0p
F
05384-
010
+
BS
T
IN
OD
VC
C
BS
T
IN
OD
VC
C
BS
T
IN
OD
VC
C
1
FOR A DESCRIPTION OF OPTIONAL R
SW
RESISTORS, SEE THE THEORY OF OPERATION SECTION.
240
RA
M
P
A
DJ
RA
M
P
A
DJ
R7
10
C2
3
10
n
F
C2
2
1n
F
Figure 9. Typical VR101 Applications Schematic (ADP3190 Only; See Figure 18 for ADP3190A Connections)
ADP3190
Rev. 0 | Page 14 of 28
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10.1-compliant
CPU application are as follows:
Input voltage (V
IN
) = 12 V
VID setting voltage (V
VID
) = 1.300 V
Duty cycle (D) = 0.108
Nominal output voltage at no load (V
ONL
) = 1.281 V
Nominal output voltage at 101 A load (V
OFL
) = 1.180 V
Static output voltage drop based on a 1.0 m load line (R
O
)
from no load to full load (V
D
) = V
ONL
- V
OFL
=
1.281 V - 1.180 V = 101 mV
Maximum output current (I
O
) = 119 A
Maximum output current step (I
O
) = 95 A
Number of phases (n) = 4
Switching frequency per phase (f
SW
) = 330 kHz
SETTING THE CLOCK FREQUENCY
The ADP3190/ADP3190A use a fixed-frequency control
architecture. The frequency is set by an external timing resistor
(R
T
). The clock frequency and the number of phases determine
the switching frequency per phase, which relates directly to
switching losses and the sizes of the inductors and/or the input
and output capacitors. With n = 4 for four phases, a clock
frequency of 1.32 MHz sets the switching frequency (f
SW
) of
each phase to 330 kHz, which represents a practical trade-off
between the switching losses and the sizes of the output filter
components. Figure 3 shows that to achieve 1.32 MHz oscillator
frequency, the correct value for R
T
is 130 k. Alternatively, the
value for R
T
can be calculated using
-
=
k
31
pF
7
.
4
1
SW
T
f
n
R
(1)
where 4.7 pF and 31 k are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended.
SOFT START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
Because the soft start and current-limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C
DLY
for the soft start ramp. This
ramp is generated with a 20 A internal current source. The
value of R
DLY
has a second-order impact on the soft start time
because it sinks part of the current source to ground.
However, as long as R
DLY
is kept greater than 200 k, this effect
is minor. The value for C
DLY
can be approximated using
VID
SS
DLY
VID
DLY
V
t
R
V
C
-
=
2
A
20
(2)
where t
SS
is the desired soft start time. Assuming an R
DLY
of
390 k and a desired soft start time of 3 ms, C
DLY
is 36 nF.
The closest standard value for C
DLY
is 39 nF. Once C
DLY
is
chosen, R
DLY
can be calculated for the current-limit latch-off
time using
DLY
DELAY
DLY
C
t
R
=
96
.
1
(3)
If the result for R
DLY
is less than 200 k, a smaller soft start time
should be considered by recalculating the equation for C
DLY
, or
a longer latch-off time should be used. R
DLY
should never be less
than 200 k. In this example, a delay time of 9 ms results in
R
DLY
= 452 k. The closest standard 5% value is 470 k.
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs; but it allows using smaller inductors
and, for a specified peak-to-peak transient deviation, less total
output capacitance.
Conversely, a higher inductance means lower ripple current and
reduced conduction losses but requires larger inductors and
more output capacitance for the same peak-to-peak transient
deviation. In any multiphase converter, a practical value for the
peak-to-peak inductor ripple current is less than 50% of the
maximum dc current in the same inductor. Equation 4 shows the
relationship between the inductance, oscillator frequency, and
peak-to-peak ripple current in the inductor.
(
)
L
f
D
V
I
SW
VID
R
-
=
1
(4)
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
(
)
(
)
RIPPLE
SW
O
VID
V
f
D
n
R
V
L
-
1
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
(
)
nH
224
mV
10
kHz
330
0.432
1
m
1.0
V
1.3
=
-
L
If the resulting ripple voltage is less than it was designed
for, make the inductor smaller until the ripple value is met.
This allows optimal transient response and minimum output
decoupling.
ADP3190
Rev. 0 | Page 15 of 28
The smallest possible inductor should be used to minimize
the number of output capacitors. For this example, choosing a
320 nH inductor is a good starting point and gives a calculated
ripple current of 11 A. The inductor should not saturate at the
peak current of 35.5 A and should be able to handle the sum of
the power dissipation caused by the average current of 30 A in
the winding and core loss.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
can cause excessive power losses, while too small a value can
lead to increased measurement error. A good rule is to have the
DCR be about 1 to 1 times the droop resistance (R
O
). For this
design, an inductor with a DCR of 1.4 m is used.
DESIGNING AN INDUCTOR
Once the inductance and DCR are known, the next step is
either to design an inductor or to find a standard inductor that
comes as close as possible to meeting the overall design goals.
It is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 15% inductance
and 8% DCR (at room temperature) are reasonable tolerances
most manufacturers can meet.
The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss at
high frequencies include the powder cores (for example, Kool-
M from Magnetics, Inc. or from Micrometals) and the gapped
soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low
frequency powdered iron cores should be avoided due to their
high core loss, especially when the inductor value is relatively
low and the ripple current is high.
The best choice for a core geometry is a closed-loop type such
as a potentiometer core, PQ, U, or E core or toroid. A good
compromise between price and performance is a core with a
toroidal shape.
Many useful magnetics design references are available for
quickly designing a power inductor, such as
Magnetic Designer Software
Intusoft (www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-
DC Converters, by William T. McLyman, KG Magnetics,
Inc., ISBN 1883107008
Selecting a Standard Inductor
The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request:
Coilcraft
www.coilcraft.com
Coiltronics
www.coiltronics.com
Sumida Electric Company
www.sumida.com
Vishay Intertechnology
www.vishay.com
OUTPUT DROOP RESISTANCE
The design requires the regulator output voltage measured at
the CPU pins to drop when the output current increases. The
specified voltage drop corresponds to a dc output resistance (R
O
).
The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with R
PH(X)
(summers), R
CS,
and C
CS
(filter). The output resistance of the
regulator is set by the following equations, where R
L
is the DCR
of the output inductors:
( )
L
x
PH
CS
O
R
R
R
R
=
(6)
CS
L
CS
R
R
L
C
=
(7)
The user has the flexibility of choosing either R
CS
or R
PH(X)
. It is
best to select R
CS
equal to 100 k, and then solve for R
PH(X)
by
rearranging Equation 6.
( )
( )
k
140
k
100
m
0
.
1
m
4
.
1
=
=
=
x
PH
CS
O
L
x
PH
R
R
R
R
R
Next, use Equation 6 to solve for C
CS
.
nF
8
2
.
2
k
100
m
4
.
1
nH
320
=
=
CS
C
It is best to have a dual location for C
CS
in the layout, so that
standard values can be used in parallel to get as close as possible
to the value desired. For accuracy, C
CS
should be a 5% or 10%
NPO capacitor. This example uses a 5% combination for C
CS
of
1.5 nF and 560 pF in parallel. Recalculating R
CS
and R
PH(X)
using
this capacitor combination yields 110 k and 154 k. The
closest standard 1% value for R
PH(X)
is 158 k.
ADP3190
Rev. 0 | Page 16 of 28
INDUCTOR DCR TEMPERATURE CORRECTION
With the inductor's DCR being used as the sense element and
copper wire being the source of the DCR, compensation is
needed for temperature changes of the inductor's winding.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/C.
If R
CS
is designed to have an opposite and equal percentage
change in resistance to that of the wire, it cancels the tempera-
ture variation of the inductor's DCR. Due to the nonlinear
nature of NTC thermistors, Resistor R
CS1
and Resistor R
CS2
are
needed. See Figure 10 to linearize the NTC and produce the
desired temperature tracking.
CSSUM
CSCOMP
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
OR LOW-SIDE MOSFET
CSREF
ADP3190
CCS1
CCS2
RCS1
RTH
RCS2
KEEP THIS PATH
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
TO
SWITCH
NODES
TO
VOUT
SENSE
RPH1
RPH3
RPH2
05384-
0
1
1
18
17
16
Figure 10. Temperature Compensation Circuit Values
The following procedure and expressions yield values to use for
R
CS1
, R
CS2
, and R
TH
(the thermistor value at 25C) for a given R
CS
value.
1.
Select an NTC based on type and value. Because there isn't
a value yet, start with a thermistor with a value close to R
CS
.
The NTC should also have an initial tolerance of better
than 5%.
2.
Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well are
50C and 90C. These resistance values are called A
(R
TH(50C)
/R
TH(25C)
) and B (R
TH(90C)
/R
TH(25C)
). The NTC's
relative value is always 1 at 25C.
3.
Find the relative values of R
CS
required for each of these
temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/C. These
are called r
1
(1/(1 + TC (T
1
- 25))) and r
2
(1/(1 + TC
(T
2
- 25))), where TC = 0.0039 for copper. T
1
= 50C and
T
2
= 90C are chosen. From this, calculate that r
1
= 0.9112
and r
2
= 0.7978.
4.
Compute the relative values for R
CS1
, R
CS2
, and R
TH
using
(
)
(
)
(
)
(
)
(
)
(
)
B
A
r
A
B
r
B
A
r
A
B
r
B
A
r
r
B
A
R
2
1
1
2
2
1
CS2
-
-
-
-
-
-
+
-
-
-
=
1
1
1
1
(
)
CS2
1
CS2
CS1
R
r
A
R
A
R
-
-
-
-
=
1
1
1
CS1
CS2
TH
R
R
R
1
1
1
1
-
-
=
(8)
5.
Calculate R
TH
= r
TH
R
CS
, then select the closest value of
thermistor available. Also, compute a scaling factor k
based on the ratio of the actual thermistor value used
relative to the computed one:
(
)
(
)
CALCULATED
TH
ACTUAL
TH
R
R
k =
(9)
6.
Calculate values for R
CS1
and R
CS2
using Equation 10:
CS1
CS
CS1
R
k
R
R
=
(
)
(
)
(
)
CS2
CS
CS2
R
k
k
R
R
+
-
=
1
(10)
For this example, R
CS
has been calculated to be 110 k.
Start with a thermistor value of 100 k. Next, look
through the available 0603-size thermistors, and find
a Vishay NTHS0603N01N1003JR NTC thermistor
with A = 0.3602 and B = 0.09174. From these, compute
R
CS1
= 0.3795, R
CS2
= 0.7195, and R
TH
= 1.075. Solve for R
TH
,
which yields 118.28 k. Then, choose 100 k, which
makes k = 0.8455. Finally, R
CS1
and R
CS2
are 35.3 k
and 83.9 k. Choose the closest 1% resistor values,
which yields a choice of 35.7 k or 84.5 k.
OUTPUT OFFSET
The Intel specification requires that at no load should the
nominal output voltage of the regulator be offset to a value
lower than the nominal voltage corresponding to the VID code.
The offset is set by a constant current source flowing out of the
FB pin (I
FB
) and flowing through R
B
. The value of R
B
B
can be
found using Equation 11:
FB
ONL
VID
B
I
V
V
R
-
=
k
22
.
1
A
5
.
15
V
281
.
1
V
3
.
1
=
-
=
B
R
(11)
The closest standard 1% resistor value is 1.21 k.
ADP3190
Rev. 0 | Page 17 of 28
C
OUT
SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Also, to determine what is required, use some simple design
guidelines that are based on having both bulk and ceramic
capacitors in the system.
The first thing is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to be
used. The best location for ceramic capacitors is inside the
socket, with 12 to 18 of Size 1206 being the physical limit.
Additional ceramic capacitors can be placed along the outer
edge of the socket as well.
Combined ceramic values of 200 F to 300 F are recommended,
usually made up of multiple 10 F or 22 F capacitors. Select
the number of ceramic capacitors, and find the total ceramic
capacitance (C
Z
).
Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
X
) when considering the VID on-the-fly
voltage stepping of the output (Voltage Step V
V
in Time t
V
with
error of V
ERR
). A lower limit is based on meeting the capaci-
tance for load release for a given maximum load step, I
O
, and
a maximum allowable overshoot. The total amount of load
release voltage is given as
V
O
=
I
O
R
O
+
V
rl
, where
V
rl
is the maximum allowable overshoot voltage.
(
)
-
+
z
VID
O
rl
O
O
MIN
x
C
V
I
V
R
n
I
L
C
(12)
(
)
MAX
x
C
z
O
V
VID
v
VID
V
2
O
2
C
L
nKR
V
V
t
V
V
R
nK
L
-
-
+
1
1
2
(13)
=
V
ERR
V
V
n
K 1
where
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (R
X
) should be less
than two times the droop resistance (R
O
). If the C
X(MIN)
is larger
than C
X(MAX)
, the system cannot meet the VID on-the-fly speci-
fication and may require the use of a smaller inductor or more
phases (and may need the switching frequency to increase to
keep the output ripple the same).
This example uses 18, 10 F 1206 MLC capacitors (C
Z
= 180 F).
The VID on-the-fly step change is 450 mV in 230 s with a
settling error of 2.5 mV. The maximum allowable load release
overshoot for this example is 50 mV, so solving for the bulk
capacitance yields
(
)
mF
65
.
3
F
180
V
3
.
1
A
95
mV
50
m
0
.
1
4
A
95
nH
320
=
-
+
MIN
x
C
(
)
(
)
V
3
.
1
m
0
.
1
6
.
4
4
mV
450
nH
320
2
2
MAX
x
C
F
180
1
nH
320
mV
450
m
1.0
4.6
4
V
1.3
s
230
1
2
-
-
+
=
48.5 mF
where K = 4.6.
Using eight 560 F Al-Poly capacitors with a typical ESR
of 5 m each yields C
X
= 4.48 mF with an R
X
= 0.63 m.
One last check should be made to ensure that the ESL of the
bulk capacitors (L
X
) is low enough to limit the high frequency
ringing during a load change. This is tested using
(
)
pH
360
2
m
1
F
180
2
2
2
=
x
O
z
x
L
Q
R
C
L
(14)
where Q is limited to the square root of 2 to ensure a critically
damped system. In this example, L
X
is approximately 350 pH
for the eight A1-Polys capacitors, which satisfies this limitation.
If the L
X
of the chosen bulk capacitor bank is too large, the
number of ceramic capacitors may need to be increased if
there is excessive ringing.
For this multimode control technique, all ceramic designs can
be used as long as the conditions of Equation 11, Equation 12,
and Equation 13 are satisfied.
ADP3190
Rev. 0 | Page 18 of 28
POWER MOSFETS
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V
GS(TH)
, Q
G
, C
ISS
, C
RSS
, and R
DS(ON)
. The minimum gate drive
voltage (the supply voltage to the
ADP3120A
) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V
GATE
~10 V, logic-level threshold MOSFETs
(V
GS(TH)
< 2.5 V) are recommended.
The maximum output current (I
O
) determines the R
DS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3190/ADP3190A, currents are balanced between
phases, thus the current in each low-side MOSFET is the output
current divided by the total number of MOSFETs (n
SF
). With
conduction losses being dominant, the following expression
shows the total power being dissipated in each synchronous
MOSFET in terms of the ripple current per phase (I
R
) and
average total output current (I
O
):
(
)
( )
SF
DS
SF
R
SF
O
SF
R
n
I
n
n
I
D
P
+
-
=
2
2
12
1
1
(15)
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, it is possible to find
the required R
DS(ON)
for the MOSFET. For D-PAK MOSFETs up
to an ambient temperature of 50C, a safe limit for P
SF
is 1 W to
1.5 W at 120C junction temperature. Thus, for this example
(119 A maximum), R
DS(SF)
(per MOSFET) < 7.5 m. This R
DS(SF)
is also at a junction temperature of about 120C, so be certain to
account for this temperature when making this selection. This
example uses two lower-side MOSFETs at 4.8 m each at 120C.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the
ADP3120A
). The output impedance of the
driver is approximately 2 , and the typical MOSFET input gate
resistances are about 1 to 2 , so a total gate capacitance of
less than 6000 pF should be adhered to. Because there are two
MOSFETs in parallel, the input capacitance for each synchronous
MOSFET should be limited to 3000 pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off and to the
current and voltage that are being switched.
Basing the switching speed on the rise and fall time of the gate
driver impedance and MOSFET input capacitance, the follow-
ing expression provides an approximate value for the switching
loss per main MOSFET, where n
MF
is the total number of main
MOSFETs:
(
)
ISS
MF
G
MF
O
CC
SW
MF
S
C
n
n
R
n
I
V
f
P
= 2
(16)
where R
G
is the total gate resistance (2 for the
ADP3120A
and
about 1 for typical high speed switching MOSFETs, making
R
G
= 3 ), and C
ISS
is the input capacitance of the main MOSFET.
Adding more main MOSFETs (n
MF
) does not really help the
switching loss per MOSFET because the additional gate
capacitance slows switching. The best way to reduce switching
loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where R
DS(MF)
is the on resistance of the MOSFET:
(
)
(
)
MF
DS
MF
R
MF
MF
C
R
n
I
n
n
D
P
+
=
2
2
O
12
1
I
(17)
Typically, for main MOSFETs, the highest speed (low C
ISS
)
device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
For this example, an NTD40N03L was selected as the main
MOSFET (eight total; n
MF
= 8), with a C
ISS
= 584 pF (maximum)
and R
DS(MF)
= 19 m (maximum at T
J
= 120C). An NTD110N02L
was selected as the synchronous MOSFET (eight total; n
SF
= 8),
with C
ISS
= 2710 pF (maximum) and R
DS(SF)
= 4.8 m (maximum
at T
J
= 120C). The synchronous MOSFET C
ISS
is less than 3000 pF,
satisfying that requirement. Solving for the power dissipation per
MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each
synchronous MOSFET and 872 mW for each main MOSFET.
These numbers comply with the guideline to limit the power
dissipation to 1 W per MOSFET.
One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the Q
G
for the
MOSFETs and is given by the following equation, where Q
GMF
is
the total gate charge for each main MOSFET, and Q
GSF
is the
total gate charge for each synchronous MOSFET:
(
)
CC
CC
GSF
SF
GMF
MF
SW
DRV
V
I
Q
n
Q
n
n
f
P
+
+
=
2
(18)
Also shown is the standby dissipation factor (I
CC
V
CC
) for the
driver. For the
ADP3120A
, the maximum dissipation should be
less than 400 mW. In this example, with I
CC
= 7 mA, Q
GMF
=
5.8 nC, and Q
GSF
= 48 nC, 297 mW is found in each driver,
which is below the 400 mW dissipation limit. See the
ADP3120A
data sheet for more details.
ADP3190
Rev. 0 | Page 19 of 28
RAMP RESISTOR SELECTION
The ramp resistor (R
R
) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:
k
356
pF
5
m
2.4
5
3
nH
320
0.2
3
=
=
=
R
R
DS
D
R
R
R
C
R
A
L
A
R
(19)
where A
R
is the internal ramp amplifier gain, A
D
is the current
balancing amplifier gain, R
DS
is the total low-side MOSFET on
resistance, and C
R
is the internal ramp capacitor value. The
closest standard 1% resistor value is 357 k.
The internal ramp voltage magnitude can be calculated by using
(
)
(
)
V
m
390
kHz
330
pF
5
k
357
V
1.3
0.108
1
0.2
1
=
-
=
-
=
R
SW
R
R
VID
R
R
V
f
C
R
V
D
A
V
(20)
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves at the sacrifice of transient
response and stability. The factor of 3 in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage and
output voltage ramps. This ramp amplitude adds to the internal
ramp to produce the following overall ramp signal at the PWM
input:
(
)
-
-
=
O
X
SW
R
RT
R
C
f
n
D
n
V
V
1
2
1
(21)
In this example, the overall ramp signal is 0.49 V.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor value
for R
LIM
. The current-limit threshold for the ADP3190/ADP3190A
is set with a 3 V source (V
LIM
) across R
LIM
with a gain of
10.4 mV/A (A
LIM
). R
LIM
can be found using
O
LIM
LIM
LIM
LIM
R
I
V
A
R
=
(22)
For values of R
LIM
greater than 500 k, the current limit can be
lower than expected, so some adjustment of R
LIM
may be needed.
Here, I
LIM
is the average current limit for the output of the supply.
In this example, choosing a peak current limit of 200 A for I
LIM
results in R
LIM
= 156 k, for which 150 k is chosen as the
nearest 1% value.
The limit of the per-phase current limit described earlier is
determined by
(
)
(
)
2
R
MAX
DS
D
BIAS
R
MAX
COMP
PHLIM
I
R
A
V
V
V
I
+
-
-
(23)
For the ADP3190/ADP3190A, the maximum COMP voltage
(V
COMP(MAX)
) is 3.3 V, the COMP pin bias voltage (V
BIAS
) is 1.2 V,
and the current-balancing amplifier gain (A
D
) is 5. Using V
R
of
0.49 V and R
DS(MAX)
of 3 m (low-side on resistance at 150C),
calculate a per-phase peak current limit of 100 A. Although this
number may seem high, this current level can be reached only
with an absolute short at the output, and the current-limit latch-
off function shuts down the regulator before overheating can
occur.
This limit can be adjusted by changing the ramp voltage (V
R
),
but make sure not to set the per-phase limit lower than the
average per-phase current (I
LIM
/n).
The per-phase initial duty cycle limit is determined by
(
)
RT
BIAS
MAX
COMP
MAX
V
V
V
D
D
-
=
(24)
In this example, the maximum duty cycle is 0.46.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3190/ADP3190A allows
the best possible response of the regulator's output to a load
change. The basis for determining the optimum compensation
is to make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including dc, and equal to the droop
resistance (R
O
).
With the resistive output impedance, the output voltage droops
in proportion to the load current at any load current slew rate.
This ensures optimal positioning and allows minimization of
the output decoupling.
With the multimode feedback structure of the ADP3190/
ADP3190A, the feedback compensation must be set to make
the converter's output impedance, working in parallel with the
output decoupling, to meet this goal. Several poles and zeros
created by the output inductor and decoupling capacitors
(output filter) need to be compensated for.
ADP3190
Rev. 0 | Page 20 of 28
A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 25 to Equation 29
yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see
the Layout and Component Placement section).
The first step is to compute the time constants for all of the poles and zeros in the system
(
)
VID
O
X
RT
VID
RT
L
DS
D
O
E
V
R
C
n
V
D
n
L
V
V
R
R
A
R
n
R
-
+
+
+
=
1
2
(
)
m
24.2
V
1.3
m
1
mF
4.45
4
V
0.49
0.432
1
nH
320
2
V
1.3
V
0.49
m
1.4
m
2.4
5
m
1
4
=
-
+
+
+
=
E
R
(25)
(
)
(
)
s
2.50
m
10.63
m
0.65
m
1
m
1
pH
350
m
0.5
m
1
mF
4.45
=
-
+
-
=
-
+
-
=
X
O
O
X
O
X
A
R
R
R
R
L
R
R
C
T
(26)
(
)
(
)
ns
580
mF
4.45
m
1
m
0.5
m
0.63
=
-
+
=
-
+
=
X
O
X
B
C
R
R
R
T
(27)
s
4.7
m
24.2
V
1.3
kHz
330
2
m
2.4
5
nH
320
V
0.49
2
=
-
=
-
=
E
VID
SW
DS
D
RT
C
R
V
f
R
A
L
V
T
(28)
(
)
(
)
(
)
ns
333
m
1
F
180
m
0.5
m
1
mF
4.45
m
1
F
180
mF
4.45
'
2
2
=
+
-
=
+
-
=
O
Z
O
X
O
Z
X
D
R
C
R
R
C
R
C
C
T
(29)
where, for the ADP3190/ADP3190A, R' is the PCB resistance from the bulk capacitors to the ceramics and R
DS
is the total low-side
MOSFET on resistance per phase. In this example, A
D
is 5, V
RT
equals 0.49 V, R' is approximately 0.5 m (assuming a 4-layer, 1 ounce
motherboard), and L
X
is 350 pH for the eight Al-Poly capacitors.
The compensation values can then be solved using the following:
pF
342
k
1.21
m
24.2
s
2.50
m
1
4
=
=
=
A
B
E
A
O
A
C
R
R
T
R
n
C
(30)
k
13.7
pF
342
s
4.7
=
=
=
A
C
A
C
T
R
(31)
nF
479
k
1.21
ns
580
=
=
=
B
B
B
R
T
C
(32)
F
p
24.3
k
13.7
ns
333
=
=
=
A
D
FB
R
T
C
(33)
These are the starting values, prior to tuning the design, to account for layout and other parasitic effects (see the Layout and Component
Placement section).
The final values selected after tuning are
C
A
= 470 pF
R
A
= 12.1 k
C
B
= 470 pF
C
B
FB
= 22 pF
ADP3190
Rev. 0 | Page 21 of 28
Figure 11 and Figure 12
show the typical transient response
using these compensation values.
05
38
4-
01
2
Figure 11. Typical Transient Response
for Design Example Load Step
05
38
4-
0
13
Figure 12. Typical Transient Response
for Design Example Load Release
C
IN
SELECTION AND
INPUT CURRENT DI/DT REDUCTION
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n V
OUT
/V
IN
and an amplitude of one-nth the
maximum output current. To prevent large voltage transients,
a low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by
A
14.7
1
0.108
4
1
A
19
1
108
.
0
1
1
=
-
=
-
=
CRMS
O
CRMS
I
D
N
I
D
I
(34)
The capacitor manufacturer's ripple current ratings are often
based on only 2000 hours of life. This makes it advisable to
further derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors can be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2700 F, 16 V aluminum electrolytic capacitors and eight
4.7 F ceramic capacitors.
To reduce the input current di/dt to a level below the recom-
mended maximum of 0.1 A/s, an additional small inductor
(L > 370 nH at 18 A) should be inserted between the converter
and the supply bus. This inductor also acts as a filter between
the converter and the primary power source.
0
20
40
60
80
100
120
100
80
60
40
20
0
EF
F
I
C
I
E
N
C
Y
(
%
)
OUTPUT CURRENT (A)
V
OUT
= 1.3 V
T
A
= 25C
05
384
-
01
4
Figure 13. Efficiency of the Circuit of Figure 10 vs. Output Current
ADP3190
Rev. 0 | Page 22 of 28
TUNING THE ADP3190/ADP3190A
1.
Build a circuit based on the compensation values
computed from the design spreadsheet.
2.
Hook up the dc load to circuit, turn it on, and verify its
operation. Also, check for jitter at no load and full load.
DC Load Line Setting
3.
Measure the output voltage at no load (V
NL
). Verify it is
within tolerance.
4.
Measure the output voltage at full load cold (V
FLCOLD
). Let
the board sit for ~10 minutes at full load, and then measure
the output (V
FLHOT
). If there is a change of more than a few
millivolts, adjust R
CS1
and R
CS2
, using Equation 35 and
Equation 36.
(
)
(
)
FLHOT
NL
FLCOLD
NL
OLD
CS2
NEW
CS2
V
V
V
V
R
R
-
-
=
(35)
5.
Repeat Step 4 until the cold and hot voltage measurements
remain the same.
6.
Measure the output voltage from no load to full load, using
5 A steps. Compute the load line slope for each change, and
then average to get the overall load line slope (R
OMEAS
).
7.
If R
OMEAS
is off from R
O
by more than 0.05 m, use the
following to adjust the R
PH
values:
(
)
(
)
O
OMEAS
OLD
PH
NEW
PH
R
R
R
R
=
(36)
8.
Repeat Step 6 and Step 7 to check the load line, and repeat
adjustments if necessary.
9.
Once dc load line adjustment is complete, do not change
R
PH
, R
CS1
, R
CS2
, or R
TH
for the remainder of the procedure.
10.
Measure the output ripple at no load and full load with a
scope, and make sure it is within specifications.
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
C
25
C
25
C
25
C
25
1
1
-
-
-
+
+
=
TH
TH
OLD
CS1
NEW
CS2
OLD
CS1
TH
OLD
CS1
TH
OLD
CS1
NEW
CS1
R
R
R
R
R
R
R
R
R
R
(37)
ADP3190
Rev. 0 | Page 23 of 28
AC Load Line Setting
11.
Remove the dc load from the circuit and hook up the
dynamic load.
12.
Hook up the scope to the output voltage and set it to dc
coupling, with the time scale at 100 s/div.
13.
Set the dynamic load for a transient step of about 40 A at
1 kHz with a 50% duty cycle.
14.
Measure the output waveform (if not visible, use dc offset
on scope to view). Try to use a vertical scale of 100 mV/div
or finer. This waveform should look similar to Figure 14.
V
ACDRP
V
DCDRP
0
53
84
-
01
5
Figure 14. AC Load Line Waveform
15.
Use the horizontal cursors to measure V
ACDRP
and V
DCDRP
,
as shown. Do not measure the undershoot or overshoot that
happens immediately after this step.
If V
ACDRP
and V
DCDRP
are different by more than a few
millivolts, use Equation 38 to adjust C
CS.
It may be neces-
sary to parallel different values to get the correct one,
because there are limited standard capacitor values
available. It is a good idea to have locations for two
capacitors in the layout for this.
(
)
(
)
DCDRP
ACDRP
OLD
CS
NEW
CS
V
V
C
C
=
(38)
16.
Repeat Step 11 to Step 13, and repeat the adjustments, if
necessary. Once complete, do not change C
CS
for the
remainder of the procedure.
17.
Set the dynamic load step to maximum step size. Do not
use a step size larger than needed, and verify that the
output waveform is square, which means that V
ACDRP
and
V
DCDRP
are equal.
Initial Transient Setting
18.
With the dynamic load still set at the maximum step size,
expand the scope time scale to see 2 s/div to 5 s/div. The
waveform may have two overshoots and one minor under-
shoot (see Figure 15). Here, V
DROOP
is the final desired value.
05
38
4-
01
6
V
DROOP
V
TRAN1
V
TRAN2
Figure 15. Transient Setting Waveform
19.
If both overshoots are larger than desired, try making the
following adjustments:
Make the ramp resistor larger by 25% (R
RAMP
).
For V
TRAN1
, increase C
B
, or increase the switching
frequency.
B
For V
TRAN2
, increase R
A
, and decrease C
A
by 25%.
If these adjustments do not change the response, the output
decoupling is the limiting factor. Check the output response
every time a change is made, or nodes are switched, to
make sure the response remains stable.
20.
For load release (see Figure 16), if V
TRANREL
is larger than
V
TRAN1
(see Figure 15), there is not enough output capaci-
tance. Either more capacitance is needed or the inductor
values need to be smaller. If inductors are changed, start
the design again using the spreadsheet and this tuning
procedure.
V
DROOP
V
TRANREL
05
38
4-
0
17
Figure 16. Transient Setting Waveform
ADP3190
Rev. 0 | Page 24 of 28
Because the ADP3190/ADP3190A turn off all of the phases
(switches inductors to ground), there is no ripple voltage
present during load release. Thus, headroom does not need to
be added for ripple, allowing load release, V
TRANREL
, to be larger
than V
TRAN1
by the amount of ripple and still meet specifications.
If V
TRAN1
and V
TRANREL
are less than the desired final droop, this
implies that capacitors can be removed. When removing capaci-
tors, also check the output ripple voltage to make sure it is still
within specifications.
REPLACING THE ADP3188 WITH THE ADP3190
Figure 17 shows the changes needed when replacing an existing
ADP3188
design with the ADP3190. The shunt resistor needs
to be rated for W.
VIN
12V
V
IN
RTN
370nH
18A
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
COMP
PWRGD
EN
DELAY
RT
RAMPADJ
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
3
1
4
5
26
25
24
2
28
27
6
10
14
7
8
9
19
22
21
20
23
11
12
13
15
18
17
16
U1
ADP3190
1F
100F
2700F/16V/3.3 A 2
SANYO MV-WX SERIES
+
+
1N4148
+
240
1206
1/4W
ADP3190
0
538
4-
0
18
357k
1%
R
1k
C
0.1F
Figure 17. Replacing the ADP3188 with the ADP3190.
CHOOSING BETWEEN THE ADP3190
AND THE ADP3190A
For existing designs using the
ADP3188
, the ADP3190 is the
recommended replacement. For new designs, where 5 V system
voltage is available, it is recommended to use the ADP3190A, as
configured in Figure 18. For correct power sequencing, ensure
that the 12 V rail is present before the 5 V V
IN
is applied to the
ADP3190A.
V
IN
12V
V
IN
RTN
370nH
18A
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
COMP
PWRGD
EN
DELAY
RT
RAMPADJ
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
3
1
4
5
26
25
24
2
28
27
6
10
14
7
8
9
19
22
21
20
23
11
12
13
15
18
17
16
U1
ADP3190A
1F
100F
2700F/16V/3.3 A 2
SANYO MV-WX SERIES
+
+
+
10
0603
1/8W
V
IN
5V
357k
1%
0
5384-
0
19
R
1k
C
0.1F
Figure 18. Replacing the ADP3188 with the ADP3190A
ADP3190
Rev. 0 | Page 25 of 28
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal per-
formance of a switching regulator in a PC system.
GENERAL RECOMMENDATIONS
For good results, a PCB with at least four layers is
recommended. This allows the needed versatility for
control circuitry interconnections with optimal placement;
power planes for ground, input, and output power; and
wide interconnection traces in the remainder of the power
delivery current paths.
Note: Each square unit of 1 ounce copper trace has a
resistance of ~0.53 m at room temperature.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths. Then, the resistance and inductance
introduced by these current paths is minimized, and the
via current rating is not exceeded.
If critical signal lines, including the output voltage sense
lines of the ADP3190/ADP3190A, must cross through
power circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground noisier.
Use an analog ground plane around and under the
ADP3190/ADP3190A as a reference for the components
associated with the controller. This plane should be tied to
the nearest output decoupling capacitor ground and not tied
to any other power circuitry. This prevents power currents
from flowing in the ground plane.
Locate the components around the ADP3190/ADP3190A
close to the controller with short traces. The most
important traces to keep short, and away from other traces,
are the FB pin and the CSSUM pin. Connect the output
capacitors as close as possible to the load (or connector),
for example, a microprocessor core that receives the power.
If the load is distributed, the capacitors should also be
distributed and generally be in proportion to where the
load tends to be more dynamic.
Avoid crossing any signal lines over the switching power
path loop, as described in the Power Circuitry
Recommendations section.
POWER CIRCUITRY RECOMMENDATIONS
The switching power path should be routed on the PCB
to encompass the shortest possible length in order to
minimize radiated switching noise energy (that is, EMI)
and conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire
PC system as well as noise-related operational problems in
the power converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all
interconnecting PCB traces and planes. Using short and
wide interconnection traces is especially critical in this path
for two reasons: it minimizes the inductance in the switching
loop, which can cause high energy ringing; and it accom-
modates the high current demand with minimal voltage loss.
Whenever a power dissipating component, (for example,
a power MOSFET), is soldered to a PCB, the liberal use of
vias, both directly on the mounting pad and immediately
surrounding it, is recommended. This improves current
rating through the vias and also improves thermal
performance from vias extended to the opposite side of the
PCB, where a plane can more readily transfer the heat to the
air. Make a mirror image of any pad being used to heat-
sink the MOSFETs on the opposite side of the PCB to
achieve the best thermal dissipation to the air around the
board. To further improve thermal performance, use the
largest possible pad area.
The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.
For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.
SIGNAL CIRCUITRY RECOMMENDATIONS
The output voltage is sensed and regulated between the
FB pin and the FBRTN pin, which connect to the signal
ground at the load. To avoid differential-mode noise pickup in
the sensed signal, the loop area should be small. Thus, the
FB and FBRTN traces should be routed adjacent to each
other on top of the power ground plane back to the controller.
The feedback traces from the switch nodes should be
connected as close as possible to the inductor. The CSREF
signal should be connected to the output voltage at the
nearest inductor to the controller.
ADP3190
Rev. 0 | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AE
2 8
1 5
1 4
1
8
0
SEATING
PLANE
COPLANARITY
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19
0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
Figure 19. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-137-AF
28
15
14
1
PIN 1
SEATING
PLANE
8
0
0.012
0.008
0.025
BSC
0.010
0.004
COPLANARITY
0.004
0.065
0.049
0.069
0.053
0.010
0.006
0.050
0.016
0.394
0.390
0.386
0.158
0.154
0.150
0.244
0.236
0.228
Figure
20. 28-Lead Thin Shrink Small Outline Package [QSOP]
(RQ-28)
Dimensions show
n in inches
ORDERING GUIDE
Model Temperature
Range
Package
Description
Package Option
Ordering Quantity
ADP3190JRUZ-RL
1
0C to 85C
28-Lead TSSOP 13" Reel
RU-28
2500
ADP3190JRQZ-RL
1
0C to 85C
28-Lead QSOP 13" Reel
RQ-28
2500
ADP3190AJRUZ-RL
1
0C to 85C
28-Lead TSSOP 13" Reel
RU-28
2500
ADP3190AJRQZ-RL
1
0C to 85C
28-Lead QSOP 13" Reel
RQ-28
2500
1
Z = Pb-free part.
ADP3190
Rev. 0 | Page 27 of 28
NOTES
ADP3190
Rev. 0 | Page 28 of 28
T
NOTES
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05384-0-1/06(0)
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