Document Outline

FEATURES
APPLICATIONS
GENERAL DESCRIPTION
þÿ
þÿ
þÿ
þÿ
- ESD CAUTION
þÿ
þÿ
þÿ
- START-UP SEQUENCE
- PHASE DETECTION SEQUENCE
- MASTER CLOCK FREQUENCY
- OUTPUT VOLTAGE DIFFERENTIAL SENSING
- OUTPUT CURRENT SENSING
- ACTIVE IMPEDANCE CONTROL MODE
- CURRENT CONTROL MODE AND THERMAL BALANCE
- VOLTAGE CONTROL MODE
- DELAY TIMER
- SOFT START
- CURRENT LIMIT, SHORT CIRCUIT, AND LATCH-OFF PROTECTION
- DYNAMIC VID
- POWER GOOD MONITORING
- OUTPUT CROWBAR
- OUTPUT ENABLE AND UVLO
- THERMAL MONITORING
þÿ
- SETTING THE CLOCK FREQUENCY
- SOFT START DELAY TIME
- CURRENT LIMIT LATCH-OFF DELAY TIMES
- INDUCTOR SELECTION
- DESIGNING AN INDUCTOR
  - Selection a Standard Inductor
- CURRENT SENSE AMPLIFIER
- INDUCTOR DCR TEMPERATURE CORRECTION
- LOAD LINE SETTING
- OUTPUT OFFSET
- COUT SELECTION
- POWER MOSFETS
- RAMP RESISTOR SELECTION
- COMP PIN RAMP
- CURRENT LIMIT SETPOINT
- FEEDBACK LOOP COMPENSATION DESIGN
- CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION
- THERMAL MONITOR DESIGN
- TUNING THE ADP3189
  - DC Loadline Setting
  - AC Loadline Setting
  - Initial Transient Setting
- LAYOUT AND COMPONENT PLACEMENT
  - General Recommendations
  - Power Circuitry Recommendations
  - Signal Circuitry Recommendations
þÿ
- ORDERING GUIDE

8-Bit Programmable 2- to 5-Phase

Synchronous Buck Controller

ADP3189

FEATURES

Selectable 2-, 3-, 4-, or 5-phase operation at up

to 1 MHz per phase

±7.7 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to external

high-power drivers

Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly

VID code changes

Digitally programmable 0.5 V to 1.6 V output-- supports

both VR10.x and VR11 specifications

Programmable short-circuit protection with programmable

latch-off delay

APPLICATIONS

Desktop PC power supplies for

Next generation Intel® processors

VRM modules

GENERAL DESCRIPTION

The ADP3189

is a highly efficient multi-phase synchronous

buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between 0.5 V
and 1.6 V.

This device uses a multi-mode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
4-, or 5-phase operation, allowing for the construction of up to
five complementary buck switching stages.

The ADP3189 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current, so it is optimally positioned for a system transient.
The ADP3189 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.

ADP3189 is specified over the extended commercial tem-
perature range of 0°C to +85°C and is available in a
40-lead LFCSP package.

Protected by U.S. Patent Number 6,683,441; others pending.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

ADP3189

Rev. 0 | Page 2 of 36

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Test Circuits....................................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function DescriptionS ............................ 9

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 12

Start-Up Sequence...................................................................... 12

Phase Detection Sequence......................................................... 12

Master Clock Frequency............................................................ 13

Output Voltage Differential Sensing ........................................ 13

Output Current Sensing ............................................................ 13

Active Impedance Control Mode............................................. 13

Current Control Mode and Thermal Balance ........................ 13

Voltage Control Mode................................................................ 14

Delay Timer................................................................................. 14

Soft Start ...................................................................................... 14

Current Limit, Short Circuit, and Latch-Off Protection....... 15

Dynamic VID.............................................................................. 15

Power Good Monitoring ........................................................... 15

Output Crowbar ......................................................................... 16

Output Enable and UVLO ........................................................ 16

Thermal Monitoring .................................................................. 16

Application Information................................................................ 22

Setting the Clock Frequency ..................................................... 22

Soft Start Delay Time ................................................................. 22

Current Limit Latch-Off Delay Times..................................... 22

Inductor Selection ...................................................................... 23

Designing an Inductor............................................................... 23

Selecting a Standard Inductor .............................................. 23

Current Sense Amplifier............................................................ 24

Inductor DCR Temperature Correction ................................. 24

Load Line Setting........................................................................ 25

Output Offset .............................................................................. 26

OUT

Selection ............................................................................. 26

Power MOSFETs......................................................................... 27

Ramp Resistor Selection............................................................ 28

COMP Pin Ramp ....................................................................... 28

Current Limit SetPoint .............................................................. 29

Feedback Loop Compensation Design.................................... 29

Selection and Input Current di/dt Reduction.................. 31

Thermal Monitor Design .......................................................... 31

Tuning the ADP3189 ................................................................. 32

DC Loadline Setting .............................................................. 32

AC Loadline Setting............................................................... 33

Initial Transient Setting ......................................................... 33

Layout and Component Placement ......................................... 34

General Recommendations .................................................. 34

Power Circuitry Recommendations .................................... 34

Signal Circuitry Recommendations .................................... 34

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

7/05--Revision 0: Initial Version

ADP3189

Rev. 0 | Page 3 of 36

FUNCTIONAL BLOCK DIAGRAM

VCC

PRECISION

REFERENCE

DELAY

UVLO

SHUTDOWN

AND BIAS

OSCILLATOR

GND

ADP3189

VRHOT

VRFAN

TTSENSE

PWRGD

RAMPADJ

PWM2

LLSET

PWM3

PWM4

PWM5

SW1

CSREF

CSCOMP

SW2

SW3

SW5

SW4

CSSUM

VID4

VID3

VID2

VID1

VID0

VID6

VID7

VID5

COMP

DELAY

ILIMIT

VIDSEL

FBRTN

VID

DAC

DAC + 150mV

DAC 250mV

CSREF

CURRENT

LIMIT

CIRCUIT

CROWBAR

CURRENT
LIMIT

CMP

CURRENT

BALANCING

CIRCUIT

2-/3-/4-/5-PHASE

DRIVER LOGIC

SET

RESET

PWM1

05626-001

850mV

CMP

BOOT

VOLTAGE

& SOFT-START

CONTROL

THERMAL

THROTTLING

CONTROL

Figure 1.

ADP3189

Rev. 0 | Page 4 of 36

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, T

= 0°C to 85°C, unless otherwise noted.

Table 1.

Parameter Symbol

Conditions

Min

Typ

Max

Unit

ERROR

AMPLIFIER

Output Voltage Range

COMP

0.95

3.95 V

Accuracy V

Relative to nominal DAC output, referenced to
FBRTN,
LLSET = CSREF, Figure 2,

VIDSEL = GND,

-7.7

+7.7

VIDSEL = 1.25 V,
VID Range 1.00625 V to 1.60000 V

-7.7

+7.7 mV

FB(BOOT)

start-up

1.092 1.1

1.108 V

Load Line Positioning Accuracy

CSREF - LLSET = 80 mV

-78

-80

-82

Differential

Non-Linearity

-1

+1 LSB

Line Regulation

VCC = 10 V to 14 V

0.003

Input Bias Current

13.5 15 16.5 A

FBRTN Current

FBRTN

125

200

Output Current

COMP

FB forced to V

OUT

- 3%

500

Gain Bandwidth Product

GBW

(ERR)

COMP = FB

MHz

Slew Rate

COMP = FB

V/s

LLSET Input Voltage Range

LLSET

Relative to CSREF

-250

+250

LLSET Input Bias Current

LLSET

-120

+120 nA

BOOT Voltage Hold Time

BOOT

DELAY

= 10 nF

VID

INPUTS

Input Low Voltage

IL(VID)

VIDx,

VIDSEL

0.4 V

Input High Voltage

IH(VID)

VIDx,

VIDSEL

0.8

Max V

for VID on Fly

1.26

Input Current

IN(VID)

-1

VID Transition Delay Time

VID code change to FB change

200

No CPU Detection Turn-Off Delay

Time

VID code change to PWM going low

200

OSCILLATOR

Frequency Range

OSC

0.25

MHz

Frequency Variation

PHASE

= 25°C, R

= 243 k, 5-phase

180

200

220

kHz

= 25°C, R

= 113 k, 5-phase

400

kHz

= 25°C, R

= 51 k, 5-phase

800

kHz

Output Voltage

= 243 k to GND

1.6

1.7

1.8

RAMPADJ Output Voltage

RAMPADJ

-50

+50 mV

RAMPADJ Input Current Range

RAMPADJ

50 A

CURRENT SENSE AMPLIFIER

Offset Voltage

OS(CSA)

CSSUM - CSREF, Figure 3

-1.0

+1.0 mV

Input Bias Current

BIAS(CSSUM)

-50

+50 nA

Gain Bandwidth Product

GBW

(CSA)

CSSUM = CSCOMP

MHz

Slew Rate

CSCOMP

= 10 pF

V/s

Input Common-Mode Range

CSSUM and CSREF

Output Voltage Range

0.05

2.8

Output Current

CSCOMP

500

Current Limit Latch-Off Delay Time

OC(DELAY)

DELAY

= 10 nF

ADP3189

Rev. 0 | Page 5 of 36

Parameter Symbol

Conditions

Min

Typ

Max

Unit

CURRENT BALANCE AMPLIFIER

Common Mode Range

SW(X)CM

-600

+200 mV

Input Resistance

SW(X)

SWx = 0 V

Input Current

SW(X)

SWx = 0 V

2.5

4.0

5.5

Input Current Matching

SW(X)

SWx = 0 V

-5

CURRENT

LIMIT

COMPARATOR

Output Voltage

ILIMIT

= 143 k

1.6

1.7

1.8

Output Current

ILIMIT

= 143 k

Maximum Output Current

Current Limit Threshold Voltage

CSREF

- V

CSCOMP

, R

ILIMIT

= 143 k

105

120

135

Current Limit Setting Ratio

ILIMIT

mV/A

DELAY

TIMER

Normal Mode Output Current

DELAY

12 15 18 A

Output Current in Current Limit

DELAY(CL)

3.0 3.75

4.5 A

Threshold Voltage

DELAY(TH)

1.6 1.7 1.8 V

SOFT

START

Output Current

During

start-up

12 15 18 A

ENABLE

INPUT

Threshold Voltage

TH(EN)

800 850 900 mV

Hysteresis V

HYS(EN)

80 100 120 mV

Input Current

IN(EN)

-1

+1 A

Delay Time

DELAY(EN)

EN > 950 mV, C

DELAY

= 10 nF

OD OUTPUT

Output Low Voltage

OL(

)

100

500

Output High Voltage

OH(

)

4 5

THERMAL

THROTTLING

CONTROL

TTSENSE Voltage Range

Internally limited

5.3

TTSENSE VRFAN Threshold Voltage

1.08

1.11

1.14

TTSENSE VRHOT Threshold Voltage

780

810

840

TTSENSE

Hysteresis

TTSENSE Input Current

-105

-120

-135

VRFAN Output Low Voltage

OL(VRFAN)

VRFAN (SINK)

= -4 mA

150

300

VRHOT Output Low Voltage

OL(VRHOT)

VRHOT (SINK)

= -4 mA

150

300

POWER GOOD COMPARATOR

Undervoltage Threshold

PWRGD(UV)

Relative to nominal DAC output

-200

-250

-300

Overvoltage Threshold

PWRGD(OV)

Relative to nominal DAC output

100

150

200

Output Low Voltage

OL(PWRGD)

PWRGD(SINK)

= -4 mA

150

300

Power Good Delay Time

During Soft Start

DELAY

= 10 nF

VID Code Changing

100

400

VID Code Static

200

Crowbar Trip Point

CROWBAR

Relative to nominal DAC output

100

150

200

Crowbar Reset Point

Relative to FBRTN

320

375

430

Crowbar Delay Time

CROWBAR

Overvoltage to PWM going low

VID Code Changing

100

400

VID Code Static

400

PWM

OUTPUTS

Output Low Voltage

OL(PWM)

PWM(SINK)

= -400 A

160

500

Output High Voltage

OH(PWM)

PWM(SOURCE)

= 400 A

4.0

ADP3189

Rev. 0 | Page 8 of 36

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC

-0.3 V to +15 V

FBRTN

-0.3 V to +0.3 V

PWM3 to PWM5, RAMPADJ

-0.3 V to VCC + 0.3 V

SW1 to SW5

-5 V to +25 V

<200 ns

-10 V to +25 V

All Other Inputs and Outputs

-0.3 V to +5.5 V

Storage Temperature

-65°C to +150°C

Operating Ambient Temperature Range

0°C to +85°C

Operating Junction Temperature

125°C

Thermal Impedance (

)

100°C/W

Lead Temperature

Soldering (10 sec)

300°C

Infrared (15 sec)

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages re referenced to GND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADP3189

Rev. 0 | Page 9 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1
INDICATOR

PWGRD

FBRTN

COMP

DELAY

VRFAN

VRHOT

TTSENSE

PWM4

PWM3

PWM2

PWM1

PWM5

SW1

SW2

SW3

SW4

SW5

I
L

I
M

I
T

1
2

1
3

I
D

TOP VIEW

(Not to Scale)

ADP3189

I
D

3
7

3
8

3
2

3
9

4
0

I
D

05626-005

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD
output low.

PWRGD

Power Good Output. Open-drain output that signals when the output voltage is outside of the proper
operating range.

FBRTN

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.

5 COMP

Error

Amplifier

Output and Compensation Point.

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start
ramp-up time.

DELAY

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent
latch-off delay time, BOOT voltage hold time, EN delay time, and PWRGD delay time.

VRFAN

VR Fan Activation Output. Active high open drain output that signals when the temperature at the
monitoring point connected to TTSENSE exceeds the programmed VRFAN temperature threshold.

VRHOT

VR Hot Output. Active high open drain output that signals when the temperature at the monitoring point
connected to TTSENSE exceeds the programmed VRHOT temperature threshold.

TTSENSE

VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely
sense the temperature at the desired thermal monitoring point.

ILIMIT

Current Limit Set Point. An external resistor from this pin to GND sets the current limit threshold of the
converter.

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.

RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.

LLSET

Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected
to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables
positioning.

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.

CSCOMP

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of
the current sense amplifier and the positioning loop response time.

GND

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Output Disable Logic Output. This pin is actively pulled low when the ADP3189 EN input is low or when
VCC is below its UVLO threshold to signal to the Driver IC that the driver high-side and low-side outputs
should go low.

20 NC

Connect.

ADP3189

Rev. 0 | Page 12 of 36

THEORY OF OPERATION

The ADP3189 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, 4-, and
5-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
8-bit VRD/VRM 11- and 7-bit VRD/VRM 10x-compatible
CPUs. Multiphase operation is important for producing the
high currents and low voltages demanded by today's microproc-
essors. Handling the high currents in a single-phase converter
places high thermal demands on the components in the system,
such as the inductors and MOSFETs.

The multimode control of the ADP3189 ensures a stable,
high performance topology for the following:

Balancing currents and thermals between phases

High speed response at the lowest possible switching
frequency and output decoupling

Minimizing thermal switching losses by using lower
frequency operation

Tight load line regulation and accuracy

High current output from having up to 5-phase operation

Reduced output ripple due to multiphase cancellation

PC board layout noise immunity

Ease of use and design due to independent component
selection

Flexibility in operation for tailoring design to low cost or
high performance

START-UP SEQUENCE

The ADP3189 follows the VR11 start-up sequence shown in
Figure 8. After both the EN and UVLO conditions are met,
the DELAY pin goes through one cycle (TD1). After this cycle,
the internal oscillator is enabled. The first five clock cycles are
blanked from the PWM outputs and used for phase detection
as explained in the Phase Detection Sequence section. Then, the
soft start ramp is enabled (TD2), and the output comes up to the
boot voltage of 1.1 V. The boot hold time is determined by the
DELAY pin as it goes through a second cycle (TD3). During
TD3, the processor VID pins settle to the required VID code.
When TD3 is over, the ADP3189 soft starts either up or down to
the final VID voltage (TD4). After TD4 has been completed and
the PWRGD masking time (equal to VID on the fly masking) is
finished, a third ramp on the DELAY pin sets the PWRGD
blanking (TD5).

VTT I/O

(ADP3189 EN)

12V

SUPPLY

UVLO

THRESHOLD

0.85V

1.0V

DELAY

VCC_CORE

VR READY

(ADP3189 PWRGD)

CPU

VID INPUTS

VID INVALID

VID VALID

DELAY(TH)

(1.7V)

BOOT

(1.1V)

BOOT

(1.1V)

VID

TD1

TD2

TD4

TD5

TD3

05626-008

Figure 8. System Start-Up Sequence

PHASE DETECTION SEQUENCE

During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry moni-
toring the PWM outputs. Normally, the ADP3189 operates as
a 5-phase PWM controller. Connecting the PWM5 pin to VCC
programs a 4-phase operation, and connecting the PWM5 pin
and PWM4 pin to VCC programs a 3-phase operation. For
2-phase operation, connect PWM5, PWM4, and PWM3
to VCC.

Prior to soft start, while EN is low, the PWM3, PWM4, and
PWM5 pins sink approximately 100 A. An internal compara-
tor checks each pin's voltage vs. a threshold of 3.15 V. If the pin
is tied to VCC, it is above the threshold. Otherwise, an internal
current sink pulls the pin to GND, which is below the threshold.
PWM1 and PWM2 are low during the phase detection interval,
which occurs during the first five clock cycles of the internal
oscillator. After this time, if the remaining PWM outputs are
not pulled to VCC, the 100 A current sink is removed, and
they function as normal PWM outputs. If they are pulled to
VCC, the 100 A current source is removed, and the outputs
are put into a high-impedance state.

The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3120. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at the
same time to allow overlapping phases.

ADP3189

Rev. 0 | Page 13 of 36

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3189 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
all phases are in use, divide by 5. If PWM5 is tied to VCC, then
divide the master clock by 4 for the frequency of the remaining
phases. If PWM4 and PWM5 are tied to VCC, then divide by 3.
If PWM3, PWM4, and PWM5 are tied to VCC, then divide
by 2.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3189 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error ampli-
fier. This maintains a worst-case specification of ±7.7 mV
differential sensing error over its full operating output voltage
and temperature range. The output voltage is sensed between
the FB pin and FBRTN pin. FB should be connected through
a resistor to the regulation point, usually the remote sense pin
of the microprocessor. FBRTN should be connected directly
to the remote sense ground point. The internal VID DAC
and precision reference are referenced to FBRTN, which has
a minimal current of 125 A to allow accurate remote sensing.
The internal error amplifier compares the output of the DAC
to the FB pin to regulate the output voltage.

OUTPUT CURRENT SENSING

The ADP3189 provides a dedicated current-sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways, depending on
the objectives of the system, as follows:

Output inductor DCR sensing without a thermistor for
lowest cost.

Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature.

Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element, such as the switch node side of the output
inductors, to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor.

An additional resistor divider connected between CSREF and
CSCOMP, with the mid point connected to LLSET, can be used
to set the load line required by the microprocessor. The current
information is then given as CSREF LLSET. This difference
signal is used internally to offset the VID DAC for voltage
positioning. The difference between CSREF and CSCOMP
is then used as a differential input for the current-limit
comparator. This allows for the load line to be set independ-
ently of the current-limit threshold. In the event that the
current limit threshold and load line are not independent,
the resistor divider between CSREF and CSCOMP can be
removed and the CSCOMP pin can be directly connected
to LLSET. To disable voltage positioning entirely (that is,
no load line) connect LLSET to CSREF.

To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors, so that it can be made
extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the LLSET pin can be scaled to be equal to the droop imped-
ance of the regulator times the output current. This droop voltage
is then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input voltage
directly to tell the error amplifier where the output voltage should
be. This allows enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL
BALANCE

The ADP3189 has individual inputs (SW1 to SW5) for each
phase, which are used for monitoring the current of each phase.
This information is combined with an internal ramp to create
a current balancing feedback system that has been optimized
for initial current balance accuracy and dynamic thermal
balancing during operation. This current balance information
is independent of the average output current information used
for positioning as described in the Output Current Sensing
section.

The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply volt-
age for feed-forward control for changes in the supply. A resistor
connected from the power input voltage to the RAMPADJ pin
determines the slope of the internal PWM ramp. External
resistors can be placed in series with individual phases to
create an intentional current imbalance if desired, such as
when one phase has better cooling and can support higher
currents. Resistors R

SW1

through R

SW5

(see the Typical

Application Circuit in Figure 11) can be used for adjusting
thermal balance. It is best to have the ability to add these
resistors during the initial design, so ensure that placeholders
are provided in the layout.

ADP3189

Rev. 0 | Page 14 of 36

To increase the current in any given phase, enlarge R

for that

phase (make R

= 0 for the hottest phase and do not change

during balancing). Increasing R

to only 500 makes a

substantial increase in phase current. Increase each R

value

by small amounts to achieve balance, starting with the coolest
phase first.

VOLTAGE CONTROL MODE

A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4.

This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with
a resistor R

and is used for sensing and controlling the output

voltage at this point. A current source from the FB pin flowing
through R

is used for setting the no-load offset voltage from

the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.

DELAY TIMER

The delay times for the start-up timing sequence are set with
a capacitor from the DELAY pin to ground. In UVLO, or when
EN is logic low, the DELAY pin is held at ground. After the
UVLO and EN signals are asserted, the first delay time (TD1 in
Figure 8) is initiated. A 15 A current flows out of the DELAY
pin to charge C

DLY

. A comparator monitors the DELAY voltage

with a threshold of 1.7 V. The delay time is therefore set by the
15 A charging a capacitor from 0 V to 1.7 V. This DELAY pin
is used for multiple delay timings (TD1, TD3, and TD5) during
the start-up sequence. Also, DELAY is used for timing the
current limit latch off, as explained in the Current Limit, Short
Circuit, and Latch-Off Protection section.

SOFT START

The Soft Start times for the output voltage are set with a capacitor
from the SS pin to ground. After TD1 and the phase detection
cycle have been completed, the SS time (TD2 in Figure 8) starts.
The SS pin is disconnected from GND, and the capacitor is
charged up to the 1.1 V boot voltage by the SS amplifier, which
has a limited output current of 15 A. The voltage at the FB pin
follows the ramping voltage on the SS pin, limiting the inrush
current during start-up. The soft start time depends on the
value of the boot voltage and C

Once the SS voltage is within 100 mV of the boot voltage, the
boot voltage delay time (TD3) is started. The end of the boot
voltage delay time signals the beginning of the second soft start
time (TD4). The SS voltage now changes from the boot voltage
to the programmed VID DAC voltage (either higher or lower)
using the SS amplifier with the limited output current of 15 A.
The voltage of the FB pin follows the ramping voltage of the SS
pin, limiting the inrush current during the transition from the
boot voltage to the final DAC voltage. The second soft start
time depends on the boot voltage, the programmed VID DAC
voltage, and C

If either EN is taken low or VCC drops below UVLO, DELAY
and SS are reset to ground to be ready for another soft start
cycle. Figure 9 shows typical start-up waveforms for the
ADP3189.

05626-009

CH1

1.0V

CH2 1.0V

CH3

1.0V

CH4 10.0V

M2.00ms

A CH1 500V

22.0%

Figure 9. Typical Start-up Waveforms
Channel 1: CSREF, Channel 2: DELAY,

Channel 3: SS, Channel 4: Phase 1 Switch Node

ADP3189

Rev. 0 | Page 15 of 36

CURRENT LIMIT, SHORT CIRCUIT, AND LATCH-OFF
PROTECTION

The ADP3189 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During operation, the voltage
on ILIMIT is 1.7 V. The current through the external resistor is
internally scaled to give a current limit threshold of 10 mV/A.
If the difference in voltage between CSREF and CSCOMP rises
above the current limit threshold, the internal current limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.

If the limit is reached and TD5 has completed, a latch-off delay
time starts, and the controller shuts down if the fault is not
removed. The current limit delay time shares the DELAY pin
timing capacitor with the start-up sequence timing. However,
during current limit, the DELAY pin current is reduced to
3.75 A. A comparator monitors the DELAY voltage and shuts
off the controller when the voltage reaches 1.7 V. Therefore,
the current limit latch-off delay time is set by the current of
3.75 A, charging the delay capacitor from 0 V to 1.7 V. This
delay is four times longer than the delay time during the start-
up sequence.

The current limit delay time starts only after the TD5 has
completed. If there is a current limit during start-up, the
ADP3189 goes through TD1 to TD5, and then starts the latch-
off time. Because the controller continues to cycle the phases
during the latch-off delay time, if the short is removed before
the 1.7 V threshold is reached, the controller returns to normal
operation, and the DELAY capacitor is reset to GND.

The latch-off function can be reset by either removing and
reapplying the supply voltage to the ADP3189, or by toggling
the EN pin low for a short time. To disable the short circuit
latch-off function, an external resistor should be placed in
parallel with C

DLY

. This prevents the DELAY capacitor from

charging up to the 1.7 V threshold. The addition of this resistor
will cause a slight increase in the delay times.

During start-up, when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 1.5 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry. An inherent per-phase current limit protects
individual phases if one or more phases stop functioning
because of a faulty component. This limit is based on the
maximum normal mode COMP voltage. Typical overcurrent
latch-off waveforms are shown in Figure 10.

05626-010

CH1

1.0V

CH2 1.0V

CH3

1.0V

CH4 10.0V

M2.00ms

A CH1 500V

22.0%

Figure 10. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

DYNAMIC VID

The ADP3189 has the ability to dynamically change the VID
inputs while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID on-
the-fly (OTF). A VID OTF can occur under light or heavy load
conditions. The processor signals the controller by changing the
VID inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.

When a VID input changes state, the ADP3189 detects the
change and ignores the DAC inputs for a minimum of 200 ns.
This time prevents a false code due to logic skew while the eight
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and crowbar blanking functions for a
minimum of 100 s to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.

POWER GOOD MONITORING

The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level, when connected to a pull-up resistor, indicates that
the output voltage is within the nominal limits specified based
on the VID voltage setting. PWRGD goes low if the output
voltage is outside of this specified range, if the VID DAC inputs
are in no CPU mode, or whenever the EN pin is pulled low.
PWRGD is blanked during a VID OTF event for a period of
400 s to prevent false signals during the time the output is
changing.

ADP3189

Rev. 0 | Page 16 of 36

The PWRGD circuitry also incorporates an initial turn-on
delay time (TD5), based on the DELAY timer. Prior to the
SS voltage reaching the programmed VID DAC voltage and the
PWRGD masking time finishing, the PWRGD pin is held low.
Once the SS pin is within 100 mV of the programmed DAC
voltage, the capacitor on the DELAY pin begins to charge up.
A comparator monitors the DELAY voltage and enables
PWRGD when the voltage reaches 1.7 V. The PWRGD delay
time is, therefore, set by a current of 15 A, charging a capacitor
from 0 V to 1.7 V.

OUTPUT CROWBAR

As part of the protection for the load and output components
of the supply, the PWM outputs are driven low, turning on the
low-side MOSFETs, when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately
375 mV.

Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high-side MOSFET, this
action current-limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.

OUTPUT ENABLE AND UVLO

For the ADP3189 to begin switching, the input supply (VCC)
to the controller must be higher than the UVLO threshold,
and the EN pin must be higher than its 0.85 V threshold. This
initiates a system start up sequence. If either UVLO or EN is
less than their respective thresholds, the ADP3189 is disabled.
This holds the PWM outputs at ground, shorts the DELAY
capacitor to ground, and forces PWRGD and OD signals low.

In the application circuit, the OD pin should be connected to
the OD inputs of the ADP3120 driver. Grounding OD disables
the drivers such that both DRVH and DRVL are grounded. This
feature is important in preventing the discharge of the output
capacitors when the controller is shut off. If the driver outputs
were not disabled, a negative voltage can be generated during
output due to the high current discharge of the output
capacitors through the inductors.

THERMAL MONITORING

The ADP3189 includes a thermal monitoring circuit to detect
when a point on the VR has exceeded two different user-defined
temperatures. The thermal monitoring circuit requires an NTC
thermistor to be placed between TTSENSE and GND. A fixed
current of 120 A is sourced out of the TTSENSE pin and into
the thermistor. The current source is internally limited to 5 V.
An internal circuit compares the TTSENSE voltage to a 1.11 V
and a 0.81 V threshold, and outputs an open-drain signal at the
VRFAN and VRHOT outputs, respectively. Once the voltage on
the TTSENSE pin goes below its respective threshold, the open
drain outputs assert high to signal the system that an overtem-
perature event has occurred. Since the TTSENSE voltage changes
slowly with respect to time, 55 mV of hysteresis is built into these
comparators. The thermal monitoring circuitry does not depend
on EN and is active when UVLO is above its threshold. When
UVLO is below its threshold, VRFAN and VRHOT are
forced low.

ADP3189

Rev. 0 | Page 17 of 36

Table 4.VR11 and VR10.x VID Codes for the ADP3189

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

OFF 0 0 0 0 0 0 0 0 N/A

OFF 0 0 0 0 0 0 0 1 N/A

1.60000

0 0 0 0 0 0 1 0 0 1 0 1 0 1 1

1.59375

0 0 0 0 0 0 1 1 0 1 0 1 0 1 0

1.58750

0 0 0 0 0 1 0 0 0 1 0 1 1 0 1

1.58125

0 0 0 0 0 1 0 1 0 1 0 1 1 0 0

1.57500

0 0 0 0 0 1 1 0 0 1 0 1 1 1 1

1.56875

0 0 0 0 0 1 1 1 0 1 0 1 1 1 0

1.56250

0 0 0 0 1 0 0 0 0 1 1 0 0 0 1

1.55625

0 0 0 0 1 0 0 1 0 1 1 0 0 0 0

1.55000

0 0 0 0 1 0 1 0 0 1 1 0 0 1 1

1.54375

0 0 0 0 1 0 1 1 0 1 1 0 0 1 0

1.53750

0 0 0 0 1 1 0 0 0 1 1 0 1 0 1

1.53125

0 0 0 0 1 1 0 1 0 1 1 0 1 0 0

1.52500

0 0 0 0 1 1 1 0 0 1 1 0 1 1 1

1.51875

0 0 0 0 1 1 1 1 0 1 1 0 1 1 0

1.51250

0 0 0 1 0 0 0 0 0 1 1 1 0 0 1

1.50625

0 0 0 1 0 0 0 1 0 1 1 1 0 0 0

1.50000

0 0 0 1 0 0 1 0 0 1 1 1 0 1 1

1.49375

0 0 0 1 0 0 1 1 0 1 1 1 0 1 0

1.48750

0 0 0 1 0 1 0 0 0 1 1 1 1 0 1

1.48125

0 0 0 1 0 1 0 1 0 1 1 1 1 0 0

1.47500

0 0 0 1 0 1 1 0 0 1 1 1 1 1 1

1.46875

0 0 0 1 0 1 1 1 0 1 1 1 1 1 0

1.46250

0 0 0 1 1 0 0 0 1 0 0 0 0 0 1

1.45625

0 0 0 1 1 0 0 1 1 0 0 0 0 0 0

1.45000

0 0 0 1 1 0 1 0 1 0 0 0 0 1 1

1.44375

0 0 0 1 1 0 1 1 1 0 0 0 0 1 0

1.43750

0 0 0 1 1 1 0 0 1 0 0 0 1 0 1

1.43125

0 0 0 1 1 1 0 1 1 0 0 0 1 0 0

1.42500

0 0 0 1 1 1 1 0 1 0 0 0 1 1 1

1.41875

0 0 0 1 1 1 1 1 1 0 0 0 1 1 0

1.41250

0 0 1 0 0 0 0 0 1 0 0 1 0 0 1

1.40625

0 0 1 0 0 0 0 1 1 0 0 1 0 0 0

1.40000

0 0 1 0 0 0 1 0 1 0 0 1 0 1 1

1.39375

0 0 1 0 0 0 1 1 1 0 0 1 0 1 0

1.38750

0 0 1 0 0 1 0 0 1 0 0 1 1 0 1

1.38125

0 0 1 0 0 1 0 1 1 0 0 1 1 0 0

1.37500

0 0 1 0 0 1 1 0 1 0 0 1 1 1 1

1.36875

0 0 1 0 0 1 1 1 1 0 0 1 1 1 0

1.36250

0 0 1 0 1 0 0 0 1 0 1 0 0 0 1

1.35625

0 0 1 0 1 0 0 1 1 0 1 0 0 0 0

1.35000

0 0 1 0 1 0 1 0 1 0 1 0 0 1 1

1.34375

0 0 1 0 1 0 1 1 1 0 1 0 0 1 0

1.33750

0 0 1 0 1 1 0 0 1 0 1 0 1 0 1

1.33125

0 0 1 0 1 1 0 1 1 0 1 0 1 0 0

1.32500

0 0 1 0 1 1 1 0 1 0 1 0 1 1 1

1.31875

0 0 1 0 1 1 1 1 1 0 1 0 1 1 0

ADP3189

Rev. 0 | Page 18 of 36

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

1.31250

0 0 1 1 0 0 0 0 1 0 1 1 0 0 1

1.30625

0 0 1 1 0 0 0 1 1 0 1 1 0 0 0

1.30000

0 0 1 1 0 0 1 0 1 0 1 1 0 1 1

1.29375

0 0 1 1 0 0 1 1 1 0 1 1 0 1 0

1.28750

0 0 1 1 0 1 0 0 1 0 1 1 1 0 1

1.28125

0 0 1 1 0 1 0 1 1 0 1 1 1 0 0

1.27500

0 0 1 1 0 1 1 0 1 0 1 1 1 1 1

1.26875

0 0 1 1 0 1 1 1 1 0 1 1 1 1 0

1.26250

0 0 1 1 1 0 0 0 1 1 0 0 0 0 1

1.25625

0 0 1 1 1 0 0 1 1 1 0 0 0 0 0

1.25000

0 0 1 1 1 0 1 0 1 1 0 0 0 1 1

1.24375

0 0 1 1 1 0 1 1 1 1 0 0 0 1 0

1.23750

0 0 1 1 1 1 0 0 1 1 0 0 1 0 1

1.23125

0 0 1 1 1 1 0 1 1 1 0 0 1 0 0

1.22500

0 0 1 1 1 1 1 0 1 1 0 0 1 1 1

1.21875

0 0 1 1 1 1 1 1 1 1 0 0 1 1 0

1.21250

0 1 0 0 0 0 0 0 1 1 0 1 0 0 1

1.20625

0 1 0 0 0 0 0 1 1 1 0 1 0 0 0

1.20000

0 1 0 0 0 0 1 0 1 1 0 1 0 1 1

1.19375

0 1 0 0 0 0 1 1 1 1 0 1 0 1 0

1.18750

0 1 0 0 0 1 0 0 1 1 0 1 1 0 1

1.18125

0 1 0 0 0 1 0 1 1 1 0 1 1 0 0

1.17500

0 1 0 0 0 1 1 0 1 1 0 1 1 1 1

1.16875

0 1 0 0 0 1 1 1 1 1 0 1 1 1 0

1.16250

0 1 0 0 1 0 0 0 1 1 1 0 0 0 1

1.15625

0 1 0 0 1 0 0 1 1 1 1 0 0 0 0

1.15000

0 1 0 0 1 0 1 0 1 1 1 0 0 1 1

1.14375

0 1 0 0 1 0 1 1 1 1 1 0 0 1 0

1.13750

0 1 0 0 1 1 0 0 1 1 1 0 1 0 1

1.13125

0 1 0 0 1 1 0 1 1 1 1 0 1 0 0

1.12500

0 1 0 0 1 1 1 0 1 1 1 0 1 1 1

1.11875

0 1 0 0 1 1 1 1 1 1 1 0 1 1 0

1.11250

0 1 0 1 0 0 0 0 1 1 1 1 0 0 1

1.10625

0 1 0 1 0 0 0 1 1 1 1 1 0 0 0

1.10000

0 1 0 1 0 0 1 0 1 1 1 1 0 1 1

1.09375

0 1 0 1 0 0 1 1 1 1 1 1 0 1 0

OFF N/A

1 1 1 1 1 0 1

OFF N/A

1 1 1 1 1 0 0

OFF N/A

1 1 1 1 1 1 1

OFF N/A

1 1 1 1 1 1 0

1.08750

0 1 0 1 0 1 0 0 0 0 0 0 0 0 1

1.08125

0 1 0 1 0 1 0 1 0 0 0 0 0 0 0

1.07500

0 1 0 1 0 1 1 0 0 0 0 0 0 1 1

1.06875

0 1 0 1 0 1 1 1 0 0 0 0 0 1 0

1.06250

0 1 0 1 1 0 0 0 0 0 0 0 1 0 1

1.05625

0 1 0 1 1 0 0 1 0 0 0 0 1 0 0

1.05000

0 1 0 1 1 0 1 0 0 0 0 0 1 1 1

1.04375

0 1 0 1 1 0 1 1 0 0 0 0 1 1 0

1.03750

0 1 0 1 1 1 0 0 0 0 0 1 0 0 1

ADP3189

Rev. 0 | Page 19 of 36

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

1.03125

0 1 0 1 1 1 0 1 0 0 0 1 0 0 0

1.02500

0 1 0 1 1 1 1 0 0 0 0 1 0 1 1

1.01875

0 1 0 1 1 1 1 1 0 0 0 1 0 1 0

1.01250

0 1 1 0 0 0 0 0 0 0 0 1 1 0 1

1.00625

0 1 1 0 0 0 0 1 0 0 0 1 1 0 0

1.00000

0 1 1 0 0 0 1 0 0 0 0 1 1 1 1

0.99375

0 1 1 0 0 0 1 1 0 0 0 1 1 1 0

0.98750

0 1 1 0 0 1 0 0 0 0 1 0 0 0 1

0.98125

0 1 1 0 0 1 0 1 0 0 1 0 0 0 0

0.97500

0 1 1 0 0 1 1 0 0 0 1 0 0 1 1

0.96875

0 1 1 0 0 1 1 1 0 0 1 0 0 1 0

0.96250

0 1 1 0 1 0 0 0 0 0 1 0 1 0 1

0.95625

0 1 1 0 1 0 0 1 0 0 1 0 1 0 0

0.95000

0 1 1 0 1 0 1 0 0 0 1 0 1 1 1

0.94375

0 1 1 0 1 0 1 1 0 0 1 0 1 1 0

0.93750

0 1 1 0 1 1 0 0 0 0 1 1 0 0 1

0.93125

0 1 1 0 1 1 0 1 0 0 1 1 0 0 0

0.92500

0 1 1 0 1 1 1 0 0 0 1 1 0 1 1

0.91875

0 1 1 0 1 1 1 1 0 0 1 1 0 1 0

0.91250

0 1 1 1 0 0 0 0 0 0 1 1 1 0 1

0.90625

0 1 1 1 0 0 0 1 0 0 1 1 1 0 0

0.90000

0 1 1 1 0 0 1 0 0 0 1 1 1 1 1

0.89375

0 1 1 1 0 0 1 1 0 0 1 1 1 1 0

0.88750

0 1 1 1 0 1 0 0 0 1 0 0 0 0 1

0.88125

0 1 1 1 0 1 0 1 0 1 0 0 0 0 0

0.87500

0 1 1 1 0 1 1 0 0 1 0 0 0 1 1

0.86875

0 1 1 1 0 1 1 1 0 1 0 0 0 1 0

0.86250

0 1 1 1 1 0 0 0 0 1 0 0 1 0 1

0.85625

0 1 1 1 1 0 0 1 0 1 0 0 1 0 0

0.85000

0 1 1 1 1 0 1 0 0 1 0 0 1 1 1

0.84375

0 1 1 1 1 0 1 1 0 1 0 0 1 1 0

0.83750

0 1 1 1 1 1 0 0 0 1 0 1 0 0 1

0.83125

0 1 1 1 1 1 0 1 0 1 0 1 0 0 0

0.82500

0 1 1 1 1 1 1 0 N/A

0.81875

0 1 1 1 1 1 1 1 N/A

0.81250

1 0 0 0 0 0 0 0 N/A

0.80625

1 0 0 0 0 0 0 1 N/A

0.80000

1 0 0 0 0 0 1 0 N/A

0.79375

1 0 0 0 0 0 1 1 N/A

0.78750

1 0 0 0 0 1 0 0 N/A

0.78125

1 0 0 0 0 1 0 1 N/A

0.77500

1 0 0 0 0 1 1 0 N/A

0.76875

1 0 0 0 0 1 1 1 N/A

0.76250

1 0 0 0 1 0 0 0 N/A

0.75625

1 0 0 0 1 0 0 1 N/A

0.75000

1 0 0 0 1 0 1 0 N/A

0.74375

1 0 0 0 1 0 1 1 N/A

0.73750

1 0 0 0 1 1 0 0 N/A

0.73125

1 0 0 0 1 1 0 1 N/A

ADP3189

Rev. 0 | Page 20 of 36

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0.72500

1 0 0 0 1 1 1 0 N/A

0.71875

1 0 0 0 1 1 1 1 N/A

0.71250

1 0 0 1 0 0 0 0 N/A

0.70625

1 0 0 1 0 0 0 1 N/A

0.70000

1 0 0 1 0 0 1 0 N/A

0.69375

1 0 0 1 0 0 1 1 N/A

0.68750

1 0 0 1 0 1 0 0 N/A

0.68125

1 0 0 1 0 1 0 1 N/A

0.67500

1 0 0 1 0 1 1 0 N/A

0.66875

1 0 0 1 0 1 1 1 N/A

0.66250

1 0 0 1 1 0 0 0 N/A

0.65625

1 0 0 1 1 0 0 1 N/A

0.65000

1 0 0 1 1 0 1 0 N/A

0.64375

1 0 0 1 1 0 1 1 N/A

0.63750

1 0 0 1 1 1 0 0 N/A

0.63125

1 0 0 1 1 1 0 1 N/A

0.62500

1 0 0 1 1 1 1 0 N/A

0.61875

1 0 0 1 1 1 1 1 N/A

0.61250

1 0 1 0 0 0 0 0 N/A

0.60625

1 0 1 0 0 0 0 1 N/A

0.60000

1 0 1 0 0 0 1 0 N/A

0.59375

1 0 1 0 0 0 1 1 N/A

0.58750

1 0 1 0 0 1 0 0 N/A

0.58125

1 0 1 0 0 1 0 1 N/A

0.57500

1 0 1 0 0 1 1 0 N/A

0.56875

1 0 1 0 0 1 1 1 N/A

0.56250

1 0 1 0 1 0 0 0 N/A

0.55625

1 0 1 0 1 0 0 1 N/A

0.55000

1 0 1 0 1 0 1 0 N/A

0.54375

1 0 1 0 1 0 1 1 N/A

0.53750

1 0 1 0 1 1 0 0 N/A

0.53125

1 0 1 0 1 1 0 1 N/A

0.52500

1 0 1 0 1 1 1 0 N/A

0.51875

1 0 1 0 1 1 1 1 N/A

0.51250

1 0 1 1 0 0 0 0 N/A

0.50625

1 0 1 1 0 0 0 1 N/A

0.50000

1 0 1 1 0 0 1 0 N/A

OFF 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0

OFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ADP3189

Rev. 0 | Page 21 of 36

* FOR A DESCRIPTION OF OPTIONAL R

RESISTORS, SEE THE THEORY OF OPERATION SECTION

ADP3189

M C

3120

VIDSEL

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VCC

ILIMIT

RAMPADJ

SET

CSREF

CSSUM

CSCOMP

GND

BRT

*
*

I
N

DUC

R3 1

C8 1nF

560pF

1.00k

100k

, 5%

LIM

100k

CS2

88.7k

CS1

35.7k

PH3

158k

PH4

158k

PH2

158k

PH1

158k

182k

10.0k

27pF

18nF

39nF

100

(C3 OP

I
ONAL

)

1N4148

12V

0.1

1nF

CS1

1nF

5% NP

CS2

1nF

5% NP

C22

4.7

C18

4.7

1nF

560nF

R GOOD

TT I/O

VRF

PROCHOT

2.2

370nH

18A

2700

F / 16V

/ 3.3 A

SANYO

-
W

X SERI

C14

4.7

1N4148

C21

18nF

2.2

C17

18nF

2.2

C13

18nF

Q13

NTD40N03

Q11

NTD110N02

Q12

NTD110N02

Q14

NTD40N03

Q15

NTD110N02

Q16

NTD110N02

C23

10nF

C24

4.7

C19

10nF

C15

10nF

Q10

NTD40N03

C20

4.7

320nH/1.4m

NTD40N03

NTD110N02

NTD40N03

C16

4.7

320nH/1.4m

3120

C10

4.7

1N4148

2.2

18nF

C25

C34

C11

10nF

NTD40N03

NTD110N02

560

F / 4V

/ 4V

SANYO

SEPC SERI

EACH

NTD40N03

C12

4.7

320nH/1.4m

100k

, 5%

1
0

*
*

CC(CORE)

0.5V

1.6V

115A TDC, 130A P

CC(SENSE)

SS(SENSE)

CC(CORE) RT

F×18

MLC

IN S

CKE

05626-011

Figure 11.Typical 4-Phase Application Circuit

ADP3189

Rev. 0 | Page 22 of 36

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 11 compliant
CPU application are as follows:

Input voltage (V

) = 12 V

VID setting voltage (V

VID

) = 1.300 V

Duty cycle (D) = 0.108

Nominal output voltage at no load (V

ONL

) = 1.285 V

Nominal output voltage at 115 A load (V

OFL

) = 1.170 V

Static output voltage drop based on a 1.0 m load line (R

)

from no load to full load (V

) = V

ONL

- V

OFL

1.285 V - 1.170 V = 115 mV

Maximum output current (I

) = 130 A

Maximum output current step (I

) = 100 A

Maximum output current slew-rate (S

) = 200 A/ sec

Number of phases (n) = 4

Switching frequency per phase (f

) = 330 kHz

SETTING THE CLOCK FREQUENCY

The ADP3189 uses a fixed-frequency control architecture.
The frequency is set by an external timing resistor (R

The clock frequency and the number of phases determine
the switching frequency per phase, which relates directly
to switching losses and the sizes of the inductors, and of
the input and output capacitors. With n = 4 for four phases,
a clock frequency of 1.32 MHz sets the switching frequency
(f

) of each phase to 330 kHz, which represents a practical

trade-off between the switching losses and the sizes of the out-
put filter components. Equation 1 shows that to achieve a
1.32 MHz oscillator frequency, the correct value for R

181 k. Alternatively, the value for R

can be calculated using

(1)

where 3.9 pF and 13 k are internal IC component values.
For good initial accuracy and frequency stability, a 1% resistor
is recommended.

SOFT START DELAY TIME

The value of C

sets the soft start time. The ramp is generated

with a 15 A internal current source. The value for C

can be

found using:

BOOT

(2)

where TD2 is the desired soft start time and V

BOOT

is internally

set to 1.1 V. Assuming a desired TD2 time of 3 ms, C

is 41 nF.

The closest standard value for C

is 39 nF. Although C

also

controls the time delay for TD4 (which is determined by the
final VID voltage), the minimum specification for TD4 is 0 ns.
This means that as long as the TD2 time requirement is met,
TD4 will be within the specification.

CURRENT LIMIT LATCH-OFF DELAY TIMES

The start-up and current limit delay times are determined by
the capacitor connected to the DELAY pin. The first step is to
set C

DLY

for the TD1, TD3, and TD5 delay times (see Figure 8).

The DELAY ramp (I

DELAY

)

is generated using a 15 A internal

current source. The value for C

DLY

can be approximated using:

)

(

)

(

DELAY

DLY

(3)

where TD(x) is the desired delay time for TD1, TD3, and TD5.
The DELAY threshold voltage (V

DELAY(TH)

) is given as 1.7 V. In

this example, 2 ms is chosen for all three delay times, which
meets Intel's specification. Solving for C

DLY

gives a value of

17.6 nF. The closest standard value for C

DLY

is 18 nF.

When the ADP3189 goes into current limit, the internal current
source changes from 15 A to 3.75 A. This makes the latch-off
delay time 4 times longer than the start-up delay time. Longer
latch-off delay times can be achieved by placing a resistor in
parallel with C

DLY

ADP3189

Rev. 0 | Page 23 of 36

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs, but allows using smaller inductors and,
for a specified peak-to-peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower
ripple current and reduced conduction losses, but requires
larger inductors and more output capacitance for the same
peak-to-peak transient deviation.

In any multiphase converter, a practical value for the
peak-to-peak inductor ripple current is less than 50% of
the maximum dc current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator
frequency, and peak-to-peak ripple current in the inductor.

Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.

(

)

VID

(4)

(

)

(

)

RIPPLE

VID

(5)

Solving Equation 5 for an 8 mV p-p output ripple voltage yields

(

)

kHz

330

0.432

1.0

1.3

If the resulting ripple voltage is less than that designed for,
the inductor can be made smaller until the ripple value is met.
This allows optimal transient response and minimum output
decoupling.

The smallest possible inductor should be used to minimize
the number of output capacitors. For this example, choosing a
320 nH inductor is a good starting point and gives a calculated
ripple current of 11 A. The inductor should not saturate at the
peak current of 35.5 A and should be able to handle the sum of
the power dissipation caused by the average current of 30 A in
the winding and core loss.

Another important factor in the inductor design is the DCR
(R

), which is used for measuring the phase currents. A large

DCR can cause excessive power losses, while too small a value
can lead to increased measurement error. A good rule is to have
the DCR be about 1 to 1½ times the droop resistance (R

). This

example uses an inductor with a DCR of 1.4 m.

DESIGNING AN INDUCTOR

Once the inductance and DCR are known, the next step is to
either design an inductor or to find a standard inductor that
comes as close as possible to meeting the overall design goals.
It is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 15% inductance
and 7% DCR, at room temperature, are reasonable tolerances
most manufacturers can meet.

The first decision in designing the inductor is choosing the
core material. Several possibilities for providing low core loss
at high frequencies include the powder cores (for example,
Kool-M® from Magnetics, Inc. or from Micrometals) and the
gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips).
Low frequency powdered iron cores should be avoided due to
their high core loss, especially when the inductor value is
relatively low and the ripple current is high.

The best choice for a core geometry is a closed-loop type such
as a potentiometer core; PQ, U, or E core; or toroid. A good
compromise between price and performance is a core with
a toroidal shape.

Many useful magnetics design references are available for
quickly designing a power inductor, such as

Magnetic Designer Software
Intusoft (www.intusoft.com)

Designing Magnetic Components for High-Frequency DC-
DCConverters, by William T. McLyman, Kg Magnetics,
Inc., ISBN 1883107008

Selecting a Standard Inductor

The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request.

Coilcraft
www.coilcraft.com

Coiltronics
www.coiltronics.com

Sumida Electric Company
www.sumida.com

Vishay Intertechnology
www.vishay.com

ADP3189

Rev. 0 | Page 24 of 36

CURRENT SENSE AMPLIFIER

Most designs require the regulator output voltage, measured at
the CPU pins, to drop when the output current increases. The
specified voltage drop corresponds to a dc output resistance (R

also referred to as a load line. The ADP3189 has the flexibility of
adjusting R

, independent of current limit or compensation

components, and it can also support CPUs that do not require
a load line.

For designs requiring a load line, the impedance gain of the
CS amplifier (R

CSA

) must be to be greater than or equal to the load

line. All designs, whether they have a load line or not, should
keep R

CSA

1 m.

The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with resistors
R

PH(X)

(summers), and R

and C

(filter). The impedance gain

of the regulator is set by the following equations, where R

is the

DCR of the output inductors:

( )

CSA

(6)

(7)

The user has the flexibility of choosing either R

or R

PH(X)

However, it is best to select R

equal to 100 k, and then solve

for R

PH(X)

by rearranging Equation 6. Here R

CSA

= R

= 1 m

since this is equal to our design loadline.

( )

140

100

CSA

Next, use Equation 7 to solve for C

100

320

It is best to have a dual location for C

in the layout so that

standard values can be used in parallel to get as close to the
value desired. For best accuracy, C

should be a 5% or 10%

NPO capacitor. This example uses a 5% combination for C

of two 1 nF capacitors in parallel. Recalculating R

and R

PH(X)

using this capacitor combination yields 114 k and 160 k.
The closest standard 1% value for R

PH(X)

is 158 k.

INDUCTOR DCR TEMPERATURE CORRECTION

With the inductor's DCR is used as the sense element and
copper wire is the source of the DCR, the user needs to
compensate for temperature changes of the inductor's winding.
Fortunately, copper has a well known temperature coefficient
(TC) of 0.39%/°C.

If R

is designed to have an opposite and equal percentage

change in resistance to that of the wire, it cancels the tempera-
ture variation of the inductor's DCR. Due to the nonlinear
nature of NTC thermistors, resistors R

CS1

and R

CS2

are needed.

See Figure 12 to linearize the NTC and produce the desired
temperature tracking.

CSREF

CSSUM

CSCOMP

CS1

CS2

CS1

CS2

PH1

PH2

PH3

PLACE AS CLOSE AS POSSIBLE

TO THE NEAREST INDUCTOR

KEEP THIS PATH

AS SHORT AS

POSSIBLE AND

WELL AWAY FROM

SWITCH NODE LINES

ADP3189

05626-012

Figure 12. Temperature Compensation Circuit Values

The following procedure and expressions yield values to use
for R

CS1

, R

CS2

, and R

(the thermistor value at 25°C) for a given

value.

Select an NTC based on type and value. Since the value
is unknown, use a thermistor with a value close to R

The NTC should also have an initial tolerance of better
than 5%.

Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called
A (R

TH(50°C)

)/R

TH(25°C)

) and B (R

TH(90°C)

)/R

TH(25°C)

). The NTC's

relative value is always 1 at 25°C.

Find the relative value of R

required for each of these

temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/°C. These
are called r

(1/(1 + TC × (T

- 25))) and r

(1/(1 + TC ×

- 25))), where TC = 0.0039 for copper. T

= 50°C and

= 90°C are chosen. From this, calculate that r

= 0.9112

and r

= 0.7978.

ADP3189

Rev. 0 | Page 25 of 36

Compute the relative values for R

CS1

, R

CS2

, and R

using

(

)

(

)

(

)

(

)

(

)

(

)

CS2

(8)

(

)

CS2

CS1

(9)

CS1

CS2

(10)

Calculate R

= r

× R

, then select the closest value of

thermistor available. Also, compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:

(

)

(

)

CALCULATED

ACTUAL

k =

(11)

Calculate values for R

CS1

and R

CS2

using Equation 12 and

Equation 13:

CS1

(12)

(

) (

)

(

)

CS2

(13)

In this example, R

was calculated to be 114 k. Look for an

available 100 k thermistor, 0603 size. One such thermistor
is the Vishay NTHS0603N01N1003JR NTC thermistor with
A = 0.3602 and B = 0.09174. From these values, compute
r

CS1

= 0.3795, r

CS2

= 0.7195, and r

= 1.075.

Solving for R

yields 122.55 k, so 100 k is chosen, making

k = 0.816. Next find R

CS1

and R

CS2

to be 35.3 k and 87.9 k.

Finally, choose the closest 1% resistor values, which yields a
choice of 35.7 k and 88.7 k.

LOAD LINE SETTING

For load line values greater than 1 m, R

CSA

can be set equal

to R

, and the LLSET pin can be directly connected to the

CSCOMP pin. When the load line value needs to be less than
1 m, two additional resistors are required. Figure 13 shows
the placement of these resistors.

CSREF

LLSET

CSSUM

CSCOMP

ADP3189

05626-013

LL1

LL2

OPTIONAL LOAD LINE

SELECT SWITCH

Figure 13. Load Line Setting Resistors

The two resistors R

LL1

and R

LL2

set up a divider between the

CSCOMP pin and CSREF pin. This resistor divider is input into
the LLSET pin to set the load line slope R

of the VR according

to the following equation:

CSA

(14)

For best results, start with a 1% resistor of 20.0 k for R

LL2

Then, solve for the required value of R

LL1

by rearranging

Equation 14 as follows:

CSA

Another useful feature for some VR applications is the ability to
select different load lines. Figure 13 shows an optional MOSFET
switch that allows this. Here, design for R

CSA

= R

O(MAX)

(selected

with Q

on) and then use Equation 14 to set R

= R

O(MIN)

(selected with Q

off).

For this design, R

CSA

= R

= 1 m, so connect LLSET directly to

CSCOMP, and the resistors R

LL1

and R

LL2

are not needed.

ADP3189

Rev. 0 | Page 26 of 36

OUTPUT OFFSET

The Intel specification requires that at no load the nominal
output voltage of the regulator is offset to a value lower than
the nominal voltage corresponding to the VID code. The offset
is set by a constant current source flowing out of the FB pin (I

)

and flowing through R

. The value of R

can be found using

Equation 15:

ONL

VID

285

(15)

The closest standard 1% resistor value is 1.00 k.

OUT

SELECTION

The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Use some simple design guidelines to determine the require-
ments. These guidelines are based on having both bulk
capacitors and ceramic capacitors in the system.

First, select the total amount of ceramic capacitance. This is
based on the number and type of capacitor to be used. The best
location for ceramic capacitors is inside the socket, with 12 to
18 of size, 1206 being the physical limit. Other capacitors can be
placed along the outer edge of the socket as well.

To aid in determining the minimum amount of ceramic
capacitance required, start with a worst-case load step occur-
ring right after a switching cycle has stopped. The ceramic
capacitance then delivers the charge to the load while the load
is ramping up and until the VR has responded with the next
switching cycle.

The following equation gives the designer a rough
approximation for determining the minimum ceramic
capacitance needed. Due to the complexity of the PCB
parasitics and bulk capacitors, the actual amount of ceramic
capacitance required may vary.

(

)

MIN

(16)

The typical ceramic capacitors used are made up of multiple
10 F or 22 F capacitors. For this example, Equation 16 yields
180.8 F, so eighteen 10 uF ceramics will suffice.

Next, there is an upper limit imposed on the total amount of
bulk capacitance (C

) when the user considers the VID on-the-

fly voltage stepping of the output (voltage step V

A lower limit is based on meeting the capacitance for load
release for a given maximum load step I

and a maximum

allowable overshoot. The total amount of load release voltage
is given as

× R

, where

is the maximum

allowable overshoot voltage.

(

)

VID

MIN

(17)

(

)

MAX

(18)

VID

nKR

ERR

where

To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (R

) should be less

than two times the droop resistance (R

). If the C

X(MIN)

is larger

than C

X(MAX)

, the system cannot meet the VID on-the-fly speci-

fication and can require the use of a smaller inductor or more
phases (and may have to increase the switching frequency to
keep the output ripple the same).

This example uses eighteen 10 F 1206 MLC capacitors
(C

= 180 F). The VID on-the-fly step change is 450 mV in

230 s with a setting error of 2.5 mV. The maximum allowable
load release overshoot for this example is 50 mV, therefore
solving for the bulk capacitance yields

(

)

180

100

320

MIN

(

)

(

)

450

320

MAX

180

320

450

230

in time t

with error of V

ERR

where K = 5.2

ADP3189

Rev. 0 | Page 27 of 36

Using ten 560 F Al-Poly capacitors with a typical ESR of 6 m
each yields C

= 5.6 mF with an R

= 0.6 m.

One last check should be made to ensure that the ESL of the
bulk capacitors (L

) is low enough to limit the high frequency

ringing during a load change.

This is tested using

(

)

180

(19)

where Q

is limited to

to ensure a critically damped system.

In this example, L

is approximately 240 pH for the ten

A1-Polys capacitors, which satisfies this limitation. If the L

of the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased, or lower ESL bulks
used if there is excessive undershoot during a load transient.

For this multimode control technique, all ceramic designs can
be used providing the conditions of Equation 16, Equation 17,
Equation 18, and Equation 19 are satisfied.

POWER MOSFETS

For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V

GS(TH)

, Q

, C

ISS

, C

RSS

, and R

DS(ON)

. The minimum gate drive

voltage (the supply voltage to the ADP3120) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V

GATE

~10 V, logic-level threshold MOSFETs

GS(TH)

< 2.5 V) are recommended.

The maximum output current (I

) determines the R

DS(ON)

requirement for the low-side (synchronous) MOSFETs. With
the ADP3189, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (n

). With conduction losses

being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I

) and average total output current (I

(

)

( )

(20)

Knowing the maximum output current being designed for and
the maximum allowed power dissipation, the user can find the
required R

DS(ON)

for the MOSFET. For D-PAK MOSFETs up to

an ambient temperature of 50°C, a safe limit for P

is 1 W to

1.5 W at 120°C junction temperature. Thus, for this example
(119 A maximum), R

DS(SF)

(per MOSFET) < 7.5 m. This R

DS(SF)

is also at a junction temperature of about 120°C, so be certain to
account for this when making this selection. This example uses
two lower-side MOSFETs at 4.8 m, each at 120°C.

Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3120). The output impedance of the
driver is approximately 2 , and the typical MOSFET input gate
resistances are about 1 to 2 , so a total gate capacitance of
less than 6000 pF should be adhered to. Since there are two
MOSFETs in parallel, the input capacitance for each synchronous
MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switching
speed on the rise and fall time of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where n

is the total number of main MOSFETs:

(

)

ISS

= 2

(21)

where R

is the total gate resistance (2 for the ADP3120 and

about 1 for typical high speed switching MOSFETs, making
R

= 3 ), and C

ISS

is the input capacitance of the main MOSFET.

Adding more main MOSFETs (n

) does not help the switching

loss per MOSFET, since the additional gate capacitance slows
switching. Use lower gate capacitance devices to reduce
switching loss.

The conduction loss of the main MOSFET is given by the
following, where R

DS(MF)

is the on resistance of the MOSFET:

(

)

(

)

(22)

Typically, for main MOSFETs, the highest speed (low C

ISS

)

device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.

ADP3189

Rev. 0 | Page 28 of 36

For this example, an NTD40N03L was selected as the main
MOSFET (eight total; n

= 8), with C

ISS

= 584 pF (max) and

DS(MF)

= 19 m (max at T

= 120°C), and an NTD110N02L was

selected as the synchronous MOSFET (eight total; n

= 8), with

ISS

= 2710 pF (max) and R

DS(SF)

= 4.8 m (max at T

= 120°C).

The synchronous MOSFET C

ISS

is less than 3000 pF, satisfying

this requirement. Solving for the power dissipation per MOSFET
at IO = 119 A and IR = 11 A yields 958 mW for each synchronous
MOSFET and 872 mW for each main MOSFET. The guideline
is to limit the MOSFET power dissipation to 1 W. The values
calculated in Equation 21 and Equation 22 comply with this
guideline.

Finally, consider the power dissipation in the driver for each
phase. This is best expressed as Q

for the MOSFETs and is

given by the following equation, where Q

GMF

is the total gate

charge for each main MOSFET and Q

GSF

is the total gate charge

for each synchronous MOSFET.

(

)

GSF

GMF

DRV

(23)

Also shown is the driver's standby dissipation factor (I

× V

For the ADP3120, the maximum dissipation should be less than
400 mW. In this example, with I

= 7 mA, Q

GMF

= 5.8 nC, and

GSF

= 48 nC, one finds 297 mW in each driver, which is below

the 400 mW dissipation limit. See the ADP3120 data sheet for
more details.

RAMP RESISTOR SELECTION

The ramp resistor (R

) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:

356

2.4

320

0.2

(24)

where

is the internal ramp amplifier gain.

is the current balancing amplifier gain.

is the total low-side MOSFET on resistance.

is the internal ramp capacitor value.

The internal ramp voltage magnitude can be calculated by using

(

)

(

)

kHz

330

357

1.3

0.108

0.2

VID

(25)

The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and noise rejection improves, but
transient degrades. Likewise, if the ramp is made smaller,
transient response improves at the sacrifice of noise rejection
and stability.

The factor of 3 in the denominator of Equation 24 sets a ramp
size that gives an optimal balance for good stability, transient
response, and thermal balance.

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage and
output voltage ramps. This ramp amplitude adds to the internal
ramp to produce the following overall ramp signal at the PWM
input:

(

)

(26)

In this example, the overall ramp signal is 0.46 V. However,
if the ramp size is smaller than 0.5 V, increase the ramp size
to be at least 0.5 V by decreasing the ramp resistor for noise
immunity. As there is only 0.46 V initially, a ramp resistor value
of 332 k is chosen for this example, yielding an overall ramp
of 0.51 V.

ADP3189

Rev. 0 | Page 29 of 36

CURRENT LIMIT SETPOINT

FEEDBACK LOOP COMPENSATION DESIGN

To select the current limit setpoint, first find the resistor value
for R

LIM

. The current limit threshold for the ADP3189 is set

with a 1.7 V source (V

LIM

) across R

LIM

with a gain of 10 mV/A

LIM

). R

LIM

can be found using

CSA

LIM

(27)

Optimized compensation of the ADP3189 allows the best
possible response of the regulator's output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resis-
tance (R

). With the resistive output impedance, the output

voltage droops in proportion to the load current at any load
current slew rate. This ensures the optimal positioning and
allows the minimization of the output decoupling.

For values of R

LIM

greater than 500 k, the current limit may be

lower than expected, so some adjustment of R

LIM

is needed. Here,

LIM

is the peak average current limit for the supply output. In this

example, choosing a peak current limit of 170 A for I

LIM

, results

in R

LIM

= 100 k, and 100 k is chosen as the nearest 1% value.

The per-phase initial duty cycle limit and peak current during a
load step are determined by

(

)

BIAS

MAX

COMP

MAX

(28)

With the multimode feedback structure of the ADP3189, the
feedback compensation must be set to make the converter's
output impedance, working in parallel with the output decoup-
ling, to meet this goal. Several poles and zeros created by the
output inductor and decoupling capacitors (output filter) need
to be compensated for.

(

)

VID

MAX

PHMAX

(29)

A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equation 31 to
Equation 35 are intended to yield an optimal starting point for
the design; some adjustments may be necessary to account for
PCB and component parasitic effects (see the Tuning the
ADP3189 section).

For the ADP3189, the maximum COMP voltage (V

COMP(MAX)

) is

4.0 V and the COMP pin bias voltage (V

BIAS

) is 1.1 V. In this

example, the maximum duty cycle is 0.61 and the peak current
is 62 A.

First, compute the time constants for all the poles and zeros in
the system, using Equation 31 to Equation 35 on the next page.

The limit of the peak per-phase current described earlier during
the secondary current limit is determined by

(

)

(

)

MAX

BIAS

CLAMPED

COMP

PHLIM

(30)

For the ADP3189, the current balancing amplifier gain (A

) is 5,

and the clamped COMP pin voltage is 2 V. Using an R

DS(MAX)

2.8 m (low-side on resistance at 150°C) results in a per-phase
peak current limit of 64 A. This current level can be reached
only with an absolute short at the output, and the current limit
latch-off function shuts down the regulator before overheating
can occur.

ADP3189

Rev. 0 | Page 30 of 36

The first step is to compute the time constants for all of the poles and zeros in the system:

(

)

VID

(

)

1.3

0.432

320

1.3

1.4

2.4

(31)

(

)

(

)

0.6

0.5

(32)

(

)

(

)

0.5

0.6

(33)

1.3

kHz

330

2.4

320

VID

(34)

(

)

(

)

(

)

180

0.5

180

(35)

where, for the ADP3189,

R' is the PCB resistance from the bulk capacitors to the ceramics and where R

is the total low-side MOSFET

on resistance per phase. In this example,

is 5,

equals 0.51 V,

R' is approximately 0.5 m (assuming a 4-layer, 1 ounce mother-

board), and

is 240 pH for the ten Al-Poly capacitors.

The compensation values can then be solved using

524

(36)

524

(37)

560

(38)

(39)

These are the starting values prior to tuning the design to account for layout and other parasitic effects (see the Tuning the ADP3189
section). The final values selected after tuning are

= 560 pF

= 10.0 k

= 560 pF

= 27 pF

ADP3189

Rev. 0 | Page 31 of 36

Figure 14 and Figure 15

show the typical transient response

using these compensation values.

05626-014

Figure 14. Typical Transient Response for Design Example

Load Step

05626-015

Figure 15. Typical Transient Response for Design Example Load Release

SELECTION AND INPUT CURRENT

di/dt REDUCTION

In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × V

OUT

and an amplitude of one-nth the

maximum output current. To prevent large voltage transients,
a low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by

14.7

0.108

108

CRMS

(40)

The capacitor manufacturer's ripple current ratings are often
based on only 2,000 hours of life. This makes it advisable to
further derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2,700 F, 16 V aluminum electrolytic capacitors, and eight
4.7 F ceramic capacitors.

To reduce the input current di/dt to a level below the recom-
mended maximum of 0.1 A/s, an additional small inductor
(L > 370 nH at 18 A) should be inserted between the converter
and the supply bus. This inductor also acts as a filter between
the converter and the primary power source.

THERMAL MONITOR DESIGN

A thermistor is used on the TTSENSE input of the ADP3189
for monitoring the temperature of the VR. A constant current
of 120 A is sourced out of this pin and run through a thermis-
tor network such as that shown in Figure 16.

TTSENSE

VRHOT

VRFAN

ADP3189

OPTIONAL

TEMPERATURE

ADJUST

RESISTOR

0.1

PLACE THERMISTOR

NEAR CLOSEST PHASE

TTSENSE

05626-016

Figure 16. VR Thermal Monitor Circuit

A voltage is generated from this current through the thermistor
and sensed inside the IC. When the voltage reaches 1.11 V, the
VRFAN output gets set. When the voltage reaches 0.81 V, the
VRHOT gets set. This corresponds to R

TTSENSE

values of 9.25 k

for VRFAN and 6.75 k.

These values correspond to a thermistor temperature of ~100°C
and ~110°C when using the same type of 100 k NTC thermistor
used in the current sense amplifier.

An additional fixed resistor in parallel with the thermistor
provides tuning the trip point temperatures to match the hot-
test temperature in the VR, when the thermistor itself is directly
sensing a proportionately lower temperature. Setting this
resistor value is best accomplished with a variable resistor
during thermal validation, and then fixing this value for the
final design.

Additionally, a 0.1 F should be used for filtering noise.

ADP3189

Rev. 0 | Page 32 of 36

TUNING THE ADP3189

Build a circuit based on the compensation values
computed from the design spreadsheet.

Hook up the dc load to circuit, turn it on, and verify its
operation. Also, check for jitter at no load and full load.

DC Loadline Setting

Measure the output voltage at no load (V

). Verify that it

is within tolerance.

Measure the output voltage at full load cold (V

FLCOLD

). Let

the board sit for ~10 minutes at full load, and then measure
the output (V

FLHOT

). If there is a change of more than a few

millivolts, adjust R

CS1

and R

CS2

using Equation 41 and

Equation 43.

(

)

(

)

FLHOT

FLCOLD

OLD

CS2

NEW

CS2

(41)

Repeat Step 4 until the cold and hot voltage measurements
remain the same.

Measure the output voltage from no load to full load using
5 A steps. Compute the loadline slope for each change, and
then average to get overall loadline slope (R

OMEAS

If R

OMEAS

is off from R

by more than 0.05 m, use the

following to adjust the R

values:

(

)

(

)

OMEAS

OLD

NEW

(42)

Repeat Step 6 and Step 7 to check the loadline, and repeat
adjustments if necessary.

Once dc loadline adjustment is complete, do not change
R

, R

CS1

, R

CS2

, or R

for the remainder of the procedure.

10.

Measure the output ripple at no load and full load with
a scope, and make sure it is within specifications.

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

OLD

CS1

NEW

CS2

OLD

CS1

OLD

CS1

OLD

CS1

NEW

CS1

(43)

ADP3189

Rev. 0 | Page 33 of 36

AC Loadline Setting

11.

Remove the dc load from the circuit and hook up the
dynamic load.

12.

Hook up the scope to the output voltage and set it to dc
coupling with the time scale at 100 s/div.

13.

Set the dynamic load for a transient step of about 40 A at
1 kHz with 50% duty cycle.

14.

Measure the output waveform (use dc offset on scope to
see the waveform). Try to use a vertical scale of
100 mV/div or finer. This waveform should look similar
to Figure 17.

ACDRP

DCDRP

05626-017

Figure 17. AC Loadline Waveform

15.

Use the horizontal cursors to measure V

ACDRP

and V

DCDRP

shown. Do not measure the undershoot or overshoot that
happens immediately after this step.

16.

If V

ACDRP

and V

DCDRP

are different by more than a few

millivolts, use Equation 44 to adjust C

CS.

You may need to

parallel different values to get the right one since there are
limited standard capacitor values available. (It is a good
idea to have locations for two capacitors in the layout for
this.)

(

)

(

)

DCDRP

ACDRP

OLD

NEW

(44)

17.

Repeat Step 11 to Step 13 and repeat the adjustments if
necessary. Once complete, do not change C

for the

remainder of the procedure.

Set the dynamic load step to maximum step size (do not
use a step size larger than needed) and verify that the
output waveform is square, which means that V

ACDRP

and

DCDRP

are equal.

Initial Transient Setting

18.

With the dynamic load still set at the maximum step size,
expand the scope time scale to see 2 s/div to 5 s/div.
The waveform can have two overshoots and one minor
undershoot (see Figure 18). Here, V

DROOP

is the final

desired value.

DROOP

TRAN1

TRAN2

05626-018

Figure 18. Transient Setting Waveform

19.

If both overshoots are larger than desired, try making
the adjustments described later in this step. If these
adjustments do not change the response, you are limited
by the output decoupling. Check the output response
each time you make a change, and check the switching
nodes to make ensure that the response is still stable.

Make the ramp resistor larger by 25% (R

RAMP

For V

TRAN1

, increase C

or increase the switching

frequency.

For V

TRAN2

, increase R

and decrease C

by 25%.

20.

For load release (see Figure 19), if V

TRANREL

is larger

than the allowed overshoot, there is not enough output
capacitance. Either more capacitance is needed, or the
inductor values need to be made smaller. (When changing
inductors, start the design again using a spreadsheet and
this tuning procedure.)

DROOP

TRANREL

05626-019

Figure 19. Transient Setting Waveform

ADP3189

Rev. 0 | Page 34 of 36

Since the ADP3189 turns off all of the phases (switches inductors
to ground), there is no ripple voltage present during load release.
Therefore, the user does not have to add headroom for ripple,
allowing load release VTRANREL to be larger than VTRAN1,
by the amount of ripple, and still meet specifications.

If V

TRAN1

and V

TRANREL

are less than the desired final droop, this

implies that capacitors can be removed. When removing capaci-
tors, check the output ripple voltage as well to make sure it is
still within specifications.

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power delivery current paths.
Keep in mind that each square unit of 1 ounce copper trace
has a resistance of ~0.53 m at room temperature.

Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths, so the resistance and inductance introduced by these
current paths is minimized and the via current rating is not
exceeded.

If critical signal lines (including the output voltage sense lines
of the ADP3189) must cross through power circuitry, it is best
if a signal ground plane can be interposed between those signal
lines and the traces of the power circuitry. This serves as a
shield to minimize noise injection into the signals at the
expense of making signal ground a bit noisier.

An analog ground plane should be used around and under the
ADP3189 as a reference for the components associated with the
controller. This plane should be tied to the nearest output
decoupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.

The components around the ADP3189 should be located close
to the controller with short traces. The most important traces
to keep short and away from other traces are the FB pin and
CSSUM pin. The output capacitors should be connected as
close as possible to the load (or connector), for example, a
microprocessor core, that receives the power. If the load is
distributed, the capacitors should also be distributed and
generally be in proportion to where the load tends to be
more dynamic.

Avoid crossing any signal lines over the switching power path
loop, described in the Power Circuitry Recommendations
section.

Power Circuitry Recommendations

The switching power path should be routed on the PCB to
encompass the shortest-possible length in order to minimize
radiated switching noise energy (that is, EMI) and conduction
losses in the board. Failure to take proper precautions often
results in EMI problems for the entire PC system and noise-
related operational problems in the power converter control
circuitry. The switching power path is the loop formed by
the current path through the input capacitors and the power
MOSFETs, including all interconnecting PCB traces and planes.
Using short and wide interconnection traces is especially critical
in this path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal
voltage loss.

Whenever a power dissipating component, for example, a
power MOSFET, is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surrounding
it, is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal perform-
ance from vias extended to the opposite side of the PCB, where
a plane can more readily transfer the heat to the air. Make a
mirror image of any pad being used to heatsink the MOSFETs
on the opposite side of the PCB to achieve the best thermal
dissipation to the air around the board. To further improve
thermal performance, use the largest possible pad area.

The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus, the FB trace and
FBRTN trace should be routed adjacent to each other on top
of the power ground plane back to the controller.

The feedback traces from the switch nodes should be connected
as close as possible to the inductor. The CSREF signal should be
connected to the output voltage at the nearest inductor to the
controller.

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