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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADP3020

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

High-Efficiency Notebook Computer

Power Supply Controller

FUNCTIONAL BLOCK DIAGRAM

POWER-ON

RESET

LINEAR

CONTROLLER

5.5V TO 25V

3.3V

2.5V

SS3

SS5

PWRGD

ADP3020

REF

5V LINEAR

3.3V

SMPS

1.20V

PFO

3.3V

SMPS

FEATURES
Wide Input Voltage Range: 4.5 V to 25 V
High Conversion Efficiency > 96%
Integrated Current Sense--No External Resistor Required
Low Shutdown Current: 7 A (Typical)
Dual Synchronous Buck Controllers with Selectable

PWM/Power-Saving Mode Operation

Built-In Gate Drive Boost Circuit for Driving External

N-Channel MOSFETs

Two Independently Programmable Output Voltages

Fixed 3.3 V or Adjustable (1.25 V to VIN0.5 V)
Fixed 5 V or Adjustable (1.25 V to VIN0.5 V)

Programmable PWM Frequency
Integrated Linear Regulator Controller
Extensive Circuit Protection Functions
38-Lead TSSOP Package

APPLICATIONS
Notebook Computers and PDAs
Portable Instruments
General Purpose DC-DC Converters

GENERAL DESCRIPTION

The ADP3020 is a highly efficient dual synchronous buck switch-
ing regulator controller optimized for converting the battery or
adapter input into the system supply voltages required in note-
book computers. The ADP3020 uses a dual-mode PWM/Power
Saving Mode architecture to maintain efficiency over a wide
load range. The oscillator frequency can be programmed for
200 kHz, 300 kHz, or 400 kHz operation, or it can be synchro-
nized to an external clock signal of up to 600 kHz.

The ADP3020 provides accurate and reliable short circuit pro-
tection using an internal current sense circuit, which reduces
cost and increases overall efficiency. Other protection features
include programmable soft-start, UVLO, and integrated output
undervoltage/overvoltage protection. The ADP3020 contains a
linear regulator controller that is designed to drive an external
P-channel MOSFET or PNP transistor. The linear regulator
output is adjustable, and can be used to generate the auxiliary
voltages required in many laptop designs.

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ADP3020SPECIFICATIONS

(@ T

= 40 C to +85 C, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA,

REF Load = 0 mA, MODE = 0 V, SYNC = 0 V, SD = 5 V, unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INTERNAL 5 V REGULATOR

INTVCC

Input Voltage Range

5.5

5 V Voltage

= 25

°C

4.95

5.025

5.15

Line Regulation

5.5 V

VIN 25 V

0.3

mV/V

Total Variation

Line, Temp

4.8

5.2

Switchover Voltage

AUXVCC from Low to High

4.65

4.75

4.85

Switchover Hysteresis

AUXVCC from High to Low

100

Undervoltage Lockout

INTVCC Falling

3.6

3.8

4.2

Threshold Voltage
Undervoltage Lockout

120

Hysteresis

REFERENCE

Output Voltage

REF

5.5 V

VIN 25 V

1.185

1.197

1.209

SUPPLY CURRENT

Shutdown Current

SD = 0 V

µA

Standby Current

SS3 = SS5 = SD2 = 0 V

250

400

µA

SD = 5 V

Quiescent Current

No Loads, MODE = 5 V

0.95

1.8

(PWM Mode)

SS3 = SS5 = SD2 = 5 V
FB5 = FB3 = FB2 = 1.25 V,
ADJ/FX5 = ADJ/FX3 = 5 V

Quiescent Current

No Loads, MODE = 0 V

650

µA

(Power-Saving Mode)

SS3 = SS5 = SD2 = 5 V
FB5 = FB3 = FB2 = 1.25 V,
ADJ/FX5 = ADJ/FX3 = 5 V

OSCILLATOR

Frequency

OSC

SYNC = AGND

176

200

224

kHz

SYNC = REF

264

300

336

kHz

SYNC = INTVCC

352

400

448

kHz

SYNC Input

Frequency Range

230

600

kHz

Input Low Voltage

200 ns

0.4

Input High Voltage

200 ns

4.6

Input Current

SYNC = REF

1.2

µA

POWER GOOD

PWRGD

Output Voltage In Regulation

10 k

Pull-Up to 5 V

4.8

Output Voltage Out of Regulation

10 k

Pull-Up to 5 V

0.4

FB5

< 90% of Nominal

Output Value

PWRGD Trip Threshold

FB5 Rising

PWRGD Hysteresis

FB5 Falling

CPOR Pull-Up Current

CPOR = 1.2 V

2.5

µA

ERROR AMPLIFIER

DC Gain

Gain-Bandwidth Product

GBW

MHz

Input Leakage Current

EAN

ADJ/FX5 = ADJ/FX3 = 5 V

200

MAIN SMPS CONTROLLERS

Fixed 5 V Output Voltage

FB5

PWM Mode

5.5 V

VIN 25 V, ADJ/FX5 = 0 V

4.90

5.0

5.10

Power-Saving Mode

5.5 V

VIN 25 V, ADJ/FX5 = 0 V

4.925

5.025

5.125

Fixed 3.3 V Output Voltage

FB3

PWM Mode

5.5 V

VIN 25 V, ADJ/FX3 = 0 V

3.234

3.3

3.366

Power-Saving Mode

5.5 V

VIN 25 V, ADJ/FX3 = 0 V

3.250

3.316

3.382

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ADP3020

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Adjustable Output Voltage

PWM Mode

EAN5,

5.5 V

VIN 25 V,

1.173

1.197 1.221

EAN3

ADJ/FX5 = ADJ/FX3 = 5 V

Power-Saving Mode

FB5, FB3

5.5 V

VIN 25 V,

1.179

1.203 1.227

ADJ/FX5 = ADJ/FX3 = 5 V

Output Voltage Adjustment Range

FB5, FB3

ADJ/FX5 = ADJ/FX3 = 5 V

1.25

VIN0.5 V

Current Limit Threshold (PWM Mode)

CLSET5 = CLSET3 = Floating

5.5 V

VIN 25 V, T

= 25

°C

CLSET5 = CLSET3 = 0 V

5.5 V

VIN 25 V, T

= 25

°C

115

144

173

Current Limit Threshold

(Power-Saving Mode)

CLSET5 = CLSET3 = Floating

5.5 V

VIN 25 V, T

= 25

°C

CLSET5 = CLSET3 = 0 V

5.5 V

VIN 25 V, T

= 25

°C

Power-Saving Mode Trip Threshold

CLSET5 = CLSET3 = 0 V, T

= 25

°C

Soft-Start Current

SS3 = SS5 = 3 V

µA

Soft-Start Turn-On Threshold

SS5, SS3

0.7

1.2

1.8

Feedback Input Leakage Current

ADJ/FX5 = ADJ/FX3 = 5 V,

200

FB = 1.2 V

Maximum Duty Cycle

MAX

VIN = 5.5 V, SYNC = AGND

Transition Time (DRVH/DRVL)

Rise

LOAD

= 3000 pF, 10%90%

Fall

LOAD

= 3000 pF, 90%10%

Logic Input Low Voltage

MODE, SD, ADJ/FX3, ADJ/FX5

0.6

Logic Input High Voltage

MODE, SD, ADJ/FX3, ADJ/FX5

2.4

LINEAR REGULATOR CONTROLLER

Feedback Threshold

FB2

1.176

1.20

1.224

SD2 Pull-Up Current

SD2

SD2 = 1.2 V

µA

SD2 Threshold

0.7

1.2

1.8

Current Sinking Capability

DRV2

DRV2 = 2 V, FB2 = 1 V, SD2 = 5 V

FB2 Input Leakage Current

FB2 = 1.2 V

POWER-FAIL COMPARATOR

PFI Input Threshold

PFO from High to Low

1.176

1.20

1.224

PFI Input Hysteresis

PFI Input Current

200

PFO High Voltage

10 k

Pull-Up to 5 V

4.8

PFO Low Voltage

10 k

Pull-Up to 5 V

0.4

FAULT PROTECTION

Output Overvoltage Trip Threshold

With Respect to Nominal Output

115

120

125

Output Undervoltage Lockout Threshold

With Respect to Nominal Output

NOTES

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

The reference's line-regulation error is insignificant. The reference cannot be used for external load.

Guaranteed by design, not tested in production.

Specifications subject to change without notice.

ADP3020

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PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

CS5

Current Sense Input for top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of
the top N-channel MOSFET.

FB5

Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode.
Connect to an external resistor divider in adjustable output mode.

EAN5

Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation
only in fixed output mode. In adjustable output mode, connect to an external resistor divider.

EAO5

Error Amplifier Output for the 5 V Buck Converter.

ADJ/FX5

TTL Logic Input. When ADJ/FX5 = 0 V, fixed output mode, connect FB5 to the output sense point.
When ADJ/FX5 = 5 V, adjustable output mode, connect FB5 to the external resistor divider.

SS5

Soft Start for the 5 V Buck Converter. Also used as an ON/OFF Pin.

CLSET5

Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current
limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND.

REF

1.2 V Bandgap Reference. Bypass it with a capacitor (1 nF typical) to AGND. REF cannot be used
directly with an external load.

AGND

Analog Signal Ground.

CLSET3

Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current
limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND.

MODE

TTL Logic Input. MODE = 5 V, always in constant frequency PWM mode; MODE = 0 V, PWM
mode at moderate and heavy loads, and Power Saving (PSV) Mode at light load.

SYNC

Oscillator Synchronization and Frequency Select. f

OSC

= 200 kHz, when SYNC = 0 V; f

OSC

= 300 kHz, if

SYNC is tied to the REF Pin; f

OSC

= 400 kHz, when SYNC = 5 V. Oscillator can be synchronized with an

external source through the SYNC Pin.

SS3

Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF Pin

ADJ/FX3

TTL Logic Input. When ADJ/FX3 = 0 V, fixed output mode, connect FB3 to the output sense point.
When ADJ/FX3 = 5 V, adjustable output mode, connect FB3 to external resistor divider.

EAO3

Error Amplifier Output for the 3.3 V Buck Converter.

EAN3

Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation only in
fixed output mode. In adjustable output mode, connect to an external resistor divider.

FB3

Feedback Input for the 3.3 V Buck Converter. Connect to output sense point in fixed output mode.
Connect to an external resistor divider in adjustable output mode.

CS3

Current Sense Input for Top N-Channel MOSFET of the 3.3 V Buck Converter. It should be con-
nected to the drain of the N-channel MOSFET.

PFI

The () Input of a comparator that can be used as a power fail detector. The positive input is connected
to the 1.20 V reference. There is a 24 mV hysteresis for this comparator.

PFO

Open Drain Output. This pin will sink current when the PFI pin is lower than 1.20 V. Otherwise, PFO
is floating.

PWRGD

Power Good Output. PWRGD goes low with no delay, whenever the 5 V output drops 8% below its
nominal value. When the 5 V output is within 4% of its nominal value, PWRGD will be released after a
time delay determined by the timing capacitor on the CPOR pin.

CPOR

Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 2.5

µA

pull-up current is used to charge the capacitor. A manual reset (MR) function can also be implemented
by grounding this pin.

SD2

Shutdown input for the Linear Regulator Controller.

FB2

Feedback for the Linear Regulator Controller.

DRV2

Open Collector Output for the Linear Regulator Controller.

BST3

Boost Capacitor Connection for High Side Gate Driver of the 3.3 V Buck Converter.

DRVH3

High Side Gate Driver for 3.3 V Buck Converter.

SW3

Switching Node (Inductor) Connection of the 3.3 V Buck Converter.

DRVL3

Low Side Gate Driver of 3.3 V Buck Converter.

VIN

Main Supply Input (4.5 V to 25 V).

ADP3020

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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3020 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS (Continued)

Pin No.

Mnemonic

Function

INTVCC

Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7

µF capacitor to AGND.

AUXVCC

Supply Switch Over. When AUXVCC > 4.75 V, and both of the switchers are in Power Saving mode,
the internal 5 V LDO is turned off. The chip is powered by AUXVCC pin. There is a 2% hysteresis for
this pin.

Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent cur-
rent. For automatic start-up, connect SD to V

directly.

PGND

Power Ground.

DRVL5

Low Side Driver for 5 V Buck Converter.

SW5

Switching Node (Inductor) Connection for 5 V Buck Converter.

DRVH5

High Side Gate Driver for 5 V Buck Converter.

BST5

Boost Capacitor Connection for High Side Gate Driver of the 5 V Buck Converter.

ABSOLUTE MAXIMUM RATINGS

VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +27 V
AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.3 V

INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND 0.3 V to +6 V
BST5, BST3 to PGND . . . . . . . . . . . . . . . . . 0.3 V to +32 V
BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND 0.3 V to VIN
SW3, SW5 to PGND . . . . . . . . . . . . . . 0.3 V to VIN + 0.3 V
SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND 0.3 V to +27 V
DRVL5/3 to PGND . . . . . . . . . 0.3 V to (INTVCC + 0.3 V)
DRVH5/3 to SW5/3 . . . . . . . . . 0.3 V to (INTVCC + 0.3 V)
All Other Inputs and Outputs

. . . . . . . . . . . . . . . . . . AGND 0.3 V to INTVCC + 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

°C/W

Operating Ambient Temperature Range . . . . 40

°C to +85°C

Junction Temperature Range . . . . . . . . . . . . 40

°C to +150°C

Storage Temperature Range . . . . . . . . . . . . 65

°C to +150°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300

°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

PIN CONFIGURATION

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADP3020ARU

°C to +85°C

Thin Shrink Small Outline

RU-38

TOP VIEW

(Not to Scale)

ADP3020

BST5

DRVH5

SW5

DRVL5

PGND

AUXVCC

INTVCC

VIN

DRVL3

SW3

DRVH3

BST3

DRV2

FB2

SD2

CPOR

PWRGD

CS5

FB5

EAN5

EAO5

PFI

SS5

CLSET5

REF

AGND

CLSET3

MODE

SYNC

SS3

PFO

EAO3

EAN3

FB3

CS3

ADJ/

FX3

ADJ/

FX5

ADP3020

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INPUT VOLTAGE V

CURRENT

200

250

300

100

150

+25 C

40 C

+85 C

Figure 8. Input Standby Current vs. Input Voltage

INPUT VOLTAGE V

CURRENT

+25 C

40 C

+85 C

Figure 9. Input Shutdown Current vs. Input Voltage

AMBIENT TEMPERATURE C

40

FREQUENCY

kHz

10

295

315

290

305

300

310

SYNC = REF

= 25

= 12

= 7.5

= 5.5

Figure 10. PWM Mode Oscillator Frequency vs.
Temperature

AMBIENT TEMPERATURE C

40

CURRENT LIMIT THRESHOLD

30 20 10

250

150

100

200

= 5.5V TO 25V

CLSET = GND

Figure 11. Current Limit Threshold vs. Temperature

AMBIENT TEMPERATURE C

40

REFERENCE OUTPUT

30 20 10

1.180

1.210

1.190

1.185

1.195

1.200

1.205

= 5.5V TO 25V

Figure 12. Reference Output vs. Temperature

CH1

3.3V

OUTPUT

CH2

2.5V

OUTPUT

CH3

SS3

CH4

SS5

[

]

CH1

2.00V

CH2

1.00V

200

CH4

740mV

CH3

1.00V

CH4

1.00V

12V

TEK STOP: SINGLE SEQ 250 S/s

Figure 13. Soft-Start Sequencing

ADP3020

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THEORY OF OPERATION

The ADP3020 is a dual-mode, step-down power supply controller
for notebook computers or similar battery-powered applications.
The device contains two synchronous step-down buck control-
lers and a linear regulator controller. The buck controllers in the
ADP3020 have the ability to provide either fixed 3.3 V and 5 V
outputs or independently adjustable (1.25 V to VIN0.5 V) out-
puts. High efficiency over a broad load range is achieved by using a
proprietary dual-mode PWM/power-saving (PSV) mode architec-
ture. Efficiency is further improved by deleting the external current
sense resistor, which is the main contributor to loss during high
current, low output voltage conditions.

CIRCUIT DESCRIPTION
Dual-Mode Architecture

The ADP3020 contains two independent dual-mode, synchro-
nous buck controllers. Traditional constant frequency PWM
buck converters suffer from relatively low efficiency under light
load conditions. In order to maintain high efficiency over a wide
load range, the ADP3020 uses a proprietary dual-mode archi-
tecture. At moderate to heavy loads, the buck converter operates
in the traditional Pulsewidth Modulation (PWM) mode. At light
loads, PSV mode is used to increase system efficiency. A propri-
etary detection scheme is used for transition from one mode to the
other. Input current to the high-side MOSFET is detected when
going from PWM mode to PSV mode, and output voltage infor-
mation is used when changing from PSV mode to PWM mode.

When the high-side N-channel MOSFET is turned on, the current
going through the N-channel MOSFET is measured as a voltage
between CS and SW. If the peak current through the MOSFET
is less than 20% of the current limit value set by CLSET, an
internal counter that is based on the oscillator frequency will be
started. If the current stays below this threshold for 16 PWM
cycles, the buck converter will enter power-saving mode. The
counter will automatically reset if the peak current is higher than
20% of the current limit value any time prior to when the counter
reaches 16.

In PSV mode, the buck converter works like a window regula-
tor. If the output voltage drops below the PWM mode nominal
output voltage, the high-side MOSFET will be turned on. It will
remain on until the output capacitors are charged up to 2%
above the PWM mode nominal output voltage. The high-side
MOSFET will then be latched off until the output capacitors are
discharged to the lower threshold. The discharge rate is depen-
dent on the output capacitor value and load current.

It is important to note that the current limit threshold when in
PSV mode is approximately 1/4 of the current limit threshold
when in PWM mode. If a large load is applied to the converter
when in PSV mode (for example, larger than the current limit in
PSV mode), the output will continue to drop due to the lower
current limit threshold of PSV mode. When the output voltage
drops to 2% below the PWM mode nominal voltage, the converter
will automatically return to PWM mode. Once in PWM mode,
the current limit is quadrupled, and the output will be charged
up to the nominal level, as long as the load does not exceed the
higher PWM current limit.

PWM/PSV Operation (MODE)

Table I shows the summary of the operating modes of the synchro-
nous buck controllers. The MODE pin determines whether or not
the controllers remain in PWM mode under all load conditions.

MODE can be driven by an external TTL logic signal. When
MODE is pulled HIGH, PSV mode operation is disabled, and
the system is always in constant frequency PWM mode. In order
to enable PSV mode at light loads, the MODE pin needs to be
pulled LOW.

Table I. PWM Mode and PSV Mode

Load

Operating

Mode

Current

Mode

Description

High

PWM

Constant-Frequency PWM

Low

Heavy

PWM

Constant-Frequency PWM

Low

Moderate

PWM

Constant-Frequency PWM

Low

Light

PSV

Variable-Frequency, Burst
Mode

X = Don't Care.

Forcing the ADP3020 to always remain in constant frequency
PWM mode can be used to reduce interference, as this allows
filtering of the fixed fundamental frequency and its harmonics.
The operating frequency should be carefully chosen so that both
the fundamental and harmonic frequencies are not within sensitive
audio or IF bands. This is particularly important in noise-sensitive
applications such as multimedia systems, cellular phones, com-
puters with built-in RF communications, and PDAs. If two or
more switching regulators are used in a system, it is best to syn-
chronize all the switching regulators to a single master regulator
or an external clock signal.

Internal 5 V Supply (INTVCC)

An internal low dropout regulator (LDO) generates a 5 V supply
(INTVCC) that powers all of the functional blocks within the
IC. The total current rating of this LDO is 50 mA. However,
this current is used for supplying gate-drive power, and it is not
recommended that current be drawn from this pin for other
purposes. Bypass INTVCC to AGND with a 4.7

µF capacitor.

A UVLO circuit is also included in the regulator. When INTVCC
< 3.8 V, the two switching regulators and the linear regulator
controller are shut down. The UVLO hysteresis voltage is about
120 mV. The internal LDO has a built-in fold-back current
limit, so that it will be protected if a short circuit is applied to
the 5 V output.

If AUXVCC is higher than 4.75 V, and both the 5 V and 3.3 V
switching regulators are in PSV mode, an internal switch will
connect INTVCC to AUXVCC, while simultaneously turning
off the internal LDO. AUXVCC can be tied to either the 5 V
switching regulator output or a separate 5 V voltage source. By
doing this, the power loss across the internal LDO is eliminated,
and the total efficiency in PSV mode is improved.

When AUXVCC = GND, this automatic power switchover fea-
ture will be disabled.

Internal Reference (REF)

The ADP3020 contains a precision 1.2 V bandgap reference.
Bypass REF to AGND with a 1 nF ceramic capacitor. The ref-
erence is intended for internal use only. An external voltage
buffer is needed if the reference is used for another purpose.

Boost High Side Gate Drive Supply (BST)

The gate drive voltage for the high-side N-channel MOSFETs is
generated by a flying-capacitor boost circuit. The boost capacitor
connected between BST and SW is charged from the INTVCC
supply. Use only small-signal diodes for the boost circuit.

ADP3020

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Synchronous Rectifier (DRVL)

Synchronous rectification is used to reduce conduction losses
and to ensure proper start-up of the boost gate driver circuit.
Antishoot-through protection has been included to prevent cross
conduction during switch transitions. The low side driver must
be turned off before the high side driver is turned on. For typi-
cal N-channel MOSFETs, the dead time is about 50 ns. On the
other edge, a dead time of about 50 ns is achieved by an internal
delay circuit. The synchronous rectifier is turned off when the
current flowing through the low-side MOSFET falls to zero when
in Discontinuous Conduction (DCM) PWM mode and PSV mode.
In Continuous Conduction (CCM) PWM mode, the current
flowing through the low-side MOSFET never reaches zero, so the
synchronous rectifier is turned off by the next clock cycle.

Oscillator Frequency and Synchronization (SYNC)

The SYNC pin controls the oscillator frequency. When SYNC
= 0 V, f

OSC

= 200 kHz ; when SYNC = REF, f

OSC

= 300 kHz;

when SYNC = 5 V, f

OSC

= 400 kHz. 400 kHz operation will

minimize external component size and cost while 200 kHz opera-
tion provides better efficiency and lower dropout. The SYNC
pin can also be used to synchronize the oscillator with an exter-
nal 5 V clock signal. A low-to-high transition on SYNC initiates
a new cycle. Synchronization range is 230 kHz to 600 kHz.

Shutdown (SD)

Holding SD = GND low will put the ADP3020 into ultralow
current shutdown mode. For automatic start-up, SD can be tied
directly to VIN.

Soft-Start and Power-Up Sequencing (SS)

SS3 and SS5 are soft start pins for the two controllers. A 4

µA

pull-up current is used to charge an external soft start capacitor.
Power-up sequencing can be easily done by choosing different
size external capacitors. When SS3/SS5 < 1.2 V, the two switch-
ing regulators are turned off. When 1.2 V < SS5/SS3 < 2.6 V,
the regulators start working in soft start mode. When SS3/SS5 >
2.6 V, the regulators are in normal operating mode. The con-
trollers are forced to stay in PWM mode during the soft-start
period. The minimum soft-start time (~20

µs) is set by an inter-

nal capacitor. Table II shows the ADP3020 operating modes.

Current Limiting (CLSET)

A cycle-by-cycle current limiting scheme is used by monitoring
current through the top N-channel MOSFET when it is turned
on. By measuring the voltage drop across the high-side MOSFET
V

DS(ON)

, the external sense resistor can be deleted. The current

limit value can be set by CLSET. When CLSET = Floating, the
maximum V

DS(ON)

= 72 mV at room temperature; when CLSET

= 0 V, the maximum V

DS(ON)

= 144 mV at room temperature. An

external resistor can be connected between CLSET and AGND
to choose a value between 72 mV and 144 mV. The temperature

coefficient of R

DS(ON)

of the N-channel MOSFET is canceled by

the internal current limit circuitry, so that an accurate current
limit value can be obtained over a wide temperature range. In
PSV mode, the current limit value is reduced to about 1/4 of
the value in PWM mode to reduce the interference noise to other
components on the PC board.

Output Undervoltage Protection

Each switching controller has an undervoltage protection circuit.
When the current flowing through the high-side MOSFET
reaches the current limit continuously for eight clock cycles,
and the output voltage is below 20% of the nominal output
voltage, both controllers will be latched off and will not restart
until SD or SS3/SS5 is toggled, or until VIN is cycled below 4 V.
This feature is disabled during soft start.

Output Overvoltage Protection

Both converter outputs are continuously monitored for overvolt-
age. If either output voltage is higher than the nominal output
voltage by more than 20%, both converter's high-side gate drivers
(DRVH5/3) will be latched off, and the low-side gate drivers
will be latched on, and will not restart until SD or SS5/SS3 are
toggled, or until VIN is cycled below 4 V. The low-side gate
driver (DRVL) is kept high when the controller is in off-state
and the output voltage is less than 93% of the nominal output
voltage. Discharging the output capacitors through the main
inductor and low-side N-channel MOSFET will cause the out-
put to ring. This will make the output momentarily go below
GND. To prevent damage to the circuit, use a reverse-biased
1 A Schottky diode across the output capacitors to clamp the
negative surge.

Power Good Output (PWRGD)

The ADP3020 also provides a PWRGD signal for the micropro-
cessor. During start-up, the PWRGD pin is held low until 5 V
output is within 4% of its preset voltage. Then, after a time
delay determined by an external timing capacitor connected from
CPOR to GND, PWRGD will be actively pulled up to INTVCC
by an external pull-up resistor. CPOR can also be used as a
manual reset (MR) function. When the 5 V output is lower than
the preset voltage by more than 8%, PWRGD is immediately
pulled low.

Linear Regulator Controller

The ADP3020 includes an onboard linear regulator controller.
An external PNP transistor can be used for operation up to 1 A.
For higher output current applications, a low threshold PMOS
can be used as the pass transistor. The output voltage can be set
by a resistor divider. The minimum output voltage of the LDO
is 1.25 V, while the maximum output voltage depends on where
the LDO input is connected and the dropout voltage of the
external pass transistor.

Table II. Operating Modes

SS5

SS3

Mode

Description

Low

Shutdown

All Circuits Turned Off

High

SS5 < 1.2 V

SS3 < 1.2 V

Standby

5 V and 3.3 V Off; INTVCC = 5 V, REF = 1.2 V

High

1.2 V < SS5 < 2.6 V

Run

5 V in Soft Start

High

2.6 V < SS5

Run

5 V in Normal Operation

High

1.2 V < SS3 < 2.6 V

Run

3.3 V in Soft Start

High

2.6 V < SS3

Run

3.3 V in Normal Operation

ADP3020

REV. 0

Output Voltage Adjustment

Fixed output voltages (5 V and 3.3 V) are selected when
ADJ/FX5 = ADJ/FX3 = 0 V. The output voltage of each con-
troller can also be set by an external feedback resistor network
when ADJ/FX5 = ADJ/FX3 = 5 V as shown in Figure 18. There
should be two external feedback resistor dividers for each con-
troller, one for the voltage feedback loop, and one for output
voltage monitor. Both resistor dividers need to be identical. The
minimum output voltage is 1.25 V. The maximum output volt-
age is limited only by the minimum supply voltage. Remote
output voltage sensing can be done for both fixed and adjustable
output voltage modes.

The output voltage can be calculated using the following formula:

REF

OUT

(1)

where REF = 1.2 V, and R1/R2 = R3/R4.

ADP3020

DRVH

DRVL

ADJ/

EAN

OUT

Figure 18. Adjustable Output Mode

If the loop is carefully compensated, R3 and R4 can be, removed,
and FB and EAN can be tied together.

APPLICATION INFORMATION

A typical notebook PC application circuit using the ADP3020 is
shown in Figure 19. Although the component values given in
Figure 19 are based on a 5 V @ 4 A /3.3 V @ 4 A/2.5 V @ 1.5 A
design, the ADP3020 output drivers are capable of handling out-
put currents anywhere from <1 A to over 10 A. Throughout this
section, design examples and component values will be given for
three different power levels. For simplicity, these levels will be
referred to as low power, basic, and extended power. Table
III shows the input/output specifications for these three levels.

Table III. Typical Power Level Examples

Extended

Low Power

Basic

Power

Input Voltage

Range

5.5 V to 25 V

Switching

Output 1

3.3 V/2 A

3.3 V/4 A

3.3 V/10 A

Switching

Output 2

5 V/2 A

5 V/4 A

5 V/10 A

Linear Output

2.5 V/1 A

2.5 V/1.5 A

2.5 V/2 A

Input Voltage Range

The input voltage range of the ADP3020 is 5.5 V to 25 V when
5 V output is desired, and 4.5 V to 25 V when neither switcher
output is >4.0 V. This converter design is optimized to deliver
the best performance within a 7.5 V to 18 V range, which is the
nominal voltage for three to four cell Li-Ion battery stacks. Volt-
ages above 18 V may occur under light loads and when the
system is powered from an ac adapter with no battery installed.

Maximum Output Current and MOSFET Selection

The maximum output current for each switching regulator is lim-
ited by sensing the voltage drop between the drain and source of
the high-side MOSFET when it is turned on. A current sense
comparator senses voltage drop between CS5 and SW5 for the
5 V converter and between CS3 and SW3 for the 3.3 V converter.
The sense comparator threshold is 72 mV when the program-
ming pin, CLSET, is floating, and is 144 mV when CLSET is
connected to ground. Current-limiting is based on sensing the
peak current. Peak current varies with input voltage and depends
on the inductor value. The higher the ripple current or input
voltage, the lower the converter maximum output current at the
set current sense amplifier threshold. The relation between peak
and dc output current is given by:

PEAK

OUT

IN MAX

OUT

IN MAX

× ×

(

)

(

)

(2)

At a given current comparator threshold V

and MOSFET

DS(ON)

, the maximum inductor peak current is:

PEAK

DS ON

(

)

(3)

Rearranging Equation 2 to solve for I

OUT(MAX)

gives:

OUT MAX

DS ON

OUT

IN MAX

OUT

IN MAX

(

)

(

)

(

)

(

)

× ×

(4)

Normally, V

should be set to its maximum value of 144 mV.

For example, in the circuit of Figure 19, an Si4410, which has
an R

DS(ON)

of 13.5 m

would have a maximum peak current

limit of around 10 A. A less efficient way to achieve maximum
power from the converter is to design the inductor with a larger
inductance, (i.e., a lower ripple current). This helps reduce
the peak-to-dc current ratio and increases maximum converter
output, but may also increase the inductor value and its size.
It is important to remember that this current limit circuit is
designed to protect against high current or short circuit condi-
tions only. This will protect the IC and MOSFETs long enough
to allow the output undervoltage protection circuitry to latch off
the supply.

ADP3020

REV. 0

C14A

10 F

C14B

10 F

D2
10BQ040

6.8 H

130k

CS5

FB5

EAN5

EAO5

ADJ/

FX5

SS5

CLSET5

BST5

DRVH5

SW5

DRVL5

PGND

AUXVCC

INTVCC

VIN

DRVL3

SW3

DRVH3

BST3

DRV2

FB2

SD2

CPOR

PWRGD

PFO

REF

AGND

CLSET3

MODE

SYNC

SS3

ADJ/

FX3

EAO3

EAN3

FB3

CS3

PFI

ADP3020

68pF

R10

10k

C18

150pF

1 F

R11

6.2k

C19

330pF

D6
1N4148

C17
100nF

SI4410

C16
1 F

R6
10

D4
10BQ040
(OPTIONAL)

C27A
68 F

C27B
68 F

OUT5

5V, 4A

D3
10BQ040
(OPTIONAL)

C24A
68 F

C24B
68 F

OUT33

3.3V, 4A

SI4410

100nF

C15
4.7 F

C13
1 F

C20A

10 F

C20B

10 F

D1
10BQ040

6.8 H

C26
4.7 F

OUT25

2.5V, 1.5A

R9
47k

C28
1 F

R17

13k

R7
12k

C11
33 F

R24

210k

R26
60.4k

C12

R12

10k

R13

10k

PWRGD

PFO

R14

4.7

C22
4.7 F

VIN

5.5V-25V

47k

1nF

75k

470pF

68pF

1 F

1N4148

330pF

IRF7404

Figure 19. 45 W, Triple Output DC-DC Converter

ADP3020

REV. 0

Nominal Inductor Value

The inductor design is based on the assumption that the induc-
tor ripple current is 30% of the maximum output dc current at
nominal 12 V input voltage. The inductor ripple current and
inductance value are not critical, but this choice is quite impor-
tant in analyzing the trade-offs between cost, size, efficiency,
and volume. The higher the ripple current, the lower the induc-
tor size and volume. However, this will lead to higher ac losses
in the windings. Conversely, a higher inductor value means
lower ripple current and smaller output filter capacitors, but
transient response will be slower.

The design of the inductor should be based on the maximum
output current plus 15% (1/2 of the 30% ripple allowance) at
the nominal input voltage:

IN NOM

OUT

IN NOM

OUT

(

)

(

)

(

)

(5)

Optimum standard inductor values for the three power levels are
shown in Table IV.

Table IV. Standard Inductor Values

Freq.

3.3 V/2 A 3.3 V/4 A 3.3 V/10 A 5 V/2 A 5 V/4 A 5 V/10 A

200 kHz 20

µH

8.2

µH

3.3

µH

4.7

µH

300 kHz 12

µH

6.8

µH

2.2

µH

8.2

µH 3.3 µH

400 kHz 10

µH

4.7

µH

1.5

µH

6.8

µH 2.2 µH

Inductor Selection

Once the value for the inductor is known, there are two ways to
proceed; either to design the inductor in-house or to buy the
closest inductor that meets the overall design goals.

Standard Inductors

Buying a standard inductor will provide the fastest, easiest solu-
tion, and many companies offer suitable power inductor solutions.
A list of power inductor manufacturers is given in Table V.

DESIGNING THE INDUCTOR IN-HOUSE
Core Material Concerns

There are several good choices for low core loss materials at
high frequency. Two examples are distributed gap Kool Mu
powdered cores from Magnetics and soft ferrite cores, material
3F3, 3F4, 3D3, or 4C4, from Philips. To minimize the ac core
loss, especially when the inductor value is relatively low and
ripple current is high, the use of low frequency powdered iron
cores and low frequency ferrite cores (specified for frequency up
to 100 kHz) should be avoided. The ripple current is a key fac-
tor for optimization of the converter design and determines core
losses to a large extent. Selecting a high ripple current means
a relatively low inductor value. This, for a given core size,
reflects a lower number of turns and higher core loss.

Core Geometry

There are two main categories of ferromagnetic cores that could
be used in this type of application. Open magnetic loop types
such as beads, beads on leads, rods, and slugs provide the low-
est cost, but do not have focused magnetic fields in the core.
The radiated EMI distributed around the magnetic field may
create problems with noise interference in electronic circuits
surrounding the choke. Other types are cores with closed mag-
netic paths, such as pot cores, PQ, U, and E cores, toroids, etc.
The cost of these cores is higher, but EMI and RFI performance
is better. A good compromise between price and performance
are cores with a toroidal shape, used primarily in through-hole
printing board designs. A very cost-effective solution based, not
on closed-loop core, but on good shielded open-loop core, are
surface-mount power inductors, DO, DT, and DS Series from
Coilcraft.

Table V. Recommended Inductor Manufacturers

Murata Electronics

Coilcraft

Coiltronics

North America Inc.

Phone: 847/639-6400

Phone: 561/241-7876

Phone: 770/436-1300

Fax: 847/639-1469

Fax: 561/241-9339

Fax: 770/436-3030

Web: www.coilcraft.com

Web: www.coiltronics.com

Web: www.murata.com

SMT Power Inductors,

Series 1608, 3308, 3316, 5022, 5022HC,

Series UNI-PAC2, UNI-PAC3 and UNI-PAC4,

Series LQT2535

DO3340, Low Cost Solution

Low Cost Solution

Best for Low EMI/RFI

SMT Shielded Power Inductors,

SMT Power Inductors,

Series DS5022, DS3316, DT3316,

Series, ECONO-PAC, VERSA-PAC,

Best for Low EMI/RFI

Best for Low Profile or Flexible Design.

Power Inductors and Chokes,

Power Inductors CTX Series,

Chip Inductors

Series DC1012, PCV-0, PCV-1, PCV-2,

Low EMI/RFI, Low Cost Toroidal Inductors

LQN6C, LQS66C

PCH-27, PCH-45, Low Cost

but Not Miniature.

ADP3020

REV. 0

The Design

The details of designing the power inductor are covered in many
reference texts, and will not be covered here. Examples of soft-
ware and reference books that can be used for quick design of
the power inductor are given below:

Software--Magnetic Designer from Intusoft, www.intusoft.com

"Designing Magnetic Components for High Frequency
DC-DC Converters," McLyman, Kg Magnetics Inc.,
ISBN 1-883107-00-08 (for advanced users)

"Power Supply Cookbook," Marty Brown, EDN Series for
Design Engineers, ISBN 0-7506-9442-4 (for beginners and
intermediate users)

and C

OUT

Selection

In continuous conduction mode, the source current of the upper
MOSFET is approximately a square wave of duty cycle V

OUT

To prevent large voltage transients, a low ESR input capacitor
sized for the maximum rms current must be used. The maximum
rms capacitor current is given by:

RMS

OUT

MAX

(

)

(6)

This formula has a maximum at V

= 2

× V

OUT

, where I

RMS

OUT

/2. Note that the capacitor manufacturer's ripple current

ratings are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a capacitor
rated at a higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the
design. If electrolytic or tantalum capacitors are used, an addi-
tional 0.1

µF1 µF ceramic bypass capacitor should be placed in

parallel with C

The selection of C

OUT

is driven by the required effective series

resistance (ESR) and the desired output ripple. A good rule of
thumb is to limit the ripple voltage to 1% of the nominal output
voltage. It is assumed that the total ripple is caused by two factors:
25% comes from the C

OUT

bulk capacitance value, and 75%

comes from the capacitor ESR. The value of C

OUT

can be deter-

mined by:

OUT

RIPPLE

× ×

(7)

where I

RIPPLE

= 0.3

× I

OUT

and V

RIPPLE

= 0.01

× V

OUT

. The

maximum acceptable ESR of C

OUT

can then be found using:

ESR

RIPPLE

0 75

(8)

Manufacturers such as Vishay, AVX, Elna, WIMA and Sanyo
provide good high-performance capacitors. Sanyo's OSCON
semiconductor dielectric capacitors have lower ESR for a given
size, at a somewhat higher price. Choosing sufficient capacitors
to meet the ESR requirement for C

OUT

will normally exceed

the amount of capacitance needed to meet the ripple current
requirement.

In surface-mount applications, multiple capacitors may have to
be paralleled to meet the capacitance, ESR, or RMS current
handling requirements. Aluminum electrolytic and dry tantalum
capacitors are available in surface-mount configurations. In the
case of tantalum, it is critical that capacitors are surge tested for
use in switching power supplies. Recommendations for output
capacitors are shown in Table VI.

Power MOSFET Selection

N-channel power MOSFETs must be selected for use with the
ADP3020 for both the main and synchronous switch. The main
selection parameters for the power MOSFETs are the threshold
voltage (V

GS(TH)

) and ON-resistance (R

DS(ON)

). An internal LDO

generates a 5 V supply that is boosted above the input voltage
using a bootstrap circuit. This floating 5 V supply is used for the
upper MOSFET gate drive. Logic-level threshold MOSFETs
must be used for both the main and synchronous switches.

Maximum output current (I

MAX

) determines the R

DS(ON)

require-

ment for the two power MOSFETs. When the ADP3020 is
operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting the
load current. The duty cycles for the MOSFETs are given by:

Upper MOSFET Duty Cycle

OUT

(9)

Lower MOSFET Duty Cycle

OUT

(10)

Table VI. Recommended Capacitor Manufacturers

Maximum Output
Current

2 A

4 A

10 A

Input Capacitors

TOKIN Multilayer

Ceramic Caps, 22

µF/25 V

Ceramic Caps, 2

× 22 µF/25 V

Ceramic Caps, 2

× 22 µF/25 V

P/N: C55Y5U1E226Z

TAIYO YUDEN INC.

VISHEY Ceramic Caps,

Ceramic Caps, Y5V Series

Z5U Series, 2

× 15 µF/25 V

µF/25 V

×10 µF/25 V

P/N: TMK432BJ106KM

Output Capacitors

SANYO POSCAP TPC

SANYO POSCAP TPB

+3.3 V Output

Series, 68

µF/10 V

Series, 2

× 68 µF/10 V

Series, 2

× 220 µF/4.0 V

Output Capacitors

SANYO POSCAP TPC

SANYO POSCAP TPB

+5 V Output

Series, 68

µF/10 V

Series, 2

× 68 µF/10 V

Series, 2

× 330 µF/6.3 V

ADP3020

REV. 0

From the duty cycle, the required minimum R

DS(ON)

for each

MOSFET can be derived by the following equations:

Upper MOSFET:

Upper

DS ON

OUT

MAX

(

)

(

)

× +

(

)

(11)

Lower MOSFET:

Lower

DS ON

OUT

MAX

(

)

(

)

(

)

× +

(

)

(12)

where P

is the allowable power dissipation and

is the tempera-

ture dependency of R

DS(ON)

. P

will be determined by efficiency

and/or thermal requirements (see Efficiency ). (1 +

T) is gen-

erally given for a MOSFET in the form of a normalized R

DS(ON)

vs. temperature curve, but

= 0.007/°C can be used as an

approximation for low voltage MOSFETs.

Maximum MOSFET power dissipation occurs at maximum
output current, and can be calculated as follows:

Upper MOSFET:

Upper

OUT

MAX

DS ON

(

)

(

)

(

)

× +

(13)

Lower MOSFET:

Lower

OUT

MAX

DS ON

(

)

(

)

(

)

× +

(14)

The Schottky diode, D1 shown in Figure 19, conducts only during
the dead time between conduction of the two power MOSFETs.
D1's purpose is to prevent the body-diode of the lower N-channel
MOSFET from turning on and storing charge during the dead
time, which could cost as much as 1% in efficiency. D1 should
be selected for forward voltage of less than 0.5 V when conducting
I

MAX

. Recommended transistors for upper and lower MOSFET's

are given in Table VII.

Table VII. Recommended MOSFETs

Maximum
Output

2 A

4 A

10 A

Vishay/

Si4412DY,

Si4410DY,

Si4874DY,

Siliconix

28 m

13.5 m

7.5 m

International

IRF7805,

IRF7811,

IRFBA3803,

Rectifier

11 m

8.9 m

5.5 m

IRF7805,

IRF7809,

11 m

7.5 m

Soft Start

The soft-start time of each of switching regulator can be pro-
grammed by connecting a soft-start capacitor to the corresponding
soft-start pin (SS3 or SS5). The time it takes each regulator to
ramp up to its full duty ratio depends proportionally on the
values of the soft-start capacitors. The charging current is 4

µA

±20%. The capacitor value to set a given soft-start time, t

, is

given by:

µ ×

( )

2 6

(

)

(15)

Fixed or Adjustable Output Voltage

Each switching controller of the ADP3020 can be programmed
to operate with a fixed or adjustable output voltage. As shown
by the general application schematic in Figure 19, putting the
ADP3020 into fixed mode gives a nominal output of 3.3 V and
5 V for the two switching buck converters. By using two identi-
cal resistor dividers per converter, any output voltage between
1.25 V and VIN0.5 V can be set. The center point of one divider
is connected to the feedback pin, FB, and the center point of the
other identical divider is connected to EAN. It is important to use
1% resistors. A good value for the lower leg resistors is 10 k

1%, then the upper leg resistors for a given output voltage can
be determined by:

UPPER

OUT

(

)

1 2

0 12

(16)

Table VIII shows the resistor values for the most common out-
put voltages.

Table VIII. Typical Feedback Resistor Values

OUT

1.25 V

1.3 V

1.5 V

1.8 V

2.0 V

2.5 V

3.0 V

3.3 V

5.0 V

UPPER

412

825

2.49 k

4.99 k

6.65 k

10.7 k

15.0 k

17.4 k

31.6 k

LOWER

10 k

ADP3020

REV. 0

PWM Mode/Power-Saving (PSV) Mode Operation

The mode of operation for both switching regulators can be preset
using the MODE pin. When MODE is HIGH, or connected to
INTVCC, both converters work only in PWM mode, regardless
of output current. MODE connected to GND makes both con-
verters operate in a dual PWM/PSV mode of operation. In dual
mode, each converter has its own boundary output current when
the converter switches from PSV mode to PWM mode and vice
versa. There is an output current hysteresis for each mode tran-
sition to avoid improper operation.

There are several design recommendations regarding dual mode
operation. The trip output current level for switching between
PWM mode and PSV mode is a percentage of the peak current
sensed via the internal current sense comparator. However,
the value of that current depends on the R

DS(ON)

of the upper

MOSFET. For example, if the design uses an Si4420 versus an
Si4410 power MOSFET (9 m

vs. 13.5 m) the maximum

output power of the converter and the mode trip output current
will both be 50% higher.

Efficiency Enhancement

The efficiency of each switching regulator is inversely propor-
tional to the losses during the switching conversion. The main
factors to consider when attempting to maximize efficiency are:

1. Resistive losses, which include the R

DS(ON)

of upper and

lower MOSFETs, trace resistances and output choke wire
resistance.

These losses contribute a major part of the overall power loss
in low voltage battery-powered applications. However, trying
to reduce these resistive losses by using multiple MOSFETs
and thick traces may tend to lead to lower efficiency and higher
price. This is due to the trade-off between reduced resistive
loss and increased gate drive loss that must be considered
when optimizing efficiency.

2. Switching losses due to the limited time of switching transitions.

This occurs due to gate drive losses of both upper and lower
MOSFETs, and switching node capacitive losses, as well as
through hysteresis and eddy-current losses in power choke.
Input and output capacitor ripple current losses should also
be considered as switching losses. These losses are input-
voltage-dependent and can be estimated as follows:

SWLOSS

MAX

2 5

1 85

(17)

where C

is the overall capacitance of the switching node

related to loss.

3. Supply current of the switching controller (independent of

the input current redirected to supply the MOSFETs' gates).

This is a very small portion of the overall loss, but it does
increase with input voltage.

Transient Response Considerations

Both stability and regulator loop response can be checked by
looking at the load transient response. Switching regulators take
several cycles to respond to a step in output load current. When
a load step occurs, output voltage shifts by an amount equal to
the current step multiplied by the total ESR of the summed output
capacitor array. Output overshoot or ringing during the recovery
time (in both directions of the current step change) indicates a
stability problem. The external feedback compensation compo-
nents shown in Figure 18 should provide adequate
compensation for most applications.

Feedback Loop Compensation

The ADP3020 uses Voltage Mode control to stabilize the switch-
ing controller outputs. Figure 20 shows the voltage mode control
loop for one of the buck switching regulators. The internal refer-
ence voltage V

REF

is applied to the positive input of the internal

error amplifier. The other input of the error amplifier is EAN,
and is internally connected to the feedback sensing pin FB via an
internal resistor. The error amplifier creates the closed-loop
voltage level for the pulsewidth modulator that drives the external
power MOSFETs. The output LC filter smooths the pulse-
width modulated input voltage to a dc output voltage.

OUT

PWM

COMPARATOR

ADP3020

VIN

DRVH

DRVL

PARASITIC

ESR

EAO

EAN

REF

RAMP

Figure 20. Buck Regulator Voltage Control Loop

The pulsewidth modulator transfer function is V

OUT

/VEA

OUT

where VEA

OUT

is the output voltage of the error amplifier. That

function is dominated by the impedance of the output filter with
its double-pole resonance frequency (f

) and a single zero at

output capacitor (f

ESR

) and the dc gain of the modulator, equal

to the input voltage divided by the peak ramp height (V

RAMP

which is equal to V

REF

(1.2 V):

OUT

(18)

ESR

OUT

(19)

ADP3020

REV. 0

The compensation network consists of the internal error ampli-
fier and two external impedance networks Z

and Z

. Once the

application and the output filter capacitance and ESR are chosen,
the specific component values of the external impedance net-
works Z

and Z

can be determined. There are two design

criteria for achieving stable switching regulator behavior within
the line and load range. One is the maximum bandwidth of the
loop, which affects fast transient response, if needed, and the
other is the minimum accepted by the design phase margin.

The phase margin is the difference between the closed-loop phase
and 180 degrees. Recommended phase margin is 45 to 60 degrees
for most applications.

The equations for calculating the compensation Poles and Zeros
are:

×
+

(20)

(21)

(22)

(

)

(23)

The value of the internal resistor R1 is 71 k

for the 3.3 V

switching regulator, and 128 k

for the 5 V switching regulator.

Compensation Loop Design and Test Method

1. Choose the gain (R2/R1) for the desired bandwidth.

2. Place f

20%30% below f

3. Place f

20%30% above f

4. Place f

at f

ESR

, check the output capacitor for worst-case ESR

tolerances.

5. Place f

at 40%60% of oscillator frequency.

6. Estimate phase margins in full frequency range (zero frequency

to zero gain crossing frequency).

7. Apply the designed compensation and test the transient

response under a moderate step load change (30%60%) and
various input voltages. Monitor the output voltage via
oscilloscope. The voltage overshoot or undershoot should be
within 1%3% of the nominal output, without ringing and
abnormal oscillation.

Additional Application Circuits

The multiple outputs and wide input voltage range of the ADP3020
make it a very flexible IC for use in a wide variety of applications.
For example, the ADP3020 can be used to generate low voltage
(<4.0 V) outputs from a 5 V supply. The circuit shown in Fig-
ure 21 converts the 5 V input into a 3.3 V and a 2.5 V output.
The circuit of Figure 22 uses a secondary winding on the 5 V
output to generate an unregulated 15 V rail which is then regu-
lated to 12 V by the LDO output of the ADP3020.

ADP3020

REV. 0

C14A

10 F

C14B

10 F

D2
10BQ040

4.7 H

6.9k

CS5

FB5

EAN5

EAO5

ADJ/

FX5

SS5

CLSET5

BST5

DRVH5

SW5

DRVL5

PGND

AUXVCC

INTVCC

VIN

DRVL3

SW3

DRVH3

BST3

DRV2

FB2

SD2

CPOR

PWRGD

PFO

REF

AGND

CLSET3

MODE

SYNC

SS3

ADJ/

FX3

EAO3

EAN3

FB3

CS3

PFI

ADP3020

150pF

R16

10k

1 F

R11

6.2k

C19

330pF

D6
1N4148

C17
100nF

SI4410

C16
1 F

R6
10

D4
10BQ040
(OPTIONAL)

C27A
68 F

C27B
68 F

OUT25

2.5V, 3A

D3
10BQ040
(OPTIONAL)

C24A
68 F

C24B
68 F

OUT33

3.3V, 4A

SI4410

C15
4.7 F

C13
1 F

C20A

10 F

C20B

10 F

D1
10BQ040

4.7 H

C26
4.7 F

OUT15

1.5V, 1.5A

R9
4.7k

C28
1 F

R17

100

3.16k

R7
12k

C11
33 F

C12

100nF

R12

10k

PWRGD

R14

4.7

C22
4.7 F

4.5V-5.5V

47k

1nF

75k

470pF

68pF

1 F

R15

10.7k

1N4148

R10
2.2k

C18
2.2nF

R13

4.7

6.8nF

NDS8434

Figure 21. 5 V to 2.5 V/3.3 V DC-DC Converter

ADP3020

REV. 0

Layout Considerations

The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a portable PC system:

General Recommendations

For best results, a four-layer (minimum) PCB is recom-
mended. This should allow the needed versatility for control
circuitry interconnections with optimal placement, a signal
ground plane, power planes for both power ground and
the input power, and wide interconnection traces in the
rest of the power delivery current paths. Each square unit of 1
ounce copper trace has a resistance of ~ 0.53 m

at room

temperature.

Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.

The power and ground planes should overlap each other as
little as possible. It is generally easiest (although not neces-
sary) to have the power and signal ground planes on the same
PCB layer. The planes should be connected nearest to the
first input capacitor where the input ground current flows
from the converter back to the battery.

C14A

10 F

C14B

10 F

D2
10BQ040

L2*

130k

CS5

FB5

EAN5

EAO5

ADJ/

FX5

SS5

CLSET5

BST5

DRVH5

SW5

DRVL5

PGND

AUXVCC

INTVCC

VIN

DRVL3

SW3

DRVH3

BST3

DRV2

FB2

SD2

CPOR

PWRGD

PFO

REF

AGND

CLSET3

MODE

SYNC

SS3

ADJ/

FX3

EAO3

EAN3

FB3

CS3

PFI

ADP3020

68pF

R10

10k

C18

150pF

1 F

R11

6.2k

C19

330pF

D6
1N4148

C17
100nF

SI4410

C16
1 F

R6
10

C27A
68 F

C27B
68 F

OUT5

5V, 4A

C24A
68 F

C24B
68 F

OUT33

3.3V, 4A

SI4410

C15
4.7 F

C13
1 F

C14A

10 F

C14B

10 F

D1
10BQ040

6.8 H

C31
4.7 F

OUT12

12V, 100mA

R9
4.7k

C28
1 F

R17

9.09k

R7
1k

C32
4.7 F

R24

210k

R26
60.4k

C12

100nF

R12

10k

R13

10k

PWRGD

PFO

R14

4.7

C22
4.7 F

VIN

5.5V-25V

47k

1nF

75k

470pF

68pF

1 F

1N4148

*L2

4.7 H

N2/N1 =2:1

330pF

2N3906

D11
1N4148

Figure 22. Using a Secondary Winding and an LDO Post Regulator to Generate 12 V

ADP3020

REV. 0

If critical signal lines (including the voltage and current sense
lines of the ADP3020) must cross through power circuitry,
it is best if a signal ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the sig-
nals at the expense of making signal ground a bit noisier.

The PGND pin of the ADP3020 should connect first to a
ceramic bypass capacitor on the VIN pin, and then into the
power ground plane using the shortest possible trace. How-
ever, the power ground plane should not extend under other
signal components, including the ADP3020 itself. If neces-
sary, follow the preceding guideline to use the signal plane as
a shield between the power ground plane and the signal
circuitry.

The AGND pin of the ADP3020 should connect first to the
REF capacitor, and then into the signal ground plane. In cases
where no signal ground plane can be used, short interconnec-
tions to other signal ground circuitry in the power converter
should be used.

The output capacitors of the power converter should be
connected to the signal ground plane even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections
(e.g., the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).

The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the power.
If the load is distributed, the capacitors should also be dis-
tributed, and generally in proportion to where the load tends
to be more dynamic.

Absolutely avoid crossing any signal lines over the switching
power path loop, described below.

Power Circuitry

10. The switching power path should be routed on the PCB to

encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise-related operational prob-
lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs (and the power Schottky
diode if used), including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces
is especially critical in this path for two reasons: it mini-
mizes the inductance in the switching loop, which can cause
high-energy ringing, and it accommodates the high current
demand with minimal voltage loss.

11. A power Schottky diode (1 ~ 2 A dc rating) placed from the

lower FET's source (anode) to drain (cathode) will help to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET turning
on (necessary to prevent cross-conduction). The circulating
current in the power converter, no longer finding a path for
current through the channel of the lower FET, draws cur-
rent through the inherent body-drain diode of the FET.
The upper FET turns on, and the reverse recovery char-
acteristic of the lower FET's body-drain diode prevents the
drain voltage from being pulled high quickly.

The upper FET then conducts very large current while it
momentarily has a high voltage forced across it, which trans-
lates into added power dissipation in the upper FET. The
Schottky diode minimizes this problem by carrying a majority
of the circulating current when the lower FET is turned off,
and by virtue of its essentially nonexistent reverse recov-
ery time.

12. Whenever a power-dissipating component (e.g., a power

MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur-
rounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is
a current path), and improved thermal performance, espe-
cially if the vias are extended to the opposite side of the
PCB where a plane can more readily transfer the heat to
the air.

13. The output power path, though not as critical as the switch-

ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the output capacitors, and back to the
input capacitors.

14. For best EMI containment, the power ground plane should

extend fully under all the power components except the
output capacitors. These are: the input capacitors, the power
MOSFETs and Schottky diode, the inductor, and any snub-
bing elements that might be added to dampen ringing. Avoid
extending the power ground under any other circuitry or
signal lines, including the voltage and current sense lines.

Signal Circuitry

15. The CS and SW traces should be Kelvin-connected to the

upper MOSFET drain and source so that the additional
voltage drop due to current flow on the PCB at the current
sense comparator connections does not affect the sensed
voltage. It is desirable to have the ADP3020 close to the out-
put capacitor bank and not in the output power path, so that
any voltage drop between the output capacitors and the
AGND pin is minimized, and voltage regulation is not
compromised.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADP3020

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