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Hot Swap Controller and
Digital Power Monitor with AlertB Output
Preliminary Technical Data
ADM1178
Rev. PrD May 2006
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Allows Safe Board Insertion and Removal from a Live
Backplane
Controls Supply Voltages from 3.15 V to14 V
Precision Current Sense Amplifier
Precision Voltage Input
12-Bit ADC for Current and Voltage Readback
Charge Pumped Gate Drive for External N-FET Switch
Adjustable Analog Current Limit with Circuit Breaker
Fast Response Limits Peak Fault Current
Automatic Retry or Latch-Off On Current Fault
Programmable hot swap timing via TIMER pin
Active-high ON pin
AlertB pin for overcurrent interrupt
I
2
C Fast Mode compliant interface (400 KHz max)
10-lead MSOP package
APPLICATIONS
Power Monitoring/Power Budgeting
Central office Equipment
Telecommunication and Datacommunication Equipment
PC/Servers
GENERAL DESCRIPTION
The ADM1178 is an integrated hotswap controller and current
sense amplifier that offers digital current and voltage
monitoring via an on-chip 12-bit ADC, communicated through
an I
2
C interface.
An internal current sense amplifier senses voltage across the
sense resistor in the power path via the VCC and SENSE pins.
The ADM1178 limits the current through this resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage (and hence the
inrush current) is kept below a preset maximum.
The ADM1178 protects the external FET by limiting the time
that it spends with the maximum current running in it. This
current limit period is set by the choice of capacitor attached to
the TIMER pin. Additionally, the device provides protection
from overcurrent events at times after the hot-swap event is
complete. In the case of a short-circuit event the current in the
sense resistor will exceed an overcurrent trip threshold, and the
FET will be switched off immediately by pulling down the
GATE pin.
FUNCTIONAL BLOCK DIAGRAM
+
-
SCL
I2C
12-Bit
ADC
ADM1178
V
SENSE
VCC
SDA
GND
I
ADR
TIMER
FET Drive
Controller
GATE
ON
0
1
+
-
UV Comparator
Current Sense
Amplifier
Mux
1.3V
A
ALERTB
Alert
Figure 1.
APPLICATIONS DIAGRAM
R
SENSE
CONTROLLER
ADM1178
SENSE
Vcc
SDA
SCL
SDA
SCL
3.15V - 14V
P=VI
GND
GATE
N-Channel FET
ON
ADR
TIMER
ALERTB
INTERRUPT
Figure 2.
A 12-bit ADC can measure the current seen in the sense
resistor, and also the supply voltage on the VCC pin.
An industry standard I
2
C interface allows a controller to read
current and voltage data from the ADC. Measurements can be
initiated by an I
2
C command. Alternatively the ADC can run
continuously and the user can read the latest conversion data
whenever it is required. Up to 4 unique I
2
C addresses can be
created by the way the ADR pin is connected.
The ADM1178 is packaged in a 10-lead MSOP package.
ADM1178
Preliminary Technical Data
Rev. PrD | Page 2 of 16
TABLE OF CONTENTS
REVISION HISTORY
May 06--Revision PrD: Preliminary Version
Preliminary Technical Data
ADM1178
Rev. PrD | Page 3 of 16
ADM1178--SPECIFICATIONS
V
VCC
= 3.15V to 14V, T
A
= -40C to +85C, Typical Values at T
A
= +25C unless otherwise noted.
Table 1.
Parameter Min
Typ
Max
Units
Conditions
VCC Pin
Operating Voltage Range, V
VCC
3.15
14
V
Supply Current, I
CC
1.6
3
mA
Undervoltage Lockout, V
UVLO
2.8
V
V
VCC
Rising
Undervoltage Lockout Hysteresis, V
UVLOHYST
25
mV
ON Pin
Input Current, I
INON
-100
0
+100
nA
Trip Threshold, V
ONTH
1.3
V
ON rising
Trip Threshold Hysteresis, V
ONHYST
80
mV
Glitch Filter Time
3
s
ALERTB Pin
Output low voltage, V
ALERTOL
0.05
0.2
V
I
ALERT
= -100A
Maximum sink current, I
ALERTMAX
-2
mA
Maximum sink current allowed to flow in
ALERT pin 0 output state
Input Current, I
ALERT
-1
1
A
V
ALERT
= V
CC
; in Alert Condition
SENSE Pin
Input Leakage, I
SENSE
-1
+1
A
V
SENSE
= V
VCC
Overcurrent Fault Timing Threshold, V
OCTIM
85
mV
V
OCTRIM
= (V
VCC
- V
SENSE
), Fault timing starts
on the TIMER pin
Overcurrent Limit Threshold, V
LIM
90
100
110
mV
V
LIM
= (V
VCC
- V
SENSE
), Closed loop regulation
to a current limit
Fast Overcurrent Trip Threshold, V
OCFAST
115
mV
V
OCFAST
= (V
VCC
- V
SENSE
), Gate pulldown
current turned on
GATE Pin
Drive Voltage, V
GATE
5
7
10
V
V
GATE
- V
VCC
, V
VCC
= 3.15 V
Drive Voltage, V
GATE
6
8
12
V
V
GATE
- V
VCC
, V
VCC
= 5 V
Drive Voltage, V
GATE
5
7
10
V
V
GATE
- V
VCC
, V
VCC
= 13.2 V
Pullup Current
10
12
14
A
V
GATE
= 0 V
Pulldown Current
2
mA
V
GATE
= 3 V, V
VCC
> UVLO
Pulldown Current
25
mA
V
GATE
= 3 V, V
VCC
< UVLO
TIMER Pin
Pull-Up Current (Power On Reset), I
TIMERUPPOR
-4
-5
-6
A
Initial Cycle, V
TIMER
= 1 V
Pull-Up Current (Fault Mode), I
TIMERUPFAULT
-48
-60
-72
A
During Current Fault, V
TIMER
= 1 V
Pull-Down Current (Retry Mode), I
TIMERDNRETRY
2
2.5
A
After current fault and during a cool-down
period on a retry device, V
TIMER
= 1 V
Pull-Down Current, I
TIMERDN
100
A
Normal Operation, V
TIMER
= 1 V
Trip Threshold High, V
TIMERH
1.235
1.3
1.365
V
TIMER rising
Trip Threshold Low, V
TIMERL
0.18
0.2
0.22
V
TIMER falling
ADR Pin
Set address to 00, V
ADRLOWV
0
0.8
V
Low state
Set address to 01, R
ADRLOWZ
135
150
165
k
Resistor to ground state, load pin with
specified resistance for 01 decode
Set address to 10, I
ADRHIGHZ
-1
+1
A
Open state, maximum load allowed on
ADR pin for 10 decode
Set address to 11, V
ADRHIGHV
2
5.5
V
High state
Input current for 11 decode, I
ADRLOW
3
5
A
V
ADR
= 2.0 V to 5.5 V
Input current for 00 decode, I
ADRHIGH
-40
-22
A
V
ADR
= 0 V to 0.8 V
ADM1178
Preliminary Technical Data
Rev. PrD | Page 4 of 16
Parameter Min
Typ
Max
Units
Conditions
MONITORING ACCURACY
1
Current Sense Absolute Accuracy
TBD
TBD %
V
SENSE
= 75 mV
-2.3
+2.2
%
V
SENSE
= 75 mV, @ 0C to +70C
TBD
TBD %
V
SENSE
= 50mV
-2.5
+2.5
%
V
SENSE
= 50 mV, @ 0C to +70C
TBD
TBD %
V
SENSE
= 25mV
-2.8
+2.8
%
V
SENSE
= 25mV, @ 0C to +70C
-3.5
+3.5
%
V
SENSE
= 12.5 mV, @ 25C
Current Sense Accuracy, T
C
0.01
%/C
V
SENSE
for ADC full-scale
105
mV
Voltage Sense Accuracy
-1.5
0
+1.5
%
V
VCC
= 3.0 V to 5.5V(VRANGE = 1)
-1.5
0
+1.5
%
V
VCC
= 10.8 V to 13.2V(VRANGE = 0)
V
CC
for ADC full-scale, low range
6.656
V
VRANGE = 1
V
CC
for ADC full-scale, high range
26.628
2
V
VRANGE = 0
I
2
C Timing
3
Low level input voltage, V
IL
0.99
V
High level input voltage, V
IH
2.31 V
Low level output voltage on SDA, V
OL
0.4
V
I
OL
= 3mA
Output fall time on SDA from V
IHMIN
to V
ILMAX
20+0.1C
B
250
ns
C
B
= bus capacitance from SDA to GND
Maximum width of spikes suppressed by input
filtering on SDA and SCL pins
50 250
ns
Input current, I
I
, on SDA/SCL when not driving out
a logic low
-10 +10
A
Input capacitance on SDA/SCL
5
pF
SCL clock frequency, f
SCL
400
kHz
LOW period of the SCL clock
600 ns
HIGH period of the SCL clock
1300
ns
Setup time for a repeated START condition, t
SU;STA
600 ns
SDA output data hold time, t
HD;DAT
100 ns
Set-up time for a stop condition, t
SU;STO
600 ns
Bus free time between a STOP and a START
condition, t
BUF
1300
ns
Capacitive load for each bus line
400
pF
1
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error and
ADC error.
2
The maximum operating voltage is limited to V
VCC
=14 V which corresponds to an ADC code of 871.
3
The following conditions apply to all timing specifications: V
BUS
=3.3V, T
A
=25C. All timings refer to V
IHMIN
and V
ILMAX
.
Preliminary Technical Data
ADM1178
Rev. PrD | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
V
CC
Pin
20 V
SENSE Pin
20 V
TIMER Pin
-0.3 V to +6 V
ON Pin
-0.3 V to +20 V
ALERTB Pin
TBD
GATE Pin
30 V
SDA, SCL Pins
-0.3 V to +6 V
ADR Pin
-0.3 V to +6 V
Power Dissipation
TBD
Storage Temperature
-65C to +125C
Operating Temperature Range
-40C to +85C
Lead Temperature Range
(Soldering 10 sec)
300C
Junction Temperature
150C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
Ambient temperature = 25C, unless otherwise noted.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADM1178
Preliminary Technical Data
Rev. PrD | Page 6 of 16
PIN CONFIGURATIONS
1
2
3
4
ADM1178
TOP VIEW
(NOT TO SCALE)
Vcc
ADR
SDA
GATE
ON
TIMER
SENSE
ALERTB
GND
5
SCL
10
9
8
7
6
Figure 3. Pin Configurations
PIN FUNCTIONAL DESCRIPTIONS
Table 3.
Pin No.
Name
Description
1 VCC
Positive supply input pin. The operating supply voltage range is between 3.15 V to 14 V. An undervoltage
lockout (UVLO) circuit resets the ADM1178 when a low supply voltage is detected.
2 SENSE
Current sense input pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. The
hotswap operation of the ADM1178 controls the external FET gate to maintain the (V
VCC
-V
SENSE
) voltage at 100
mV or below.
3 ON
Undervoltage input pin. Aactive high pin. An internal ON comparator has a trip threshold of 1.3 V and the
output of this comparator is used as an enable for the hotswap operation. With an external resistor divider
from VCC to GND, this pin can be used to enable the hotswap operation one a specific voltage on VCC, giving
an undervoltage function.
4
GND
Chip Ground Pin
5 TIMER
Timer pin. An external capacitor C
TIMER
sets a 270 ms/F initial timing cycle delay and a 21.7 ms/F fault delay.
The GATE pin turns off whenever the TIMER pin is pulled beyond the upper threshold. An overvoltage
detection with an external zener can be used to force this pin high.
6 SCL
I
2
C Clock Pin. Open-drain output requires an external resistive pull-up.
7 SDA
I
2
C Data I/O Pin. Open-drain output requires an external resistive pull-up.
8 ADR
I
2
C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor to set four
different I
2
C addresses.
9 GATE
GATE Output Pin. This pin is the high side gate drive of an external N-channel FET. This pin is driven by the FET
drive controller which utilises a charge pump to provide a 12 A pull-up current to charge the FET gate pin.
The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by
modulating the GATE pin.
10 ALERTB
Alert Output Pin. Active low, open drain configuration. This pin asserts when an overcurrent condition is
present.
Preliminary Technical Data
ADM1178
Rev. PrD | Page 7 of 16
OVERVIEW OF THE HOTSWAP FUNCTION
When circuit boards are inserted into a live backplane,
discharged supply bypass capacitors would draw large transient
currents from the backplane power bus as they charge. Such
transient currents can cause permanent damage to connector
pins, and dips on the backplane supply which could reset other
boards in the system. The ADM1178 is designed to turn a
circuit board's supply voltage on and off in a controlled manner,
allowing the circuit board to be safely inserted into or removed
from a live backplane. The ADM1178 can reside either on the
backplane or on the circuit board itself.
The ADM1178 controls the "inrush" current to a fixed
maximum level by modulating the gate of an external N-
channel FET placed between the live supply rail and the load.
This "hotswap" function protects the card connectors and the
FET itself from damage and also limits any problems which
could be caused by the high current loads on the live supply rail.
The ADM1178 holds the GATE pin down (and thus the FET is
held off) until a number of conditions are met. An undervoltage
lockout circuit ensures that the device is being provided with an
adequate input supply voltage. Once this has been successfully
detected, the device goes through an initial timing cycle to
provide a delay before it will attempt to hotswap. This delay
ensures that the board is fully seated in the backplane before the
board is powered up.
Once the initial timing cycle is complete, the hotswap function
is switched on under control of the ON pin. When asserted high
the hotswap operation starts.
The ADM1178 charges up the gate of the FET to turn on the
load. It will continue to charge up the GATE pin until the linear
current limit (set to 100 mV/R
SENSE
) is reached. For some
combinations of low load capacitance and high current limit,
this limit may not be reached before the load is fully charged up.
If current limit is reached, the ADM1178 will regulate the
GATE pin to keep the current at this limit. For currents above
the overcurrent fault timing threshold, nominally 100 mV/
R
SENSE
, the current fault is timed by sourcing a current out to the
TIMER pin. If the load becomes fully charged before the fault
current limit time is reached (when the TIMER pin reaches
1.3 V), the current will drop below the overcurrent fault timing
threshold, the ADM1178 will then charge the GATE pin higher
to fully enhance the FET for lowest R
ON
, and the TIMER pin
will be pulled down again.
If the fault current limit time is reached before the load drops
below the current limit, a fault has been detected, and the
hotswap operation is aborted by pulling down on the GATE pin
to turn off the FET. The ADM1178-2 is latched off at that point
and will only attempt to hotswap again when the ON pin is de-
asserted then asserted again. The ADM1178-1 will retry the
hotswap operation indefinitely, keeping the FET in SOA by
using the TIMER pin to time a cool-down period in between
hotswap attempts. The current and voltage threshold
combinations on the TIMER pin set the retry duty cycle to
3.8%.
The ADM1178 is designed to operate over a range of supplies
from 3.15 V to 14 V.
UNDERVOLTAGE LOCKOUT
An internal undervoltage lockout (UVLO) circuit resets the
ADM1178 if the VCC
supply is too low for normal operation.
The UVLO has a low-to-high threshold of 2.8 V, with 25 mV
hysteresis. Above 2.8 V supply voltage, the ADM1178 will start
the initial timing cycle.
ON FUNCTION
The ADM1178 has an active-high ON pin. The ON pin is the
input to a comparator which has a low-to-high threshold of 1.3
V, an 80 mV hysteresis and a glitch filter of 3 s. A low input on
the ON pin turns off the hotswap operation by pulling the
GATE pin to ground, turning off the external FET. The TIMER
pin is also reset by turning on a pull-down current on this pin.
A low-to-high transition on the ON pin starts the hotswap
operation. A 10 k pull-up resistor connecting the ON pin to
the supply is recommended.
Alternatively, an external resistor divider at the ON pin can be
used to program an undervoltage lockout value higher than the
internal UVLO circuit, thereby setting a voltage level at the
VCC supply where the hotswap operation is to start. An RC
filter can be added at the ON pin to increase the delay time at
card insertion if the initial timing cycle delay is insufficient.
TIMER FUNCTION
The TIMER pin handles several timing functions with an
external capacitor, C
TIMER
. There are two comparator thresholds:
V
TIMERH
(0.2 V) and V
TIMERL
(1.3 V). The four timing current
sources are a 5 A and a 60 A pull-up, and a 2 A and a
100 A pull-down. The 100 A is a non-ideal current source
approximating a 7 k resistor below 0.4 V.
These current and voltage levels, together with the value of
C
TIMER
that the user chooses, determine the initial timing cycle
time, the fault current limit time, and the hotswap retry duty
cycle.
ADM1178
Preliminary Technical Data
Rev. PrD | Page 8 of 16
GATE AND TIMER FUNCTIONS DURING A
HOTSWAP
During hot insertion of a board onto a live supply rail at VCC,
the abrupt application of supply voltage charges the external
FET drain/gate capacitance, which could cause an unwanted
gate voltage spike. An internal circuit holds GATE low before
the internal circuitry wakes up. This reduces the FET current
surges substantially at insertion. The GATE pin is also held low
during the initial timing cycle, and until the ON pin has been
taken high to start the hotswap operation.
During hotswap operation the GATE pin is first pulled up by a
12 A current source. If the current through the sense resistor
reaches the overcurrent fault timing threshold, Voctim, then a
pull-up current of 60 A on the TIMER pin is turned on, and
this pin starts charging up. At a slightly higher voltage in the
sense resistor, the error amplifier servos the GATE pin to
maintain a constant current to the load by controlling the
voltage across the sense resistor to the linear current limit, V
LIM
.
A normal hotswap will complete when the board supply
capacitors near full charge and the current through the sense
resistor drops, to eventually reach the level of the board load
current. As soon as the current drops below the overcurrent
fault timing threshold, the current into the TIMER pin will
switch from being a 60 A pull-up to a 100 A pull-down. The
ADM1178 will then drive the GATE voltage as high as it can to
fully enhance the FET and reduce R
ON
losses to a minimum.
A hotswap will fail if the load current fails to drop below the
overcurrent fault timing threshold, V
OCTIM
, before the TIMER
pin has charged up to 1.3 V. In this case the GATE pin is then
pulled down with a 2 mA current sink. The GATE pull-down
will stay on until a hotswap retry starts, which can be forced by
de-asserting then re-asserting the ON pin, or the device will
retry automatically after a cool-down period, on the ADM1178-
1.
The ADM1178 also features a method of protection from
sudden load current surges, such as a low impedance fault,
when the current seen across the sense resistor may go well
beyond the linear current limit. If the fast overcurrent trip
threshold, V
OCFAST
, is exceeded, the 2 mA GATE pull-down is
turned on immediately. This pulls the GATE voltage down
quickly to enable the ADM1178 to limit the length of the
current spike that gets through, and also to bring the current
through the sense resistor back into linear regulation as quickly
as possible. This protects the backplane supply from sustained
overcurrent conditions, which may otherwise have caused
problems with the backplane supply level dropping too low.
CALCULATING CURRENT LIMITS AND FAULT
CURRENT LIMIT TIME
The nominal linear current limit is determined by a sense
resistor connected between the VCC and SENSE pins as given
by the equation below:
I
LIMIT(NOM)
= V
LIM(NOM)
/R
SENSE
= 100 mV/R
SENSE
(1)
The minimum linear fault current is given by Equation 2:
I
LIMIT(MIN)
= V
LIM(MIN)
/R
SENSE(MAX)
= 90 mV/R
SENSE(MAX)
(2)
The maximum linear fault current is given by Equation 3:
I
LIMIT(MAX)
= V
LIM(MAX)
/R
SENSE(MIN)
= 110 mV/R
SENSE(MIN)
(3)
The power rating of the sense resistor should be rated at the
maximum linear fault current level.
The minimum overcurrent fault timing threshold current is
given by
I
OCTIM(MIN)
= V
OCTIM(MIN)
/R
SENSE(MAX)
= 85 mV/R
SENSE(MAX)
(4)
The maximum fast overcurrent trip threshold current is given
by
I
OCFAST(MAX)
= V
OCFAST(MAX)
/R
SENSE(MIN)
= 115 mV/R
SENSE(MIN)
(5)
The fault current limit time is the time that a device will spend
timing an overcurrent fault, and is given by
t
FAULT
~= 21.7 C
TIMER
ms/F (6)
INITIAL TIMING CYCLE
When VCC is first connected to the backplane supply, there is
an internal supply (time-point (1) in Figure 4) in the ADM1178
which needs to charge up. A very short time later (significantly
less than 1 ms) the internal supply will be fully up and, since the
undervoltage lockout voltage has been exceeded at VCC, the
device will come out of reset. During this first short reset period
the GATE pin is held down with a 25 mA pulldown current,
and the TIMER pin is pulled down with a 100 A current sink.
The ADM1178 then goes through an initial timing cycle. At
point (2) the TIMER pin is pulled high with 5 A. At time point
(3), the TIMER reaches the V
TIMERL
threshold and the first
portion of the initial cycle ends. The 100 A current source
then pulls down the TIMER pin until it reaches 0.2 V at time
point (4). The initial cycle delay (time point 2 to time point 4) is
related to C
TIMER
by equation:
t
INITIAL
~= 270 C
TIMER
ms/F
(7)
When the initial timing cycle terminates, the device is ready to
start a hotswap operation (assuming ON pin is asserted). In the
example shown in Figure 4, the ON pin was asserted at the
same time as VCC was applied, so the hotswap operation starts
immediately after time-point (4). At this point the FET gate is
Preliminary Technical Data
ADM1178
Rev. PrD | Page 9 of 16
charged up with a 12 A current source. At timepoint (5) the
threshold voltage of the FET is reached and the load current
begins to flow. The FET is controlled to keep the sense voltage
at 100 mV (this corresponds to a maximum load current level
defined by the value of R
SENSE
). At timepoint (6) V
GATE
and V
OUT
have reached their full potential and the load current has settled
to its nominal level. Figure 5 illustrates the situation where the
ON pin is asserted after V
VCC
is applied.
VVCC
VON
VGATE
VOUT
VTIMER
INITIAL TIMING
CYCLE
(1)
(2)
(3) (4) (5)
(6)
VSENSE
Figure 4. Start-up (ON asserts as power is applied)
VVCC
VON
VGATE
VOUT
VTIMER
INITIAL TIMING
CYCLE
(1)
(2)
(3)(4)
(5)(6)
VSENSE
(7)
Figure 5. Start-up (ON asserts after power is applied)
HOTSWAP RETRY CYCLE ON ADM1178-1
With the ADM1178-1 the device will turn off the FET after an
overcurrent fault, and will then use the TIMER pin to time a
delay before automatically retrying to hotswap.
As with all ADM1178 devices, on overcurrent fault is timed by
charging the TIMER cap with a 60 A pull-up current, and
when the TIMER pin reaches 1.3 V the fault current limit time
has been reached and the GATE pin is pulled down. On the
ADM1178-1, the TIMER pin is then pulled down with a 2 A
current sink. When the TIMER pin reaches 0.2 V, it will
automatically restart the hotswap operation.
The cool down period is related to C
TIMER
by equation:
t
COOL
~ = 550 C
TIMER
ms/F (8)
The retry duty cycle is thus given by
t
FAULT
/(t
COOL +
t
FAULT
) 100% = 3.8%
(9)
ADM1178
Preliminary Technical Data
Rev. PrD | Page 10 of 16
VOLTAGE AND CURRENT READBACK
In addition to providing hot swap functionality, the ADM1178
also contains the components to allow voltage and current
readback over an I
2
C bus. The voltage output of the current
sense amplifier and the voltage on the VCC pin are fed into a
12-bit ADC via a multiplexer. The device can be instructed to
convert voltage and/or current at any time during operation via
an I
2
C command. When all conversions are complete the
voltage and/or current values can be read out to 12-bit accuracy
in two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1178 is carried out via the Inter-IC Bus
(I
2
C). This interface is compatible with fastmode I
2
C (400 kHz
max). The ADM1178 is connected to this bus as a slave device,
under the control of a master device.
IDENTIFYING THE ADM1178 ON THE I
2
C BUS
The ADM1178 has a 7-bit serial bus slave address. When the
device is powered up, it will do so with a default serial bus
address. The three MSBs of the address are set to 111 and the
two MSBs are set to 10, to give an address 111xx10. Bits A2 and
A3 are determined by the state of the ADR pin. There are four
different configurations available on the ADR pin which
correspond to four different I
2
C addresses for these bits. These
are explained in Table 4 below. This scheme allows four
ADM1178 devices to operation on a single I
2
C bus.
Table 4. Setting I
2
C Addresses via the ADR Pin
ADR Configuration
Address
Low state
0xE4
Resistor to GND
0xEC
Floating (unconnected)
0xF4
High state
0xFC
GENERAL I
2
C TIMING
Figure 6 and Figure 7 show timing diagrams for general read
and write operations using the I
2
C. The I
2
C specification defines
specific conditions for different types of read and write
operation, which are discussed later. The general I
2
C protocol
operates as follows:
1.
The master initiates data transfer by establishing a START
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains
high. This indicates that a data stream will follow. All slave
peripherals connected to the serial bus respond to the
START condition, and shift in the next 8 bits, consisting
of a 7-bit slave address (MSB first) plus a R/W bit, which
determines the direction of the data transfer, i.e. whether
data will be written to or read from the slave device (0 =
write, 1 = read).
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit, and holding it low during the high
period of this clock pulse. All other devices on the bus
now remain idle while the selected device waits for data to
be read from or written to it. If the R/W bit is a 0, the
master will write to the slave device. If the R/W bit is a 1,
the master will read from the slave device.
2.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, as a low to high
transition when the clock is high may be interpreted as a
STOP signal.
If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the
slave device what to expect next. It may be an instruction
such as telling the slave device to expect a block write, or
it may simply be a register address that tells the slave
where subsequent data is to be written.
Since data can flow in only one direction as defined by the
R/W bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read
operation, it may first be necessary to do a write operation
to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
3.
When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10
th
clock pulse to
assert a STOP condition. In READ mode, the master
device will release the SDA line during the low period
before the ninth clock pulse, but the slave device will not
pull it low. This is known as No Acknowledge. The master
will then take the data line low during the low period
before the 10
th
clock pulse, then high during the 10
th
clock
pulse to assert a STOP condition.
Preliminary Technical Data
ADM1178
Rev. PrD | Page 11 of 16
SCL
SDA
START BY MASTER
1
9
1
9
A1
A0
R/W
1
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
ACK. BY
SLAVE
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
SLAVE
1
9
1
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
FRAME N
DATA BYTE
FRAME 3
DATA BYTE
SDA
(CONTINUED)
Figure 6. General I
2
C Write Timing Diagram
SCL
SDA
START BY MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
A1
A0
R/W
1
1
1
0
0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
DATA BYTE
1
9
1
9
ACK. BY
SLAVE
1
9
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK.
ACK. BY
MASTER
1
9
STOP
BY
MASTER
FRAME 3
DATA BYTE
FRAME N
DATA BYTE
Figure 7. General I
2
C Read Timing Diagram
SCL
SCL
SDA
P
S
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;DAT
t
SU;STA
t
HD;STA
t
F
t
R
t
LOW
t
BUF
t
SU;STO
P
S
Figure 8. Serial Bus Timing Diagram
ADM1178
Preliminary Technical Data
Rev. PrD | Page 12 of 16
WRITE AND READ OPERATIONS
The I
2
C specification defines several protocols for different
types of read and write operations. The ones used in the
ADM1178 are discussed below. The following abbreviations are
used in the diagrams:
Table 5. I
2
C abbreviations
S START
P STOP
R READ
W WRITE
A ACKNOWLEDGE
N
NO ACKNOWLEDGE
QUICK COMMAND
This operation allows the master check if the slave is present on
the bus. This entails the following:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
S
SLAVE
ADDRESS
W A
1
2
3
Figure 9. Quick Command
WRITE COMMAND BYTE
In this operation the master device sends a command byte to
the slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends the command byte. The command
byte is identified by an MSB =0. (An MSB =1 indicates
an Extended Register Write. See next section.)
5.
The slave asserts ACK on SDA.
6.
The master asserts a STOP condition on SDA to end
the transaction.
S
SLAVE
ADDRESS
W A
A
COMMAND
BYTE
P
1
2
3
4
5 6
Figure 10. Command Byte Write
The seven LSBs of the command byte are used to configure and
control the ADM1178. Details of the function of each bit are
provided in Table 6.
Table 6. Command Byte Operations
Bit Default Name
Function
C0 0
V_CONT
Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the
ADM1178 will ACK and return all zeros in the returned data.
C1
0
V_ONCE
Set to convert voltage once. Self-clears. I
2
C will NACK an attempted read until ADC conversion is complete.
C2 0
I_CONT
Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the
ADM1178 will ACK and return all zeros in the returned data.
C3
0
I_ONCE
Set to convert current once. Self-clears. I
2
C will NACK an attempted read until ADC conversion is complete.
C4 0
VRANGE
Selects different internal attenuation resistor networks for voltage readback. A "0" in C4 selects a 14:1 voltage
divider. A "1" in C4 selects a 7:2 voltage divider. With an ADC full-scale of 1.902 V, the voltage at the VCC pin
for an ADC full-scale result is 26.63 V for VRANGE = 0 and 6.66 V for VRANGE = 1.
C5 0
N/A
Unused
C6 0
STATUS_RD Status Read. When this bit is set the data byte read back from the ADM1178 will be the STATUS byte. This
contains the status of the device alerts. See Table14 for full details of the status byte.
Preliminary Technical Data
ADM1178
Rev. PrD | Page 13 of 16
WRITE EXTENDED BYTE
In this operation the master device writes to one of the three
extended registers of the slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends the register address byte. The MSB
of this byte is set to 1 to indicate an extended register
write. The two LSBs indicate which of the three
extended registers will be written to (see Table 7). All
other bits should be set to 0.
5.
The slave asserts ACK on SDA.
6.
The master sends the command byte. The command
byte is identified by an MSB = 0. (An MSB = 1
indicates an Extended Register Write. See next
section.)
7.
The slave asserts ACK on SDA.
8.
The master asserts a STOP condition on SDA to end
the transaction.
S
SLAVE
ADDRESS
R A
A
REGISTER
ADDRESS
P
REGISTER
DATA
N
1
2
3
4
5
6
7 8
Figure 11. Command Byte Write
Table 8, Table 9, and give details of each extended register.
Table 7. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0 Extended
Register
0 0 0 0 0 0 1 ALERT_EN
0 0 0 0 0 1 0 ALERT_TH
0 0 0 0 0 1 1 CONTROL
Table 8. ALERT_EN Register Operations
Bit Default Name
Function
0 0
EN_ADC_OC1 Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH
register
1 0
EN_ADC_OC4 Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the
ALERT_TH register
2 1
EN_HS_ALERT Enabled if the hotswap has either latched off, or entered a cool down cycle, because of an overcurrent
event
3 0
EN_OFF_ALERT
Enable an ALERT if the HS operation is turned off by a transition which de-asserts the ON pin, or by an
operation which writes the SWOFF bit high.
4 0
CLEAR
Clears the ON_ALERT, HS_ALERT and ADC_ALERT status bits in the STATUS register. These may
immediately reset if the source of the alert has not been cleared, or disabled with the other bits in this
register. This bit self-clears to 0 after the STATUS register bits have been cleared.
Table 9. ALERT_TH Register Operations
Bit Default Function
7:0 FF
The ALERT_TH register sets the current level at which an alert will occur. Defaults to ADC full-scale. ALERT_TH 8-bit number
corresponds to the top 8-bits of the current channel data.
Table 10. CONTROL Register Operations
Bit Default
Name
Function
0
0
SWOFF
Force hotswap off. Equivalent to de-asserting the ON pin.
ADM1178
Preliminary Technical Data
Rev. PrD | Page 14 of 16
READ VOLTAGE AND/OR CURRENT DATA BYTES
The ADM1178 can be set up to provide information in three
different ways (see Write Command Byte section above).
Depending on how the device is configured the following data
can be read out of the device after a conversion (or
conversions):
1. Voltage and Current Readback.
The ADM1178 will digitize both voltage and current. Three
bytes will be read out of the device in the following format:
Table 11.
Byte Contents B7 B6 B5 B4
B3 B2 B1 B0
1
Voltage
MSBs
V11 V10 V9 V8 V7 V6 V5 V4
2
Current
MSBs
I11 I10 I9 I8 I7 I6 I5 I4
3
Voltage
LSBs
V3 V2 V1 V0 I3 I2 I1 I0
2. Voltage Readback
.
The ADM1178 will digitize voltage only. Two bytes will be read
out of the device in the following format:
Table 12.
Byte
Contents
B7 B6 B5 B4
B3 B2 B1 B0
1
Voltage MSBs
V11 V10 V9 V8 V7 V6 V5 V4
2
Voltage LSBs
V3
V2
V1 V0 0
0
0
0
3. Current Readback
.
The ADM1178 will digitize current only. Two bytes will be read
out of the device in the following format:
Table 13.
Byte
Contents
B7 B6 B5 B4
B3 B2 B1 B0
1
Current MSBs
I11 I10 I9 I8 I7 I6 I5 I4
2
Current LSBs
I3
I2
I1
I0
0
0
0
0
The following series of events occur when the master receives
three bytes (voltage and current data) from the slave device:
1.
The master device asserts a START condition on SDA.
2.
The master sends the 7-bit slave address followed by
the read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives the first data byte.
5.
The master asserts ACK on SDA.
6.
The master receives the second data byte.
7.
The master asserts ACK on SDA.
8.
The master receives the third data byte.
9.
The master asserts NO ACK on SDA.
10.
The master asserts a STOP condition on SDA and the
transaction ends.
For the cases where the master is reading voltage only or
current only, only two data bytes will be read and events 7 and 8
above will not be required.
S
SLAVE
ADDRESS
R A
A
DATA 1
A
P
DATA 2
N
1
2
3
4
5
6
7
8
9 10
DATA 3
Figure 12. Three Byte Read fromADM1178
S
SLAVE
ADDRESS
R A
A
REGISTER
ADDRESS
P
REGISTER
DATA
N
1
2
3
4
5
6
7 8
Figure 13. Two Byte Read fromADM1178
Read Status Register
A single register of status data can also be read from the
ADM1178.
1.
The master device asserts a START condition on SDA.
2.
The master sends the 7-bit slave address followed by
the read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives the status byte.
5.
The master asserts ACK on SDA.
S
SLAVE
ADDRESS
R A
A
DATA 1
1
2
3
4
5
Figure 14. Status Read fromADM1178
Table 14 shows the ADM1178 status registers in detail. Note
that bits 1, 3 and 5 are cleared by writing to bit 4 of the
ALERT_EN register (CLEAR).
Preliminary Technical Data
ADM1178
Rev. PrD | Page 15 of 16
Table 14. Status Byte Operations
Bit Name
Function
0
ADC_OC
An ADC based overcurrent comparison has been detected on the last 3 conversions
1 ADC_ALERT
An ADC based overcurrent trip has happened, which has caused the ALERT. Cleared by writing to bit 4 of the
ALERT_EN register.
2 HS_OC
The hotswap is off due to an analog overcurrent event. On parts which latch off, this will be the same as the HS_ALERT
status bit (if EN_HS_ALERT=1). On the retry parts this will indicate the current state--a 0 could indicate that the data
was read during a period when the device is retrying, or that it has successfully hotswapped by retrying after at least
one overcurrent timeout.
3
HS_ALERT
The hotswapper has failed since the last time this was reset. Cleared by writing to bit 4 of the ALERT_EN register.
4 OFF_STATUS
The state of the ON pin. Set to 1 if the input pin is de-asserted. Can also be set to 1 by writing to the SWOFF bit of the
CONTROL register.
5
OFF_ALERT
An alert has been caused either by the ON pin or the SWOFF bit. Cleared by writing to bit 4 of the ALERT_EN register.
KELVIN SENSE RESISTOR CONNECTION
When using a low-value sense resistor for high current
measurement the problem of parasitic series resistance can
arise. The lead resistance can be a substantial fraction of the
rated resistance making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 15 below shows the correct way to connect the sense
resistor between the VCC and SENSE pins of the ADM1178.
SENSE RESISTOR
KELVIN SENSE TRACES
CURRENT
FLOW TO
LOAD
CURRENT
FLOW FROM
SUPPLY
V
CC
SENSE
ADM1178
Figure 15. Kelvin Sense Connections
ADM1178
Preliminary Technical Data
Rev. PrD | Page 16 of 16
OUTLINE DIMENSIONS
0.0197 (0.50)
BSC
0.122 (3.10)
0.114 (2.90)
10
6
5
1
0.199 (5.05)
0.187 (4.75)
PIN
1
0.122 (3.10)
0.114 (2.90)
0.012 (0.30)
0.006 (0.15)
0.037 (0.94)
0.031 (0.78)
SEATING
PLANE
0.120 (3.05)
0.112 (2.85)
0.043 (1.10)
MAX
0.006 (0.15)
0.002 (0.05)
0.028 (0.70)
0.016 (0.40)
0.009 (0.23)
0.005 (0.13)
6
0
o
0.120 (3.05)
0.112 (2.85)
o
Figure 16. 10-Lead MSOP Package
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model Hotswap
Retry
Option
Brand
Temperature Range
Package Description
Package Outline
ADM1178-1ARMZ-R7
Automatic Retry Version
M62
-40C to +85C
MSOP-10
RM-10
ADM1178-2ARMZ-R7
Latched Off Version
M64
-40C to +85C
MSOP-10
RM-10
1
Z = Pb-free part.
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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