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Электронный компонент: ADG527A

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ADG526A_527A Data Sheet
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REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADG526A/ADG527A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
CMOS Latched
8-/16-Channel Analog Multiplexers
FEATURES
44 V Supply Maximum Rating
V
SS
to V
DD
Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns
WR Pulse)
Extended Plastic Temperature Range (40 C to +85 C)
Low Leakage (20 pA Typ)
Low Power Dissipation (28 mW Max)
Available in DIP, SOIC, PLCC, and LCCC Packages
Superior Alternative to: DG526, DG527
GENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADG526A switches one of 16 inputs to a common output
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs
to a common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic compatible digital inputs.
The ADG526A and ADG527A are designed on an enhanced
LC
2
MOS process which gives an increased signal capability of
V
SS
to V
DD
and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single or dual supply range. These multiplex-
ers also feature high switching speeds and low R
ON
.
PRODUCT HIGHLIGHTS
1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.
2. Easily Interfaced: The ADG526A and ADG527A can be
easily interfaced with microprocessors. The
WR signal latches
the state of the Address control lines and the Enable line.
The
RS signal clears both the address and enable data in the
latches resulting in no output (all switches off).
RS can be
tied to the microprocessor reset pin.
3. Extended Signal Range: The enhanced LC
2
MOS processing
results in a high breakdown and an increased analog signal
range of V
SS
to V
DD
.
4. Break-Before-Make Switching: Switches are guaranteed
break-before-make so that input signals are protected against
momentary shorting.
5. Low Leakage: Leakage currents in the range of 20 pA make
these multiplexers suitable for high precision circuits.
FUNCTIONAL BLOCK DIAGRAM
A0
ADG526A
DECODER/
LATCHES
S1
S16
D
ADG527A
S1A
S8B
DA
DB
S8A
S1B
WR
A1 A2 A3 EN
RS
WR
DECODER/
LATCHES
A0 A1 A2 EN
RS
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REV. B
2
ADG526A/ADG527ASPECIFICATIONS
ADG526A/ADG527A
ADG526A
K Version
B Version
T Version
40 C to
40 C to
55 C to
Parameter
25 C
+85 C
25
C +85 C
25 C
+125 C
Unit
Comments
ANALOG
SWITCH
Analog Signal Range
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V min
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V max
R
ON
280
280
280
typ
10 V
V
S
+10 V, I
DS
= 1 mA;
Test Circuit 1
450
600
450
600
450
600
max
300
400
300
400
max
V
DD
= 15 V (
10%), V
SS
= 15 V (
10%)
300
400
max
V
DD
= 15 V (
5%), V
SS
= 15 V (
5%)
R
ON
Drift
0.6
0.6
0.6
%/
C typ
10 V
V
S
+10 V, I
DS
= 1 mA
R
ON
Match
5
5
5
% typ
10 V
V
S
+10 V, I
DS
= 1 mA
I
S
(OFF), Off Input Leakage
0.02
0.02
0.02
nA typ
V1 =
10 V, V2 = 10 V; Test Circuit 2
1
50
1
50
1
50
nA max
I
D
(OFF), Off Output Leakage
0.04
0.04
0.04
nA typ
V1 =
10 V, V2 = 10 V, Test Circuit 3
ADG526A
1
200
1
200
1
200
nA max
ADG527A
1
100
1
100
nA max
I
D
(ON), On Channel Leakage
0.04
0.04
0.04
nA typ
V1 =
10 V, V2 = 10 V; Test Circuit 4
ADG526A
1
200
1
200
1
200
nA max
ADG527A
1
100
1
100
nA max
I
DIFF
, Differential Off Output
Leakage (ADG527A Only)
25
25
nA max
V1 =
10 V, V2 = 10 V; Test Circuit 5
DIGITAL CONTROL
V
INH
, Input High Voltage
2.4
2.4
2.4
V min
V
INL
, Input Low Voltage
0.8
0.8
0.8
V max
I
INL
or I
INH
1
1
1
A max
V
IN
= 0 to V
DD
C
IN
Digital Input Capacitance
8
8
8
pF max
DYNAMIC CHARACTERISTICS
*
t
TRANSITION
200
200
200
ns typ
V1 =
10 V, V2 = 10 V; Test Circuit 6
300
400
300
400
300
400
ns max
t
OPEN
50
50
50
ns typ
Test Circuit 7
25
10
25
10
25
10
ns min
t
ON
(EN,
WR)
200
200
200
ns typ
Test Circuit 8 and 9
300
400
300
400
300
400
ns max
t
OFF
(EN,
RS)
200
200
200
ns typ
Test Circuit 8 and 10
300
400
300
400
300
400
ns max
t
W
Write Pulsewidth
100
120
100
120
100
130
ns min
See Figure 1
t
S
Address Enable Setup Time
100
100
100
ns min
See Figure 1
t
H
Address Enable Hold Time
10
10
10
ns min
See Figure 1
t
RS
Reset Pulsewidth
100
100
100
ns min
See Figure 2
OFF Isolation
68
68
68
dB typ
V
EN
= 0.8 V, R
L
= 1 k
, C
L
= 15 pF,
V
S
= 7 V rms, f = 100 kHz
50
50
50
dB min
V
S
= 7 V rms, f = 100 kHz
C
S
(OFF)
5
5
5
pF typ
V
EN
= 0.8 V
C
D
(OFF)
ADG526A
44
44
44
pF typ
V
EN
= 0.8 V
ADG527A
22
22
pF typ
Q
INJ
, Charge Injection
4
4
4
pC typ
R
S
= 0
, V
S
= 0 V; Test Circuit 11
POWER SUPPLY
I
DD
0.6
0.6
0.6
mA typ
V
IN
= V
INL
or V
INH
1.5
1.5
1.5
mA max
I
SS
20
20
20
A typ
V
IN
= V
INL
or V
INH
0.2
0.2
0.2
mA max
Power Dissipation
10
10
10
mW typ
28
28
28
mW max
*Sample tested at 25 C to ensure compliance.
Specifications subject to change without notice.
Dual Supply
(V
DD
= +10.8 V to +16.5 V, V
SS
= 1O.8 V to 16.5 V unless otherwise noted.)
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REV. B
3
ADG526A/ADG527A
ADG526A/ADG527A
ADG526A
K Version
B Version
T Version
40 C to
40 C to
55 C to
Parameter
25 C
+85 C
25
C +85 C
25 C
+125 C
Unit
Comments
ANALOG SWITCH
Analog Signal Range
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V min
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V max
R
ON
500
500
500
typ
0 V
V
S
10 V, I
DS
= 0.5 mA;
Test Circuit 1
700
1000
700
1000
700
1000
max
R
ON
Drift
0.6
0.6
0.6
%/
C typ
0 V
V
S
10 V, I
DS
= 0.5 mA
R
ON
Match
5
5
5
% typ
0 V
V
S
10 V, I
DS
= 0.5 mA
I
S
(OFF), Off Input Leakage
0.02
0.02
0.02
nA typ
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 2
1
50
1
50
1
50
nA max
I
D
(OFF), Off Output Leakage
0.04
0.04
0.04
nA typ
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 3
ADG526A
1
200
1
200
1
200
nA max
ADG527A
1
100
1
100
nA max
I
D
(ON), On Channel Leakage
0.04
0.04
0.04
nA typ
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 4
ADG526A
1
200
1
200
1
200
nA max
ADG527A
1
100
1
100
nA max
I
DIFF
, Differential Off Output
Leakage (ADG527A only)
25
25
nA max
V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 5
DIGITAL CONTROL
V
INH,
Input High Voltage
2.4
2.4
2.4
V min
V
INL
, Input Low Voltage
0.8
0.8
0.8
V max
I
INL
or I
INH
1
1
1
A max
V
IN
= 0 to V
DD
C
IN
Digital Input Capacitance
8
8
8
pF max
DYNAMIC CHARACTERISTICS
*
t
TRANSITION
300
300
300
ns typ
V1 = 10 V/0 V, V2 = 0 V/10 V;
450
600
450
600
450
600
ns max
Test Circuit 6
t
OPEN
50
50
50
ns typ
Test Circuit 7
25
10
25
10
25
10
ns min
t
ON
(EN,
WR)
250
250
250
ns typ
Test Circuits 8 and 9
450
600
450
600
450
600
ns max
t
OFF
(EN,
RS)
250
250
250
ns typ
Test Circuits 8 and 10
450
600
450
600
450
600
ns max
t
W
Write Pulsewidth
100
120
100
120
100
130
ns min
See Figure 1
t
S
Address Enable Setup Time
100
100
100
ns min
See Figure 1
t
H
Address Enable Hold Time
10
10
10
ns min
See Figure 1
t
RS
Reset Pulsewidth
100
100
100
ns min
See Figure 2
OFF Isolation
68
68
68
dB typ
V
EN
= 0.8 V, R
L
= 1 k
, C
L
= 15 pF
50
50
50
dB min
V
S
= 3.5 V rms, f = 100 kHz
C
S
(OFF)
5
5
5
pF typ
V
EN
= 0.8 V
C
D
(OFF)
ADG526A
44
44
44
pF typ
V
EN
= 0.8 V
ADG527A
22
22
pF typ
Q
INJ
, Charge Injection
4
4
4
pC typ
R
S
= 0
, V
S
= 0 V; Test Circuit 11
POWER SUPPLY
I
DD
0.6
0.6
0.6
mA typ
V
IN
= V
INL
or V
INH
1.5
1.5
1.5
mA max
Power Dissipation
11
11
11
mW typ
25
25
25
mW max
*Sample tested at 25
C to ensure compliance.
Specifications subject to change without notice.
Single Supply
(V
DD
= 10.8 V to 16.5 V, V
SS
= GND to 0 V unless otherwise noted.)
background image
REV. B
ADG526A/ADG527A
4
TIMING DIAGRAMS
3V
0V
3V
0V
WR
EN A0, A1, A2, (A3)
1.5V
2.0V
0.8V
t
H
t
W
t
S
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level-sensitive; there-
fore, while
WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of
WR.
ORDERING GUIDE
Model
1
Temperature Range
Package Option
2
ADG526AKN
40
C to +85C
N-28
ADG526AKR
40
C to +85C
R-28
ADG526AKP
40
C to +85C
P-28A
ADG526ABQ
40
C to +85C
Q-28
ADG526ATQ
3
55
C to +125C
Q-28
ADG526ATE
3
55
C to +125C
E-28A
ADG527AKN
40
C to +85C
N-28
ADG527AKR
40
C to +85C
R-28
ADG527AKP
40
C to +85C
P-28A
ADG527ABQ
40
C to +85C
Q-28
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
See Analog Devices Military Products Databook (1990) for military data.
2
E = Leadless Ceramic Chip Carrier; N = Narrow Plastic DIP; P = Plastic
Leaded Chip Carrier; Q = CERDIP; R = 0.3" Small Outline IC (SOIC).
3
Standard Military Drawing (SMD) assigned by DESC. SMD numbers are:
5962-89710013X (ADG526ATE/883B)
5962-8971001XX (ADG526ATQ/883B)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG526A/ADG527A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
C unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Analog Inputs
2
Voltage at S, D . . . . . . . . . . . . . . . . V
SS
2 V to V
DD
+ 2 V
. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs
2
Voltage at A, EN,
WR, RS . . . . . . . . . V
SS
4 V to V
DD
+ 4 V
. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Power Dissipation (Any Package)
Up to 75
C by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above 75
C by . . . . . . . . . . . . . . . . . . . . . 6 mW/C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . 40
C to +85C
Industrial (B Version) . . . . . . . . . . . . . . . . . 40
C to +85C
Extended (T Version) . . . . . . . . . . . . . . . . 55
C to +125C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2
Overvoltage at A, EN,
WR, RS, S, or D will be clamped by diodes. Current should
be limited to the maximum rating above.
t
R S
3V
0V
V
O
0V
RS
0.8V
O
t
OFF
(
RS)
1.5V
SWITCH
OUTPUT
Figure 2.
Figure 2 shows the Reset Pulsewidth, t
RS
, and Reset Turn-off
Time, t
OFF
(
RS).
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V, t
R
= t
F
= 20 ns.
background image
REV. B
ADG526A/ADG527A
5
TRUTH TABLES
ADG526A
A3
A2
Al
A0
EN
WR
RS
ON SWITCH
X
X
X
X
X
g
1
Retains Previous Switch Condition
X
X
X
X
X
X
0
NONE (Address and Enable Latches Cleared)
X
X
X
X
0
0
1
NONE
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
2
0
0
1
0
1
0
1
3
0
0
1
1
1
0
1
4
0
1
0
0
1
0
1
5
0
1
0
1
1
0
1
6
0
1
1
0
1
0
1
7
0
1
1
1
1
0
1
8
1
0
0
0
1
0
1
9
1
0
0
1
1
0
1
10
1
0
1
0
1
0
1
11
1
0
1
1
1
0
1
12
1
1
0
0
1
0
1
13
1
1
0
1
1
0
1
14
1
1
1
0
1
0
1
15
1
1
1
1
1
0
1
16
X = Don't Care
ADG527A
A2
Al
A0
EN
WR
RS
ON SWITCH PAIR
X
X
X
X
g
1
Retains Previous Switch Condition
X
X
X
X
X
0
NONE (Address and Enable Latches Cleared)
X
X
X
0
0
1
NONE
0
0
0
1
0
1
1
0
0
1
1
0
1
2
0
1
0
1
0
1
3
0
1
1
1
0
1
4
1
0
0
1
0
1
5
1
0
1
1
0
1
6
1
1
0
1
0
1
7
1
1
1
1
0
1
8
X = Don't Care
background image
REV. B
ADG526A/ADG527A
6
PIN CONFIGURATIONS
DIP, SOIC
LCCC
PLCC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18
S7
S6
S5
S4
S3
S2
S1
S15
S14
S13
S12
S11
S10
S9
S16
RS
NC
V
DD
D
V
SS
S8
GND
WR
A3
A2
A1
A0
EN
NC = NO CONNECT
ADG526A
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18
S7A
S6A
S5A
S4A
S3A
S2A
S1A
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S8B
RS
DB
V
DD
DA
V
SS
S8A
GND
WR
NC
A2
A1
A0
EN
NC = NO CONNECT
ADG527A
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18
S7
S6
S5
S4
S3
S2
S1
S15
S14
S13
S12
S11
S10
S9
S16
RS
NC
V
DD
D
V
SS
S8
GND
WR
A3
A2
A1
A0
EN
ADG526A
NC = NO CONNECT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADG526A
NC = NO CONNECT
A3
WR
GND
S9
S10
S11
S12
V
DD
NC
RS
S16
S13
S14
S15
A2
A1
A0
EN
S1
S2
S3
D
V
SS
S8
S7
S4
S5
S6
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADG527A
NC = NO CONNECT
NC
WR
GND
S1B
S2B
S3B
S4B
V
DD
DB
RS
S8B
S5B
S6B
S7B
A2
A1
A0
EN
S1A
S2A
S3A
DA
V
SS
S8A
S7A
S4A
S5A
S6A
TOP VIEW
(Not to Scale)
background image
REV. B
ADG526A/ADG527A
7
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
SUPPLY VOLTAGE V
1.9
5
TRIGGER LEVEL V
1.8
1.7
1.6
6
7
8
9
10
11
12
13
15
1.5
14
TPC 4. Trigger Levels vs. Power Supply Voltage, Dual or
Single Supply, T
A
= 25
C
SUPPLY VOLTAGE V
800
5
t
TRANSITION

ns
600
400
300
6
7
8
9
10
11
12
13
15
100
14
700
500
200
DUAL
SUPPLY
SINGLE
SUPPLY
TPC 5. t
TRANSITION
vs. Supply Voltage: Dual and Single
Supplies, T
A
= 25
C (Note: For V
DD
and / V
SS
/ <10 V;
V1 = V
DD
/V
SS
, V2 = V
SS
/V
DD
; See Test Circuit 6)
SUPPLY VOLTAGE V
1.0
5
I
DD

mA
0.6
0.2
6
7
8
9
10
11
12
13
16
14
0.8
0.4
15
17
TPC 6. I
DD
vs. Supply Voltage: Dual or Single Supply,
T
A
= 25 C
Typical Performance Characteristics
V
D
(V
S
) V
700
0
20
R
ON

600
500
400
300
200
100
15
10
5
0
5
10
15
20
V
DD
= 15V
V
SS
= 0V
V
DD
= 10.8V
V
SS
= 0V
TPC 1. R
ON
as a Function of V
D
(V
S
): Dual Supply Voltage,
T
A
= 25
C
V
D
(V
S
) V
700
0
20
R
ON

600
500
400
300
200
100
15
10
5
0
5
10
15
20
V
DD
= +15V
V
SS
= 15V
V
DD
= +5V
V
SS
= 5V
V
DD
= +10.8V
V
SS
= 10.8V
TPC 2. R
ON
as a Function of V
D
(V
S
); Single Supply
Voltage, T
A
= 25
C
TEMPERATURE C
100
25
LEAKAGE CURRENT
nA
10
1
0.1
35
45
55
65
75
85
95
105
115
125
V
DD
= +16.5V
V
SS
= 16.5V
I
S
(OFF)
I
D
(ON)
I
D
(OFF)
TPC 3. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply
Voltages Reduce)
background image
REV. B
ADG526A/ADG527A
8
I
DS
V1
S
D
V
S
R
ON
= V1
I
DS
Test Circuit 1. R
ON
A
V2
V1
I
S
(OFF)
D
EN
GND
V
DD
V
SS
V
DD
V
SS
0.8V
Test Circuit 2. I
S
(OFF)
D
A
EN
GND
V
DD
V
SS
V
DD
V
SS
0.8V
V2
V1
I
D
(OFF)
Test Circuit 3. I
D
(OFF)
Test Circuits
V1
D
A
EN
GND
V
DD
V
SS
V
DD
V
SS
2.4V
V2
I
D
(ON)
Test Circuit 4. I
D
(ON)
DA
A
GND
V1
V
DD
V
SS
V
DD
V
SS
EN
V2
ADG527A
DB
A
0.8V
I
DIFF
= I
DA
(OFF) I
DB
(OFF)
Test Circuit 5. I
DIFF
50
V
DD
V
SS
V
DD
V
SS
V1
OUTPUT
ADG526A*
A2
A1
A0
2.4V
EN
GND
S1
S2 THRU S15
S16
D
1M
35pF
*SIMILAR CONNECTION FOR ADG527A
3V
0V
ADDRESS
DRIVE (V
IN
)
OUTPUT
90%
90%
t
TRANSITION
A3
V2
WR
RS
V
IN
50%
t
TRANSITION
Test Circuit 6. Switching Time of Multiplexer, t
TRANSITION
background image
REV. B
ADG526A/ADG527A
9
50
V
DD
V
SS
V
DD
V
SS
5V
OUTPUT
ADG526A*
A2
A1
A0
2.4V
EN
GND
S1
S2 THRU S15
S16
D
1k
35pF
*SIMILAR CONNECTION FOR ADG527A
50%
t
OPEN
3V
0V
ADDRESS
DRIVE (V
IN
)
OUTPUT
A3
WR
RS
V
IN
Test Circuit 7. Break-Before-Make Delay, t
OPEN
50
V
IN
V
DD
V
SS
V
DD
V
SS
5V
OUTPUT
ADG526A*
A2
A1
A0
EN
GND
S1
S2 THRU S16
D
1k
35pF
*SIMILAR CONNECTION FOR ADG527A
3V
0V
ENABLE
DRIVE (V
IN
)
OUTPUT
10%
90%
t
ON
(EN)
t
OFF
(EN)
A3
WR
RS
2.4V
50%
Test Circuit 8. Enable Delay, t
ON
(EN), t
OFF
(EN)
V
DD
V
SS
V
DD
V
SS
50
V
IN
5V
OUTPUT
ADG526A*
A2
A1
A0
WR
GND
S1
S2 THRU S16
D
1k
35pF
*SIMILAR CONNECTION FOR ADG527A
OUTPUT
20%
50%
3V
0V
t
ON
(
WR)
(
WR)
DRIVE (V
IN
)
A3
EN
2.4V
RS
NOTE
DEVICE MUST BE RESET PRIOR TO
APPLYING
WR PULSE
Test Circuit 9. Write Turn-On Time, t
ON
(
WR)
background image
REV. B
ADG526A/ADG527A
10
TERMINOLOGY
R
ON
Ohmic resistance between terminals D and S
R
ON
Match
Difference between the R
ON
of any two channels
R
ON
Drift
Change in R
ON
versus temperature
I
S
(OFF)
Source terminal leakage current when the switch is off
I
D
(OFF)
Drain terminal leakage current when the switch is off
I
D
(ON)
Leakage current that flows from the closed switch into the body
V
S
(V
D
)
Analog voltage on terminal S or D
C
S
(OFF)
Channel input capacitance for "OFF' condition
C
D
(OFF)
Channel output capacitance for "OFF" condition
C
IN
Digital input capacitance
t
ON
(EN)
Delay time between the 50% and 90% points of the digital input and switch "ON" condition
t
OFF
(EN)
Delay time between the 50% and 10% points of the digital input and switch "OFF" condition
t
TRANSITION
Delay time between the 50% and 90% points of the digital inputs
and switch "ON" condition when switching from one address state to another
t
OPEN
"OFF" time measured between 50% points of both switches when switching from one address
state to another
V
INL
Maximum input voltage for Logic "0"
V
INH
Minimum input voltage for Logic "1"
I
INL
(I
INH
)
Input current of the digital input
V
DD
Most positive voltage supply
V
SS
Most negative voltage supply
I
DD
Positive supply current
I
SS
Negative supply current
V
DD
V
SS
V
DD
V
SS
50
V
IN
5V
OUTPUT
ADG526A*
A2
A1
A0
RS
GND
S1
S2 THRU S16
D
1k
35pF
*SIMILAR CONNECTION FOR ADG527A
RS DRIVE (V
IN
)
50%
3V
0V
80%
OUTPUT
t
OFF
(
RS)
A3
EN
2.4V
WR
NOTE
DEVICE
WR MUST PULSED LOW
PRIOR TO APPLYING
RS PULSE
Test Circuit 10. Reset Turn-Off Time, t
OFF
(
RS)
V
DD
V
SS
V
DD
V
SS
V
IN
ADG526A*
A0
A1
A2
2.4V
EN
D
RS
GND
WR
C
L
1nF
S1
V
S
R
S
V
O
A3
50
*SIMILAR CONNECTION FOR ADG527A
3V
V
IN
0V
V
O
V
O
Q
INJ
= C
L
V
O
Test Circuit 11. Charge Injection
background image
REV. B
ADG526A/ADG527A
11
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Plastic DIP (Suffix N)
(N-28)
28
1
14
15
PIN 1
1.450 (36.830)
1.440 (35.580)
0.550 (13.970)
0.530 (13.470)
15
0
0.606 (15.400)
0.594 (15.090)
0.012 (0.306)
0.008 (0.203)
0.200
(5.080)
MAX
SEATING
PLANE
0.020 (0.508)
0.015 (0.381)
0.105 (2.670)
0.096 (2.420)
0.060 (1.580)
0.020 (0.560)
0.175 (4.450)
0.120 (3.050)
28-Terminal Plastic Leaded Chip Carrier (Suffix P)
(P-28A)
4
PIN 1
IDENTIFIER
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
0.495 (12.57)
0.485 (12.32)
SQ
0.456 (11.58)
0.450 (11.43)
SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
28-Lead Cerdip (Suffix Q)
(Q-28)
0.525 (13.33)
0.515 (13.08)
PIN 1
1.49 (37.84) MAX
28
1
14
15
15
0
0.62 (15.74)
0.59 (14.93)
0.012 (0.305)
0.008 (0.203)
0.22
(5.59)
MAX
0.02 (0.5)
0.016 (0.406)
0.11 (2.79)
0.099 (2.28)
0.125
(3.175)
MIN
GLASS
SEALANT
0.06 (1.52)
0.05 (1.27)
0.18 (4.57)
MAX
28-Lead SOIC (R) Package
(R-28)
0.013 (0.32)
0.009 (0.23)
0.005 (1.27)
0.016 (0.40)
0.012 (0.3)
0.004 (0.1)
0.019 (0.49)
0.014 (0.35)
0.104 (2.65)
0.093 (2.35)
0.0500
(1.27)
BSC
28
15
14
1
0.512 (13.00)
0.496 (12.60)
0.419 (10.65)
0.319 (10.00)
0.300 (7.60)
0.292 (7.40)
28-Terminal Leadless Ceramic Chip Carrier (Suffix E)
(E-28A)
1
28
5
11
18
BOTTOM
VIEW
19
25
26
4
12
0.028 (0.71)
0.022 (0.56)
45 TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050
(1.27)
BSC
0.075
(1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.150
(3.51)
BSC
0.300 (7.62)
BSC
0.200
(5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
background image
REV. B
12
C0153202/02(B)
PRINTED IN U.S.A.
ADG526A/ADG527A
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Edits to Specifications Table, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to Specifications Table, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Removal of one PIN CONFIGURATION and diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6