REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADF4216/ADF4217/ADF4218

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

Dual RF PLL Frequency Synthesizers

FUNCTIONAL BLOCK DIAGRAM

22-BIT

DATA

REGISTER

SDOUT

OSCILLATOR

CLOCK

DATA

LOCK

DETECT

MUXOUT

ADF4216/ADF4217/ADF4218

CHARGE

PUMP

PHASE

COMPARATOR

OUTPUT

MUX

REF

PRESCALER

CHARGE

PUMP

PHASE

COMPARATOR

LOCK

DETECT

AGND

DGND

AGND

DGND

PRESCALER

11-BIT IF

B-COUNTER

6-BIT IF

A-COUNTER

N = BP + A

14-BIT IF

R-COUNTER

14-BIT IF

R-COUNTER

11-BIT RF

B-COUNTER

6-BIT RF

A-COUNTER

FEATURES
ADF4216: 550 MHz/1.2 GHz
ADF4217: 550 MHz/2.0 GHz
ADF4218: 550 MHz/2.5 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Currents
Selectable Dual Modulus Prescaler

IF: 8/9 or 16/17
RF: 32/33 or 64/65

3-Wire Serial Interface
Power-Down Mode

APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless LANS
Communications Test Equipment
CATV Equipment

GENERAL DESCRIPTION

The ADF4216/ADF4217/ADF4218 are dual frequency synthe-
sizers that can be used to implement local oscillators (LOs) in
the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P+1). The A (6-bit) and B
(11-bit) counters, in conjunction with the dual modulus prescaler
(P/P+1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizers are
used with an external loop filter and VCOs (Voltage Con-
trolled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.

REV. 0

ADF4216/ADF4217/ADF4218SPECIFICATIONS

1 = V

2 = 3 V 10%, 5 V 10%;

1, V

2 V

1, V

2 6.0 V

; AGND

= DGND

= AGND

= DGND

= 0 V; T

= T

MIN

to T

MAX

unless otherwise noted.)

arameter

B Version

B Chips

Unit

Test Conditions/Comments

RF/IF CHARACTERISTICS (3 V)

RF Input Frequency (RF

)

See Figure 3 for Input Circuit.

ADF4216

0.2/1.2

GHz min/max

For lower frequency operation (below the

ADF4217

0.2/2.0

GHz min/max

minimum stated) use a square wave source.

ADF4218

0.5/2.5

GHz min/max

IF Input Frequency (IF

)

45/550

MHz min/max

RF Input Sensitivity

15/+4

dBm min/max

IF Input Sensitivity

10/+4

dBm min/max

Maximum Allowable
Prescaler Output Frequency

165

MHz max

RF/IF CHARACTERISTICS (5 V)

RF Input Frequency (RF

)

See Figure 3 for Input Circuit.

ADF4216

0.2/1.2

GHz min/max

For lower frequency operation (below the

ADF4217

0.2/2.0

GHz min/max

minimum stated) use a square wave source.

ADF4218

0.5/2.5

GHz min/max

IF Input Frequency (IF

)

25/550

MHz min/max

RF Input Sensitivity

15/+4

dBm min/max

IF Input Sensitivity

10/+4

dBm min/max

Maximum Allowable
Prescaler Output Frequency

200

MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency

5/40

MHz min/max

For f < 5 MHz, use dc-coupled square wave
(0 to V

REFIN Input Sensitivity

0.5

V p-p min

AC-Coupled. When DC-Coupled:
0 to V

max (CMOS-Compatible)

REFIN Input Capacitance

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency

MHz max

CHARGE PUMP

Sink/Source

High Value

4.5

mA typ

Low Value

1.125

mA typ

Absolute Accuracy

% typ

Three-State Leakage Current

nA typ

Sink and Source Current Matching

% typ

vs. V

% max

0.5 V V

0.5 V

vs. Temperature

% typ

= V

LOGIC INPUTS

INH

, Input High Voltage

0.8

× V

0.8

× V

V min

INL

, Input Low Voltage

0.2

× V

0.2

× V

V max

INH

INL

, Input Current

±1

µA max

, Input Capacitance

pF max

Oscillator Input Current

±100

µA max

LOGIC OUTPUTS

, Output High Voltage

0.4

V min

= 500

µA

, Output Low Voltage

0.4

V max

= 500

µA

POWER SUPPLIES

2.7/5.5

V min/V max

1/6.0

V min/V max

6.0 V

REV. 0

ADF4216/ADF4217/ADF4218

Parameter

B Version

B Chips

Unit

Test Conditions/Comments

POWER SUPPLIES (Continued)

(RF + IF)

See TPC 22 and TPC 23

ADF4216

mA max

9.0 mA typical at V

= 3 V and T

= 25

°C

ADF4217

mA max

12 mA typical at V

= 3 V and T

= 25

°C

ADF4218

mA max

14 mA typical at V

= 3 V and T

= 25

°C

(RF Only)

ADF4216

mA max

5.0 mA typical at V

= 3 V and T

= 25

°C

ADF4217

mA max

7.0 mA typical at V

= 3 V and T

= 25

°C

ADF4218

mA max

9.0 mA typical at V

= 3 V and T

= 25

°C

(IF Only)

ADF4216

4.5

mA max

4.5 mA typical at V

= 3 V and T

= 25

°C

ADF4217

4.5

mA max

4.5 mA typical at V

= 3 V and T

= 25

°C

ADF4218

4.5

mA max

4.5 mA typical at V

= 3 V and T

= 25

°C

1 + I

0.6

mA max

= 25

°C

Low-Power Sleep Mode

µA max

0.5

µA typical

NOISE CHARACTERISTICS

Phase Noise Floor

171

dBc/Hz typ

@ 25 kHz PFD Frequency

164

dBc/Hz typ

@ 200 kHz PFD Frequency

Phase Noise Performance

@ VCO Output

ADF4216, ADF4217, ADF4218 (IF)

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

ADF4216 (RF): 900 MHz Output

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

ADF4217 (RF): 900 MHz Output

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

ADF4218 (RF): 900 MHz Output

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

ADF4216 (RF): 836 MHz Output

dBc/Hz typ

@ 300 Hz Offset and 30 kHz PFD Frequency

ADF4217 (RF): 1750 MHz Output

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

ADF4217 (RF): 1750 MHz Output

dBc/Hz typ

@ 200 Hz Offset and 10 kHz PFD Frequency

ADF4218 (RF): 1960 MHz Output

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

Spurious Signals

ADF4216 ADF4217, ADF4218 (IF)

97/106

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4216 (RF): 900 MHz Output

98/106

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4217 (RF): 900 MHz Output

91/100

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4218 (RF): 900 MHz Output

80/84

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4216 (RF): 836 MHz Output

80/84

dB typ

@ 30 kHz/60 kHz and 30 kHz PFD Frequency

ADF4217 (RF): 1750 MHz Output

88/90

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4217 (RF): 1750 MHz Output

65/73

dB typ

@ 10 kHz/20 kHz and 10 kHz PFD Frequency

ADF4218 (RF): 1960 MHz Output

80/84

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

Operating temperature range is as follows: B Version: 40

°C to +85°C.

The B Chip specifications are given as typical values.

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.

1 = V

2 = 3 V; For V

1 = V

2 = 5 V, use CMOS-compatible levels.

Guaranteed by design. Sample tested to ensure compliance.

P = 16; RF

= 900 MHz; IF

= 540 MHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer (f

REFOUT

= 10 MHz @ 0 dBm).

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 540 MHz; N = 2700; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 900 MHz; N = 4500; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 30 kHz; Offset frequency = 300 Hz; f

= 836 MHz; N = 27867; Loop B/W = 3 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 1750 MHz; N = 8750; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 10 kHz; Offset frequency = 200 Hz; f

= 1750 MHz; N = 175000; Loop B/W = 1 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 1960 MHz; N = 9800; Loop B/W = 20 kHz.

Specifications subject to change without notice.

REV. 0

ADF4216/ADF4217/ADF4218

TIMING CHARACTERISTICS

Limit at
T

MIN

to T

MAX

Parameter

(B Version)

Unit

Test Conditions/Comments

ns min

DATA to CLOCK Setup Time

ns min

DATA to CLOCK Hold Time

ns min

CLOCK High Duration

ns min

CLOCK Low Duration

ns min

CLOCK to LE Setup Time

ns min

LE Pulsewidth

NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.

CLOCK

DATA

DB21 (MSB)

DB20

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

Figure 1. Timing Diagram

1 = V

2 = 3 V 10%, 5 V 10%; V

1, V

2 = V

5 V 10%; AGND = DGND = 0 V;

= T

MIN

to T

MAX

unless otherwise noted.)

ABSOLUTE MAXIMUM RATINGS

1, 2

= 25

°C unless otherwise noted)

1 to GND

. . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V

1 to V

2 . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V

1, V

2 to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V

1, V

2 to V

1 . . . . . . . . . . . . . . . . . . . . 0.3 V to +5.5 V

Digital I/O Voltage to GND . . . . . . 0.3 V to DV

+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . . 0.3 V to V

+ 0.3 V

REF

, RF

A, RF

A, IF

B to GND . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . 40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . 65

°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150

°C

TSSOP

Thermal Impedance . . . . . . . . . . . . . 150.4

°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215

°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADF4216BRU

°C to +85°C

Thin Shrink Small Outline Package (TSSOP)

RU-20

ADF4217BRU

°C to +85°C

Thin Shrink Small Outline Package (TSSOP)

RU-20

ADF4218BRU

°C to +85°C

Thin Shrink Small Outline Package (TSSOP)

RU-20

*Contact the factory for chip availability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4216/ADF4217/ADF4218 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

ADF4216/ADF4217/ADF4218

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic

Function

Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. V

1 should have a value of between 2.7 V and 5.5 V. V

1 must

have the same potential as V

Power Supply for the RF Charge Pump. This should be greater than or equal to V

Output from the RF Charge Pump. When enabled this provides

±I

to the external loop filter, which in

turn drives the external VCO.

DGND

Ground Pin for the RF Digital Circuitry.

Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.

AGND

Ground Pin for the RF Analog Circuitry.

REF

Reference Input. This is a CMOS input with a nominal threshold of V

/2 and an equivalent input resis-

tance of 100 k

. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.

DGND

Ground Pin for the IF Digital (Interface and Control Circuitry).

MUXOUT

This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Fre-
quency to be accessed externally. See Table V.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.

AGND

Ground Pin for the IF Analog Circuitry.

Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.

Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.

DGND

Ground Pin for the IF Digital, Interface, and Control Circuitry.

Output from the IF Charge Pump. When enabled this provides

±I

to the external loop filter, which in turn

drives the external VCO.

Power Supply for the IF Charge Pump. This should be greater than or equal to V

Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. V

2 should have a value of between 2.7 V

and 5.5 V. V

2 must have the same potential as V

PIN CONFIGURATION

REF

CLK

DATA

MUXOUT

AGND

DGND

AGND

DGND

TSSOP

ADF4216/
ADF4217/

ADF4218

REV. 0

ADF4216/ADF4217/ADF4218

Typical Performance Characteristics

FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE OHMS
GHz

FREQ MAGS11 ANGS11
1.35 0.816886959 51.80711782
1.45 0.825983016 56.20373378
1.55 0.791737125 61.21554647
1.65 0.770543186 61.88187496
1.75 0.793897072 65.39516615
1.85 0.745765233 69.24884474
1.95 0.7517547 71.21608147
2.05 0.745594889 75.93169947
2.15 0.713387801 78.8391674
2.25 0.711578577 81.71934806
2.35 0.698487131 85.49067481
2.45 0.669871818 88.41958754
2.55 0.668353367 91.70921678

FREQ MAGS11 ANGS11
0.0 0.957111193 3.130429321
0.15 0.963546793 6.686426265
0.25 0.953621785 11.19913586
0.35 0.953757706 15.35637483
0.45 0.929831379 20.3793432
0.55 0.908459709 22.69144845
0.65 0.897303634 27.07001443
0.75 0.876862863 31.32240763
0.85 0.849338092 33.68058163
0.95 0.858403269 38.57674885
1.05 0.841888714 41.48606772
1.15 0.840354983 45.97597958
1.25 0.822165839 49.19163116

TPC 1. S-Parameter Data for the AD4218 RF Input
(Up to 2.5 GHz)

RF INPUT FREQUENCY GHz

1.5

35

RF INPUT POWER

dBm

15

20

25

30

10

0.5

= 3.3V

= +85 C

= +25 C

= 40 C

2.5

TPC 2. Input Sensitivity for the ADF4218 (RF)

2kHz

1kHz

900MHz

+1kHz

+2kHz

= 3V, V

= 5V

= 4.375mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

REFERENCE
LEVEL = 4.2dBm

OUTPUT POWER

100

90

80

70

60

50

40

30

20

10

90dBc/Hz

TPC 3. ADF4218 RF Phase Noise (900 MHz, 200 kHz, 20 kHz)

400kHz

200kHz

900MHz

+200kHz

+400kHz

= 3V, V

= 5V

= 4.375mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 30

REFERENCE
LEVEL = 4.2dBm

90dBc

OUTPUT POWER

100

90

80

70

60

50

40

30

20

10

TPC 4. ADF4218 RF Reference Spurs (900 MHz, 200 kHz,
20 kHz)

10dB/DIVISION

= 40dBc/Hz

RMS NOISE = 0.55

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

0.55 rms

PHASE NOISE

dBc/Hz

90

80

70

60

50

40

100

110

120

130

140

TPC 5. ADF4218 RF Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz)

10dB/DIVISION

RL = 40dBc/Hz

RMS NOISE = 0.65

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

0.65 rms

PHASE NOISE

dBc/Hz

90

80

70

60

50

40

100

110

120

130

140

TPC 6. ADF4218 RF Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz)

REV. 0

ADF4216/ADF4217/ADF4218

400kHz

200kHz

900MHz

+200kHz

+400kHz

= 3V, V

= 5V

= 4.375mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 30

REFERENCE
LEVEL = 4.2dBm

89dBc

OUTPUT POWER

100

90

80

70

60

50

40

30

20

10

TPC 7. ADF4218 RF Reference Spurs (900 MHz, 200 kHz,
35 kHz)

400Hz

200Hz

1750MHz

+200Hz

+400Hz

= 3V, V

= 5V

= 4.375mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

AVERAGES = 10

REFERENCE
LEVEL = 8.0dBm

74dBc/Hz

OUTPUT POWER

100

90

80

70

60

50

40

30

20

10

TPC 8. ADF4218 RF Phase Noise (1750 MHz, 30 kHz, 3 kHz)

10dB/DIVISION

= 40dBc/Hz

RMS NOISE = 1.8

100Hz

FREQUENCY OFFSET FROM 1750MHz CARRIER

1MHz

1.8 rms

PHASE NOISE

dBc/Hz

90

80

70

60

50

40

100

110

120

130

140

TPC 9. ADF4218 RF Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)

80kHz

40kHz

1750MHz

+40kHz

+80kHz

= 3V, V

= 5V

= 4.375mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255 SECONDS

POSITIVE PEAK DETECT

MODE

REFERENCE
LEVEL = 5.7dBm

10

20

30

40

50

60

70

80

90

100

POWER OUTPUT

78dBc/Hz

TPC 10. ADF4218 RF Reference Spurs (1750 MHz,
30 kHz, 3 kHz)

PHASE DETECTOR FREQUENCY kHz

10000

100

1000

180

PHASE NOISE

dBc/Hz

140

150

160

170

120

130

= 3V

= 5V

TPC 11. ADF4218 RF Phase Noise vs. PFD Frequency

TEMPERATURE C

100

40

100

PHASE NOISE

dBc/Hz

70

80

90

60

20

= 3V

TPC 12. ADF4218 RF Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)

REV. 0

ADF4216/ADF4217/ADF4218

TEMPERATURE C

100

40

100

FIRST REFERENCE SPUR

dBc 70

80

90

60

20

= 3V

= 5V

TPC 13. ADF4218 RF Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)

TUNING VOLTAGE Volts

105

FIRST REFERENCE SPUR

dBc

75

85

95

= 3V

= 5V

65

35

45

55

15

25

TPC 14. ADF4218 RF Reference Spurs vs. V

TUNE

(900 MHz,

200 kHz, 20 kHz)

2kHz

1kHz

900MHz

+1kHz

+2kHz

= 3V, V

= 5V

= 4.375mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

89dBc/Hz

REFERENCE
LEVEL = 4.2dBm

OUTPUT POWER

100

90

80

70

60

50

40

30

20

10

TPC 15. ADF4218 IF Phase Noise (540 MHz, 200 kHz, 20 kHz)

10dB/DIVISION

= 40dBc/Hz

RMS NOISE = 0.52

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

0.60 rms

PHASE NOISE

dBc/Hz

90

80

70

60

50

40

100

110

120

130

140

TPC 16. ADF4218 IF Integrated Phase Noise (540 MHz,
200 kHz, 20 kHz)

400kHz

200kHz

900MHz

+200kHz

+400kHz

= 3V, V

= 5V

= 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 2.5 SECONDS

AVERAGES = 30

REFERENCE
LEVEL = 4.2dBm

88.0dBc

OUTPUT POWER

100

90

80

70

60

50

40

30

20

10

TPC 17. ADF4218 IF Reference Spurs (540 MHz, 200 kHz,
20 kHz)

PHASE DETECTOR FREQUENCY kHz

10000

100

1000

180

PHASE NOISE

dBc/Hz

140

150

160

170

120

130

= 3V

= 5V

TPC 18. ADF4218 IF Phase Noise vs. PFD Frequency

REV. 0

ADF4216/ADF4217/ADF4218

TEMPERATURE C

100

40

100

PHASE NOISE

dBc/Hz

70

80

90

60

20

= 3V

TPC 19. ADF4218 IF Phase Noise vs. Temperature
(540 MHz, 200 kHz, 20 kHz)

TEMPERATURE C

100

40

100

FIRST REFERENCE SPUR

dBc

70

80

90

60

20

= 3V

= 5V

TPC 20. ADF4218 IF Reference Spurs vs. Temperature
(540 MHz, 200 kHz, 20 kHz)

TUNING VOLTAGE Volts

105

FIRST REFERENCE SPUR

dBc

75

85

95

= 3V

= 5V

65

35

45

55

15

25

TPC 21. ADF4218 IF Reference Spurs vs. V

TUNE

(900 MHz,

200 kHz, 20 kHz)

PRESCALER OUTPUT FREQUENCY MHz

200

150

= 3V

3.0

2.5

1.5

1.0

2.0

0.5

100

TPC 22. DI

vs. Prescaler Output Frequency (ADF4218,

RF Only)

PRESCALER VALUE

32/33

64/65

ADF4218

ADF4217

ADF4216

TPC 23. ADF4218 AI

vs. Prescaler Value (RF)

REV. 0

ADF4216/ADF4217/ADF4218

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

on power-down.

BUFFER

100k

SW2

SW1

REF

SW3

TO
R COUNTER

POWER-DOWN

CONTROL

Figure 2. Reference Input Stage

IF/RF INPUT STAGE

The IF/RF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.

BIAS

GENERATOR

AGND

Figure 3. IF/RF Input Stage

PRESCALER

The dual modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the IF/RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.

The prescaler is selectable. On the IF side it can be set to
either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17
(DB20 set to 1). On the RF side it can be set to 64/65 (DB20 of
the RF AB Counter Latch set to 0) or 32/33 (DB20 set to 1).
See Tables IV and VI.

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 165 MHz or less. Typically they will work
with 200 MHz output from the prescaler.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:

VCO

= [(P

× B) + A] × f

REFIN

VCO

= Output frequency of external voltage controlled oscilla-

tor (VCO).

= Preset modulus of dual modulus prescaler (8/9, 16/17,

etc.).

= Preset Divide Ratio of binary 11-bit counter (1 to

2047).

= Preset Divide Ratio of binary 6-bit A counter (0 to

63).

REFIN

= Output frequency of the external reference frequency

oscillator.

= Preset divide ratio of binary 14-bit programmable

reference counter (1 to 16383).

R COUNTER

The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

N = BP+A

PRESCALER

P/P+1

MODULUS

CONTROL

LOAD

11-BIT B

COUNTER

6-BIT A

COUNTER

DIVIDER

FROM IF/RF

INPUT STAGE

TO PFD

Figure 4. A and B Counters

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP

The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.

CHARGE

PUMP

DELAY

ELEMENT

CLR1

CLR2

DOWN

 IN

Figure 5. PFD Simplified Schematic

REV. 0

ADF4216/ADF4217/ADF4218

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4216 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11 and P12. See Tables
III and V. Figure 6 shows the MUXOUT section in block dia-
gram form.

CONTROL

MUXOUT

MUX

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT

IF N COUNTER OUTPUT

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT

RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

DGND

Figure 6. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for analog lock detect. The N-
channel open-drain analog lock detect should be operated with
an external pull-up resistor of 10 k

nominal. When lock has

been detected it is high with narrow low-going pulses.

INPUT SHIFT REGISTER

The functional block diagram for the ADF4216 family is shown
on Page 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter and an 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the 22-
bit shift register on each rising edge of CLK. The data is clocked in
MSB first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. The destination latch is
determined by the state of the two control bits (C2, C1) in the
shift register. These are the two LSBs DB1, DB0 as shown in
the timing diagram of Figure 1. The truth table for these bits is
shown in Table I.

Table I. C2, C1 Truth Table

Control Bits
C2

Data Latch

IF R Counter

IF AB Counter (and Prescaler Select)

RF R Counter

RF AB Counter (and Prescaler Select)

PROGRAM MODES

Table III and Table V show how to set up the Program Modes
in the ADF4216 family. The following should be noted:

1. IF and RF Analog Lock Detect indicate when the PLL is in

lock. When the loop is locked and either IF or RF Analog
Lock Detect is selected, the MUXOUT pin will show a logic
high with narrow low-going pulses. When the IF/RF Analog
Lock Detect is chosen, the locked condition is indicated only
when both IF and RF loops are locked.

2. The IF Counter Reset mode resets the R and N counters in

the IF section and also puts the IF charge pump into three-
state. The RF Counter Reset mode resets the R and N counters
in the RF section and also puts the RF charge pump into
three-state. The IF and RF Counter Reset mode does both
of the above.

Upon removal of the reset bits, the N counter resumes counting
in close alignment with the R counter (maximum error is one
prescaler output cycle).

3. The Fastlock mode uses MUXOUT to switch a second loop

filter damping resistor to ground during Fastlock operation.
Activation of Fastlock occurs whenever RF CP Gain in the
RF Reference counter is set to one.

POWER-DOWN

It is possible to program the ADF4216 family for either synchro-
nous or asynchronous power-down on either the IF or RF side.

Synchronous IF Power-Down

Programming a "1" to P7 of the ADF4216 family will initiate a
power-down. If P2 of the ADF4216 family has been set to "0"
(normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
State and then complete the power-down.

Asynchronous IF Power-Down

If P2 of the ADF4216 family has been set to "1" (three-state the
IF charge pump), and P7 is subsequently set to "1," then an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the "1" to
the IF power-down bit (P7).

Synchronous RF Power-Down

Programming a "1" to P16 of the ADF4216 family will initiate a
power-down. If P10 of the ADF4216 family has been set to "0"
(normal operation), a synchronous power-down is conducted. The
device will automatically put the charge pump into three-state
and then complete the power-down.

Asynchronous RF Power-Down

If P10 of the ADF4216 families has been set to "1" (three-state
the RF charge pump), and P16 is subsequently set to "1," an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the "1" to
the RF power-down bit (P16).

Activation of either synchronous or asynchronous power-down
forces the IF/RF loop's R and N dividers to their load state
conditions and the IF/RF input section is debiased to a high
impedance state.

The REF

oscillator circuit is only disabled if both the IF and

RF power-downs are set.

The input register and latches remain active and are capable of
loading and latching data during all the power-down modes.

The IF/RF section of the devices will return to normal powered
up operation immediately upon LE latching a "0" to the appro-
priate power-down bit.

REV. 0

ADF4216/ADF4217/ADF4218

Table II. ADF4216 Family Latch Summary

6-BIT A COUNTER

POWER-DOWN

NOT USED

PRESCALER

IF PD

POLARITY

THREE-STATE

NOT USED

IF CP GAIN

IF LOCK

DETECT

IF F

IF AB COUNTER LATCH

14-BIT REFERENCE COUNTER, R

11-BIT B COUNTER

RF REFERENCE COUNTER LATCH

RF AB COUNTER LATCH

CONTROL

BITS

CONTROL

BITS

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R14

R13

R12

R11

R10

C2 (0)

C1 (0)

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

B11

B10

C2 (0)

C1 (1)

RE F

RF LOCK

DETECT

14-BIT REFERENCE COUNTER, R

CONTROL

BITS

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R14

R13

R12

R11

R10

C2 (1)

C1 (0)

THREE-STATE

RF CP GAIN

RF PD

POLARITY

NOT USED

6-BIT A COUNTER

POWER-DOWN

NOT USED

PRESCALER

11-BIT B COUNTER

CONTROL

BITS

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

B11

B10

C2 (1)

C1 (1)

IF REFERENCE COUNTER LATCH

REV. 0

ADF4216/ADF4217/ADF4218

Table III. IF Reference Counter Latch Map

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

IF CP GAIN

IF PD

POLARITY

R14

R13

R12

..........

DIVIDE RATIO

..........

16380

..........

16381

..........

16382

..........

16383

P1 PHASE DETECTOR POLARITY

0 NEGATIVE
1 POSITIVE

1.25mA

4.375mA

THREE-STATE

IF LOCK

DETECT

IF F

CHARGE PUMP

OUTPUT

NORMAL

THREE-STATE

FROM RFR LATCH

P12

P11

MUXOUT

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

RF REFERENCE DIVIDER

RF N DIVIDER

FASTLOCK OUTPUT SWITCH ON

AND CONNECTED TO MUXOUT

IF COUNTER RESET

RF COUNTER RESET

IF AND RF COUNTER RESET

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R14

R13

R12

R11

R10

C2 (0)

C1 (0)

REV. 0

ADF4216/ADF4217/ADF4218

Table IV. IF AB Counter Latch Map

CONTROL

BITS

6-BIT A COUNTER

11-BIT B COUNTER

POWER-DOWN

B11

B10

B COUNTER DIVIDER RATIO

..........

NOT ALLOWED

..........

NOT ALLOWED

..........

NOT ALLOWED

..........

2044

..........

2045

..........

2046

..........

2047

A COUNTER

DIVIDE RATIO

N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE
GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY
ADJACENT VALUES OF N, N

MIN

IS (P

 P).

IF PRESCALER

8/9

16/17

IF SECTION

NORMAL OPERATION

POWER-DOWN

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

B11

B10

C2 (0)

C1 (1)

REV. 0

ADF4216/ADF4217/ADF4218

Table V. RF Reference Counter Latch Map

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

RF CP GAIN

RF PD

POLARITY

R14

R13

R12

..........

DIVIDE RATIO

..........

16380

..........

16381

..........

16382

..........

16383

PHASE DETECTOR POLARITY

NEGATIVE

POSITIVE

P13

1.25mA

4.375mA

THREE-STATE

RF LOCK

DETECT

RF F

P10

CHARGE PUMP

OUTPUT

NORMAL

THREE-STATE

FROM IFR LATCH

P12

P11 P4 P3

MUXOUT

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

RF REFERENCE DIVIDER

RF N DIVIDER

FASTLOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT

IF COUNTER RESET

RF COUNTER RESET

IF AND RF COUNTER RESET

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

P12

P11

P10

P13

R14

R13

R12

R11

R10

C2 (1)

C1 (0)

REV. 0

ADF4216/ADF4217/ADF4218

Table VI. RF AB Counter Latch Map

CONTROL

BITS

6-BIT A COUNTER

11-BIT B COUNTER

POWER-DOWN

B11

B10

B COUNTER DIVIDE RATIO

..........

NOT ALLOWED

..........

NOT ALLOWED

..........

NOT ALLOWED

..........

2044

..........

2045

..........

2046

..........

2047

A COUNTER

DIVIDE RATIO

N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE
GREATER THAN OR EQUAL TO A. FOR ENSURE CONTINUOUSLY
ADJACENT VALUES OF N, N

MIN

IS (P

 P).

PRESCALER

P14

RF PRESCALER

64/65

32/33

P16

RF SECTION

NORMAL OPERATION

POWER-DOWN

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

P16

P14

B11

B10

C2 (1)

C1 (1)

REV. 0

ADF4216/ADF4217/ADF4218

IF SECTION
Programmable IF Reference (R) Counter

If control bits C2, C1 are 0, 0 then the data is transferred from
the input shift register to the 14 Bit IF R counter. Table III
shows the input shift register data format for the IF R counter
and the divide ratios possible.

IF Phase Detector Polarity

P1 sets the IF Phase Detector Polarity. When the IF VCO char-
acteristics are positive, this should be set to "1." When they are
negative, it should be set to "0." See Table III.

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when pro-
grammed to a "1." It should be set to "0" for normal operation.
See Table III.

IF Charge Pump Currents

P5 sets the IF Charge Pump current. With P5 set to "0," I

1.25 mA. With P5 set to "1," I

is 4.375 mA. See Table III.

Programmable IF AB Counter

If control bits C2, C1 are 0, 1, the data in the input register is
used to program the IF AB counter. The AB counter consists of
a 6-bit swallow counter (A counter) and 11-bit programmable
counter (B counter). Table IV shows the input register data
format for programming the IF AB counter and the divide ratios
possible.

IF Prescaler Value

P6 in the IF AB Counter Latch sets the IF prescaler value.
Either 8/9 or 16/17 is available. See Table IV.

IF Power-Down

Table III and Table V show the power-down bits in the
ADF4216 family. See Power-Down section for functional
description.

RF SECTION
Programmable RF Reference (R) Counter

If control bits C2, C1 are 1, 0, the data is transferred from the
input shift register to the 14-bit RFR counter. Table V shows
the input shift register data format for the RFR counter and the
divide ratios possible.

RF Phase Detector Polarity

P9 sets the IF Phase Detector Polarity. When the RF VCO
characteristics are positive this should be set to "1." When they
are negative it should be set to "0." See Table V.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when pro-
grammed to a "1." It should be set to "0" for normal operation.
See Table V.

RF Program Modes

Table III and Table V show how to set up the Program Modes
in the ADF4216 family.

RF Charge Pump Currents

P13 sets the RF Charge Pump current. With P13 set to "0," I

is 1.25 mA. With P5 set to "1," I

is 4.375 mA. See Table V.

Programmable RF AB Counter

If control bits C2, C1 are 1, 1, the data in the input register is
used to program the RF N (AB) counter. The AB counter con-
sists of a 6-bit swallow counter (A Counter) and an 11-bit

programmable counter (B Counter). Table VI shows the input
register data format for programming the RF N counter and the
divide ratios possible.

RF Prescaler Value

P14 in the RF AB Counter Latch sets the RF prescaler value.
Either 32/33 or 64/65 is available. See Table VI.

RF Power-Down

Table IV and Table VI show the power-down bits in the ADF4216
family. See Power-Down section for functional description.

RF Fastlock

The RF CP Gain bit (P17) of the RF N register in the ADF4210
family is the Fastlock Enable Bit. Only when this is "1" is IF
Fastlock enabled. When Fastlock is enabled, the RF CP current
is set to its maximum value. Also an extra loop filter damping
resistor to ground is switched in using the FL

pin, thus com-

pensating for the change in loop characteristics while in Fastlock.
Since the RF CP Gain bit is contained in the RF N Counter,
only one write is needed both to program a new output fre-
quency and to initiate Fastlock. To come out of Fastlock, the
RF CP Gain bit on the RF N register must be set to "0." See
Table VI.

APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver

Figure 7 shows the ADF4216 being used in a classic superhet-
erodyne receiver to provide the required LOs (Local Oscillators).

In this circuit, the reference input signal is applied to the circuit
at REF

and is being generated by a 13 MHz TCXO (Tempera-

ture Controlled Crystal Oscillator).

In order to have a channel spacing of 200 kHz (the GSM stan-
dard), the reference input must be divided by 65, using the
on-chip reference counter.

The RF output frequency range is 1050 MHz to 1085 MHz. Loop
filter component values are chosen so that the loop bandwidth is
20 kHz. The synthesizer is set up for a charge pump current of
4.375 mA and the VCO sensitivity is 15.6 MHz/V.

The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.

Local Oscillator for WCDMA Receiver

Figure 8 shows the ADF4217 being used to generate the local
oscillator frequencies for a Wideband CDMA (WCDMA) system.

The RF output range needed is 1720 MHz to 1780 MHz. The
VCO1901750T will accomplish this. Channel spacing is 200 kHz
with a 20 kHz loop bandwidth. VCO sensitivity is 32 MHz/V.
Charge pump current of 4.375 mA is used and the desired phase
margin for the loop is 45

°.

The IF output is fixed at 200 MHz. The VCO190200T is
used. It has a sensitivity of 11.5 MHz/V. Channel spacing and
loop bandwidth is chosen to be the same as the RF side.

REV. 0

ADF4216/ADF4217/ADF4218

400pF

VCO190-125T

100pF

3.3k

100pF

3.9nF

1nF

MUXOUT

ADF4216

REF

CLK

DATA

DGND

AGND

DGND

AGND

VCO190-1068U

100pF 18

100pF

LOCK
DETECT

OUT

13MHz

TCXO

SPI-COMPATIBLE

SERIAL BUS

DECOUPLING CAPACITORS (22 F/10pF) ON V

1, V

OF THE ADF4216, THE TCXO, AND

ON V

OF THE VCOs, HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

620pF

5.8k

6nF

3.3k

Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4216

VCO190-200T

100pF

3.3k

100pF

1nF

MUXOUT

ADF4217

REF

CLK

DATA

DGND

AGND

DGND

AGND

VCO190-1750T

100pF 18

100pF

LOCK
DETECT

OUT

10MHz

TCXO

DECOUPLING CAPACITORS (22 F/10pF) ON V

1, V

OF THE ADF4217, THE TCXO, AND

ON V

OF THE VCOs, HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

SPI-COMPATIBLE

SERIAL BUS

2.4nF

1.5k

24nF

450pF

760pF

690pF

4.7k

7.5nF

3.3k

Figure 8. Local Oscillator for WCDMA Receiver Using the ADF4217

REV. 0

ADF4216/ADF4217/ADF4218

INTERFACING

The ADF4216/ADF4217/ADF4218 family has a simple SPI-
compatible serial interface for writing to the device. SCLK,
SDATA, and LE (Latch Enable) control the data transfer. When
LE goes high, the 22 bits that have been clocked into the input
register on each rising edge of SCLK will be transferred to the
appropriate latch. See Figure 1 for the Timing Diagram and
Table I for the Latch Truth Table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 ms. This is certainly more than
adequate for systems that will have typical lock times in hun-
dreds of microseconds.

ADuC812 Interface

Figure 9 shows the interface between the ADF421x family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF421x family
needs a 22-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.

On first applying power to the ADF421x family, it requires four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 side) for the output to become active.

When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be about
180 kHz.

ADuC812

ADF4216/
ADF4217/
ADF4218

SCLK

SDATA

MUXOUT
(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

Figure 9. ADuC812 to ADF421x Family Interface

ADSP-2181 Interface

Figure 10 shows the interface between the ADF421x family and
the ADSP-21xx Digital Signal Processor. As previously noted,
the ADF421x family needs a 22-bit serial word for each latch
write. The easiest way to accomplish this using the ADSP-21xx
family is to use the Autobuffered Transmit Mode of operation
with Alternate Framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 22-bit word. To program each 22-bit latch,
store the three 8-bit bytes, enable the Autobuffered mode and
then write to the transmit register of the DSP. This last opera-
tion initiates the autobuffer transfer.

ADSP-21xx

ADF4216/
ADF4217/
ADF4218

SCLK

SDATA

MUXOUT
(LOCK DETECT)

SCLK

I/O FLAG

TFS

Figure 10. ADSP-21xx to ADF421x Family Interface

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADF4216

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADF4216