Ultrafast SiGe
Voltage Comparator
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA
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Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
FEATURES
150 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter(DJ)
200 fs random jitter (RJ)
-2 V to +3 V input range with +5 V/-5.2 V supplies
On-chip terminations at both input pinsl
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on Analog Devices, Inc.'s proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers; the ADCMP581
features reduced swing ECL (negative ECL) output drivers; and
the ADCMP582 features reduced-swing PECL (positive ECL)
output drivers.
The three comparators offer 150 ps propagation delay and 100
ps minimum pulse width for 10 Gbps operation with 200 fs
random jitter (RJ). Overdrive and slew rate dispersion is
typically less than 25 ps.
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
TP
TERMINATION
V
TN
TERMINATION
V
N
INVERTING
INPUT
LE INPUT
HYS
Q OUTPUT
Q OUTPUT
LE INPUT
04672-0-001
ADCMP580/
ADCMP581/
ADCMP582
CML/ECL/
PECL
Figure 1.
The 5 V power supplies enable a wide -2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The three inputs have 50 on-chip termination
resistors with the optional capability to be left open (on an
individual pin basis) for applications requiring high impedance
input.
The CML output stage is designed to directly drive 400 mV into
50 transmission lines terminated to ground. The NECL
output stages are designed to directly drive 400 mV into 50
terminated to -2 V. The PECL output stages are designed to
directly drive 400 mV into 50 terminated to V
CCO
- 2 V. High
speed latch and programmable hysteresis are also provided. The
differential latch input controls are also 50 terminated to an
independent V
TT
pin to interface to either CML or ECL or to
PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP package.
2004
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 2 of 16
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Thermal Considerations.............................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Application Information.................................................................. 9
Power/Ground Layout and Bypassing ....................................... 9
ADCMP58x Family of Output Stages ....................................... 9
Using/Disabling the Latch Feature..............................................9
Optimizing High Speed Performance ..................................... 10
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 11
Minimum Input Slew Rate Requirement ................................ 11
Typical Application Circuits.......................................................... 12
Timing Information ....................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
6/04--Revision PrA
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 3 of 16
ELECTRICAL CHARACTERISTICS
V
CCI
= +5.0 V, V
EE
= -5.0 V, V
CCO
= +3.3 V, T
A
= 25C, unless otherwise noted.
Table 1.
Parameter Symbol
Condition
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Input Voltage Range
V
P
, V
N
-2.0
+3.0
V
Input Differential Range
-2.0
+2.0
V
Input Offset Voltage
V
OS
-5.0 2.0 +5.0 mV
Offset Voltage Tempco
V
OS
/d
T
10.0
V/C
Input Bias Current
I
P
, I
N
Open
termination
15.0 30.0 A
Input Bias Current Tempco
50.0
nA/C
Input Offset Current
2.0
5.0
A
Input Capacitance
C
P
, C
N
TBD
pF
Input Resistance
47.5
50
52.5
Input Resistance, Differential Mode
Open termination
50
k
Input Resistance, Common Mode
Open termination
500
k
Active Gain
A
V
48
dB
Common-Mode Rejection
CMRR
V
CM
= -2.0 V to +3.0 V
50
dB
Hysteresis
R
HYS
=
1
mV
LATCH
ENABLE
CHARACTERISTICS
ADCMP580
(CML)
Latch Enable Input Range
-0.8
0
V
Latch Enable Input Differential
0.2
0.4
0.5
V
Latch Setup Time
t
S
V
OD
= 100 mV
60
ps
Latch Hold Time
t
H
V
OD
= 100 mV
0
ps
ADCMP581
(NECL)
Latch Enable Input Range
-1.8
+0.8
V
Latch Enable Input Differential
0.2
0.4
0.5
V
Latch Setup Time
t
S
V
OD
= 100 mV
25
ps
Latch Hold Time
t
H
V
OD
= 100 mV
0
ps
ADCMP582
(PECL)
Latch Enable Input Range
V
CCO
- 1.8
V
CCO
- 0.8
V
Latch Enable Input Differential
0.2
0.4
0.5
V
Latch Setup Time
t
S
V
OD
= 100 mV
5
ps
Latch Hold Time
t
H
V
OD
= 100 mV
0
ps
Latch Enable Input Impedance
47.5
50.0
52.5
ps
Latch to Output Delay
t
PLOH
, t
PLOL
V
OD
= 100 mV
150
ps
Latch Minimum Pulse Width
t
PL
V
OD
= 100 mV
100
ps
DC OUTPUT CHARACTERISTICS
ADCMP580
(CML)
Output Impedance
Z
OUT
47.5
50
52.5
Output Voltage High Level
V
OH
50 to GND
-0.10
-0.05
0.00
V
Output Voltage Low Level
V
OL
50 to GND
V
OH
- 0.45
V
OH
- 0.40
V
OH
- 0.35
V
Output Voltage Differential
50 to GND
350
400
450
mV
Temperature Coefficient, V
OH
V
OH
/d
T
50 to GND
TBD
mV/C
Temperature Coefficient, V
OL
V
OL
/d
T
50 GND
TBD
mV/C
ADCMP581
(NECL)
Output Voltage High Level
V
OH
50 to -2.0 V
-0.90
-0.80
-0.70
V
Output Voltage Low Level
V
OL
50 to -2.0 V
V
OH
- 0.45
V
OH
- 0.40
V
OH
- 0.35
V
Output Voltage Differential
50 to -2.0 V
350
400
450
mV
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 4 of 16
Parameter Symbol
Condition
Min
Typ
Max
Unit
ADCMP582
(PECL)
Output Voltage High Level
V
OH
50 to V
CCO
- 2.0 V
V
CCO
- 0.9
V
CCO
- 0.80
V
CCO
- 0.70
V
Output Voltage Low Level
V
OL
50 to V
CCO
- 2.0 V
V
OH
- 0.45
V
OH
- 0.40
V
OH
- 0.35
V
Output Voltage Differential
50 to V
CCO
- 2.0 V
350
400
450
mV
AC
PERFORMANCE
Propagation Delay
t
PD
V
OD
= 200 mV
150
ps
Propagation Delay
V
OD
= 20 mV
165
ps
Propagation Delay Tempco
t
PD
/d
T
0.5
ps/C
Prop Delay Skew--Rising Transition
to Falling Transition
V
OD
= 200 mV, 5 V/ns
10
ps
Overdrive Dispersion
50 mV < V
OD
< 1.0 V
10
ps
5 mV < V
OD
< 1.0 V
15
ps
Slew Rate Dispersion
2 V/ns to 10 V/ns
25
ps
Pulse Width Dispersion
100 ps to 5 ns
5
ps
Duty Cycle Dispersion
1.0 V/ns, V
CM
= 0.0 V
10
ps
1.0 V/ns, V
CM
= 2.0 V
5
ps
Common-Mode Dispersion
V
OD
= 0.4V , -2 V < V
CM
< 3 V
5
ps/V
Equivalent Input Bandwidth
1
BW
EQ
0.0 V to 400 mV input
t
R
= t
F
= 25 ps, 20/80
8.0
GHz
Toggle Rate
>50% Output Swing
12.5
Gbps
Deterministic Jitter
DJ
V
OD
= 200 mV, 5 V/ns
PRBS
31
- 1 NRZ, 4 Gbps
10
ps
Deterministic Jitter
DJ
V
OD
= 200 mV, 5 V/ns
PRBS
31
- 1 NRZ, 10 Gbps
TBD
ps
RMS Random Jitter
RJ
V
OD
= 200 mV, 5 V/ns, 1.25 GHz
0.2
ps
Minimum Pulse Width
PW
MIN
t
PD
/P
W
< 5 ps
100
ps
Minimum Pulse Width
PW
MIN
t
PD
/P
W
< 10 ps
80
ps
Rise Time
t
R
20/80
35
ps
Fall Time
t
F
20/80
35
ps
POWER
SUPPLY
Positive Supply Voltage
V
CCI
+4.5 +5.0 +5.5 V
Negative Supply Voltage
V
EE
-5.5 -5.0 -4.5 V
Logic Supply Voltage
V
CCO
+4.5/+2.0 +5.0/+2.5 +5.5/+3.0 V
ADCMP580
(CML)
Positive Supply Current
I
VCCI
V
CCI
= +5.0 V, 50 to Ground
6
8
mA
Negative Supply Current
I
VEE
V
EE
= -5.0 V, 50 to Ground
43
50
mA
Power Dissipation
P
D
50 to Ground
244
260
mW
ADCMP581 (NECL)
Positive Supply Current
I
VCCI
V
CCI
= +5.0 V, 50 to -2 V
6
8
mA
Negative Supply Current
I
VEE
V
EE
= -5.0 V, 50 to -2 V
28
35
mA
Power Dissipation
P
D
50 to -2 V
218
240
mW
ADCMP582
(PECL)
Positive Supply Current
I
VCCI
+ I
VCCO
V
CCI
= +5.0 V, V
CCO
= +5.0 V
50 to V
CCO
- 2 V
47 55 mA
Negative Supply Current
I
VEE
V
EE
= -5.0 V, 50 to V
CCO
- 2 V
28
35
mA
Power Dissipation
P
D
50 to V
CCO
- 2 V
253
275
mW
Power Supply Rejection (V
CCI
) PSR
VCCI
V
CCI
=5.0 V + 5%
70
dB
Power Supply Rejection (V
EE
) PSR
VEE
V
EE
=-5.0 V + 5%
75
dB
Power Supply Rejection (V
CCO
) PSR
VCCO
V
CCO
=3.3 V + 5%
70
dB
1
Equivalent Input Bandwidth assumes a simple first-order input response and is calculated with the following formula: BW
EQ
= 0.22/
(tr
COMP
2
tr
IN
2
), where tr
IN
is the 20/80 transition time of a quasi-Gaussian input edge applied to the comparator input and tr
COMP
is the effective transition time digitized by the
comparator.
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
SUPPLY VOLTAGES
Positive Supply Voltage
(V
CCI
to GND)
-0.5 V to +6.0 V
Negative Supply Voltage
(V
EE
to GND)
6.0 V to +0.5 V
Logic Supply Voltage
(V
CCO
to GND)
-0.5 V to +6.0 V
INPUT VOLTAGES
Input Voltage
-3.0 V to +4.0 V
Differential Input Voltage
-2.5 V to +2.5 V
Input Voltage, Latch Enable
-2.5 V to +5.5 V
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to V
EE
)
-5.5 V to +0.5 V
Maximum Input/Output Current
1 mA
OUTPUT CURRENT
ADCMP580 (CML)
-25 mA
ADCMP581 (NECL)
-40 mA
ADCMP582 (PECL)
-40 mA
TEMPERATURE
Operating Temperature, Ambient
-40C to +85C
Operating Temperature, Junction
125C
Storage Temperature Range
-65C to +150C
ESD CAUTION
THERMAL CONSIDERATIONS
The ADCMP580/ADCMP581/ADCMP582 LFCSP 16-lead
package option has a
JA
(junction to ambient thermal
resistance) of 70C/W in still air.
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04672-0-002
Q
LE
PIN 1
INDICATOR
1
V
TP
2
V
P
3
V
N
4
V
TN
11 Q
12 GND
10
9 GND
5
V
C
C
I
6
7
L
E
8
V
T
T
1
5
G
N
D
1
6
V
C
C
I
1
4
H
Y
S
1
3
V
E
E
ADCMP580
TOP VIEW
(Not to Scale)
04672-0-028
Q
LE
PIN 1
INDICATOR
1
V
TP
2
V
P
3
V
N
4
V
TN
11 Q
12 GND
10
9 GND
5
V
C
C
I
6
7
L
E
8
V
T
T
1
5
G
N
D
1
6
V
C
C
I
1
4
H
Y
S
1
3
V
E
E
ADCMP581
TOP VIEW
(Not to Scale)
04672-0-029
Q
LE
PIN 1
INDICATOR
1
V
TP
2
V
P
3
V
N
4
V
TN
11 Q
12 V
CCO
10
9 V
CCO
5
V
C
C
I
6
7
L
E
8
V
T
T
1
5
G
N
D
1
6
V
C
C
I
1
4
H
Y
S
1
3
V
E
E
ADCMP582
TOP VIEW
(Not to Scale)
Figure 2. ADCMP580 Pin Configuration
Figure 3. ADCMP581 Pin Configuration
Figure 4. ADCMP582 Pin Configuration
Table 3. Pin Descriptions
Pin No.
Mnemonic
Description
1 V
TP
Termination Resistor Return Pin for VP Input.
2 V
P
Noninverting Analog Input.
3 V
N
Inverting Analog Input.
4 V
TN
Termination Resistor Return Pin for VN Input.
5, 16
V
CCI
Positive Supply Voltage.
6
LE
Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the
comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator's being
placed into latch mode. LE must be driven in compliment with LE.
7 LE
Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of
the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator's being
placed into latch mode. LE must be driven in compliment with LE.
8 V
TT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP580 (CML output stage), this pin should be connected to the GND ground.
For the ADCMP581 (ECL output stage), this pin should be connected to the 2 V termination potential.
For the ADCMP582 (PECL output stage), this pin should be connected to the V
CCO
2 V termination potential.
9, 12
GND/V
CCO
Digital Ground Pin/Positive Logic Power Supply Terminal.
For the ADCMP580/ADCMP581, this pin should be connected to the GND pin.
For the ADCMP582, this pin should be connected to the positive logic power V
CCO
supply.
10
Q
Inverting Output. Q is logic low if the analog voltage at the noninverting input, V
P
, is greater than the analog
voltage at the inverting input, V
N
, provided that the comparator is in compare mode. See the LE/LE descriptions
(Pins 6 to 7) for more information.
11 Q
Noninverting Output. Q is logic high if the analog voltage at the noninverting input, V
P
, is greater than the analog
voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions
(Pins 6 to 7) for more information.
13 V
EE
Negative Power Supply.
14 HYS Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS
hysteresis control resistor.
15 GND Analog
Ground.
Heatsink N/C
The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left
floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be
soldered to the application board if improved thermal and/or mechanical stability is desired.
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
V
CCI
= +5.0 V, V
EE
= -5.0 V, V
CCO
= +3.3 V, T
A
= 25C, unless otherwise noted.
Figure 5. Propagation Delay vs. Input Overdrive
Figure 6. Propagation Delay vs. Input Common Mode
Figure 7. Propagation Delay vs. Temperature
Figure 8. Rise/Fall Time vs. Temperature
Figure 9. Hysteresis vs. R
HYS
Control Resistor
Figure 10. Input Bias Current vs. Input Differential
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 8 of 16
Figure 11. Input Bias Current vs. Temperature
Figure 12. Input Offset Voltages vs. Temperature
Figure 13. Output Levels vs. Temperature
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 9 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP58x family of comparators is designed for very
high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes,
particularly for the negative supply (V
EE
), the output supply
plane (V
CCO
) and the ground plane (GND). Individual supply
planes are recommended as part of a multilayer board.
Providing the lowest inductance return path for the switching
currents ensures the best possible performance in the target
application.
It is also important to adequately bypass the input and output
supplies. A 1 F electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1F bypass capacitors should
be placed as close as possible to each of the V
EE,
V
CCI,
and
V
CCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
ADCMP58x FAMILY OF OUTPUT STAGES
Specified propagation delay dispersion performance can be
achieved by using proper transmission line terminations. The
outputs of the ADCMP580 comparators are designed to directly
drive 400 mV into 50 cable or microstrip/stripline
transmission lines terminated with 50 referenced to the GND
return. The CML output stage is shown in the simplified
schematic diagram in Figure 14. The outputs are each back-
terminated with 50 for best transmission line matching. The
outputs of the ADCMP581/ADCMP582 are illustrated in
Figure 15 and should be terminated to -2 V for ECL outputs of
ADCMP581 and VCCO - 2 V for PECL outputs of
ADCMP582. As an alternative, Thevenin equivalent
termination networks may also be used. If high speed CML
signals must be routed more than a centimeter, then either
microstrip or stripline techniques is required to ensure proper
transition times and to prevent excessive output ringing and
pulse-width-dependant propagation delay dispersion.
Q
16mA
50
Q
04672-0-014
GND
V
EE
Figure 14. Simplified Schematic Diagram of ADCMP580 CML Output Stage
04672-0-015
GND
V
EE
Q
Q
Figure 15. Simplified Schematic Diagram of
the ADCMP581/ADCMP582 ECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode, and are
internally terminated with 50 resistors to the V
TT
pin. When
using the ADCMP580, V
TT
should be connected to ground.
When using the ADCMP581, V
TT
should be connected to -2 V.
When using the ADCMP582, V
TT
should be connected
externally to V
CCO
- 2 V, preferably to its own low inductance
plane.
When using the ADCMP580/ADCMP582, the latch function
can be disabled by connecting the LE pin to V
EE
with an
external pull-down resistor and leaving the LE pin unconnected.
To prevent excessive power dissipation, the resistor should be
1.5 k. When using the ADCMP581 comparators, the latch can
be disabled by connecting the LE pin to GND with an external
450 resistor, and leaving the LE pin disconnected.
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 10 of 16
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit
performance and can cause oscillation. Discontinuities along
input and output transmission lines can also severely limit the
specified pulse width dispersion performance.
For applications working in a 50 environment, input and
output matching have a significant impact on data-dependant
(or deterministic) jitter (DJ) and pulse width dispersion
performance. The ADCMP58x family of comparators provides
internal 50 termination resistors for both V
P
and V
N
inputs.
The return side for each termination is pinned out separately
with the V
TP
and V
TN
pins, respectively. If the a 50 termination
is desired at one or both of the V
P
/V
N
inputs, the V
TP
and V
TN
pins can be connected (or disconnected) to (from) the desired
termination potential as appropriate. The termination potential
should be carefully bypassed using ceramic capacitors as
discussed previously to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If a 50 termination is not desired, either one or
both of the V
TP
/V
TN
termination pins can be left disconnected.
In this case, the open pins should be left floating with no
external pull downs or bypassing capacitors.
For applications that require high speed operation, but do not
have on-chip 50 termination resistors, some reflections
should be expected because the comparator inputs can no
longer provide matched impedance to the input trace leading
up to the device. It then becomes important to back-match the
drive source impedance to the input transmission path leading
to the input to minimize multiple reflections. For applications in
which the comparator is very close to the driving signal source,
the source impedance should be minimized. High source
impedance in combination with parasitic input capacitance of
the comparator could cause undesirable degradation in
bandwidth at the input, thus degrading the overall response.
Although the ADCMP58x family of comparators has been
designed to minimize input capacitance, some parasitic
capacitance is inevitable. It is therefore recommended that the
drive source impedance should be no more than 50 for best
high speed performance.
COMPARATOR PROPAGATION
DELAY DISPERSION
The ADCMP58x family of comparators has been specifically
designed to reduce propagation delay dispersion over a wide
input overdrive range of 5 mV to 500 mV. Propagation delay
dispersion is a change in propagation delays, which results from
a change in the degree of overdrive or slew rate (how far or fast
the input signal exceeds the switching threshold). The overall
result is a higher degree of timing accuracy.
Propagation delay dispersion is a specification which becomes
important in critical timing applications such as data
communication, automatic test and measurement,
instrumentation, and event driven applications such as pulse
spectroscopy, nuclear instrumentation, and medical imaging.
Dispersion is defined as the variation in the overall propagation
delay as the input overdrive conditions are changed (Figure 16
and Figure 17). For the ADCMP58x family of comparators,
dispersion is typically < 25 ps since the overdrive varies from
5 mV to 500 mV, and the input slew rate varies from 1 V/ns to
10 V/ns. This specification applies for both positive and
negative signals since the ADCMP58x family of comparators
has almost equal delays for positive- and negative-going inputs.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
5mV OVERDRIVE
DISPERSION
V
N
V
OS
04672-0-016
Figure 16. Propagation Delay--Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
V
OS
04672-0-017
Figure 17. Propagation Delay--Slew Rate Dispersion
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 11 of 16
COMPARATOR HYSTERESIS
Adding hysteresis to a comparator is often desirable in a noisy
environment or when the differential inputs are very small or
slow moving. The transfer function for a comparator with
hysteresis is shown in Figure 18. If the input voltage approaches
the threshold from the negative direction, the comparator
switches from a low to a high when the input crosses +V
H
/2.
The new switching threshold becomes -V
H
/2. The comparator
remains in the high state until the threshold -V
H
/2 is crossed
coming from the positive direction. In this manner, noise
centered on 0 V input does not cause the comparator to switch
states unless it exceeds the region bounded by V
H
/2.
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that will reduce high speed performance, and can
even reduce overall stability in some cases.
The ADCMP58x family of comparators offers a programmable
hysteresis feature that can significantly improve the accuracy
and stability of the desired hysteresis. By connecting an external
pull-down resistor from the HYS pin to V
EE
, a variable amount
of hysteresis can be applied. Leaving the HYS pin disconnected
disables the feature and hysteresis is then less than 1 mV as
specified. The maximum range of hysteresis that can be applied
by using this method is approximately 25 mV.
Figure 19 illustrates the amount of applied hysteresis as a
function of external resistor value. The advantage of applying
hysteresis in this manner is improved accuracy, stability, and
reduced component count. An external bypass capacitor is not
required on the HYS pin because it would likely degrade the
jitter performance of the device.
OUTPUT
INPUT
0V
0
1
+V
H
2
V
H
2
04672-0-018
Figure 18. Comparator Hysteresis Transfer Function of the
ADCMP580/ADCMP581
Figure 19. Comparator Hysteresis vs. R
HYS
Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
As with all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input signal crosses the threshold. This oscillation is due in part
to the high input bandwidth of the comparator and the
feedback parasitics inherent in the package. Analog Devices
recommends a minimum slew rate of 50 V/s to ensure a clean
output transition from the ADCMP58x family of comparators
unless hysteresis is programmed as discussed previously.
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 12 of 16
TYPICAL APPLICATION CIRCUITS
Q
ADCMP580
Q
V
IN
V
P
V
TP
V
TN
V
N
LATCH
INPUTS
04672-0-021
50
50
GND
Figure 20. Zero-Crossing Detector with CML Outputs
LATCH
INPUTS
04672-0-024
GND
75
75
50
50
100
100
ADCMP580
Figure 21. Interfacing CML to a 50 Ground-Terminated Instrument
Q
50
50
Q
V
P
V
N
V
P
V
TP
V
TN
V
N
LATCH
INPUTS
04672-0-022
GND
ADCMP580
Figure 22. LVDS to a 50 Back-Terminated (RS)ECL Receiver
V
P
V
N
V
EE
04672-0-025
ADCMP580
50
1.5k
50
Figure 23. Disabling the Latch Feature
50
50
+
Q
Q
V
IN
V
TH
LATCH
INPUTS
04672-0-023
GND
ADCMP580
Figure 24. Comparator with 2 V to +3 V Input Range
HYS
V
EE
50
50
04672-0-026
ADCMP580
0
TO 5k
Figure 25. Adding Hysteresis Using the HYS Control
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 13 of 16
TIMING INFORMATION
Figure 26 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 4 provides a definition of the
terms shown in the figure.
50%
50%
V
N
V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
N
V
OD
t
S
t
PL
04672-0-027
Figure 26. Comparator Timing Diagram
Table 4. Timing Descriptions
Symbol Timing
Description
t
PDH
Input to output high
delay
Propagation delay measured from the time the input signal crosses the reference ( the input offset
voltage) to the 50% point of an output low-to-high transition.
t
PDL
Input to output low
delay
Propagation delay measured from the time the input signal crosses the reference ( the input offset
voltage) to the 50% point of an output high-to-low transition.
t
PLOH
Latch enable to output
high delay
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output low-to-high transition.
t
PLOL
Latch enable to output
low delay
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output high-to-low transition.
t
H
Minimum hold time
Minimum time after the negative transition of the Latch Enable signal that the input signal must
remain unchanged to be acquired and held at the outputs.
t
PL
Minimum latch enable
pulse width
Minimum time that the Latch Enable signal must be high to acquire an input signal change.
t
S
Minimum setup time
Minimum time before the negative transition of the Latch Enable signal that an input signal change
must be present to be acquired and held at the outputs.
t
R
Output rise time
Amount of time required to transition from a low to a high output as measured at the 20% and 80%
points.
t
F
Output fall time
Amount of time required to transition from a high to a low output as measured at the 20% and 80%
points.
V
OD
Voltage overdrive
Difference between the input voltages V
P
and V
N
.
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 14 of 16
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1 INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP VIEW
12 MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
1.65
1.50 SQ*
1.35
BOTTOM
VIEW
16
5
13
8
9
12
4
* COMPLIANTTO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADCMP580BCP
-40C to +85C
LFCSP-16
CP-16
ADCMP581BCP
-40C to +85C
LFCSP-16
CP-16
ADCMP582BCP
-40C to +85C
LFCSP-16
CP-16
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 15 of 16
NOTES
Preliminary Technical Data
ADCMP580/ADCMP581/ADCMP582
Rev. PrA | Page 16 of 16
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04672-0-6/04(PrA)
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