Электронный компонент: AD9889

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REGISTER

CONFIGURATION

LOGIC

SDA

CLK

VSYNC

HSYNC

DE

D[23:0]

S/PDIF

MCLK

HTPG

SCL

Tx0[1:0]

Tx1[1:0]

Tx2[1:0]

TxC[1:0]

SWING_ADJ

I

2

S[3:0]

DDSDA

DDCSCL

MDA

MCL

COLOR

SPACE

CONVERSION

4:2:2

TO

4:4:4

CONVERSION

VIDEO

DATA

CAPTURE

I

2

C

MASTER

I

2

C

SLAVE

HDCP

CONTROLLER

HDCP

CIPHER

HDM

ITX

CORE

XOR

MASK

AUDIO

DATA

CAPTURE

AD9889

0
5
6
7
5

-
0
0

1

2

D0

3

DE

4

HSYNC

7

S/PDIF

6

CLK

5

VSYNC

1

DV

DD

8

MCLK

9

I

2

S0

10

I

2

S1

12

I

2

S3

13

SCLK

14

LRCLK

15

GND

16

PV

DD

17

GND

18

GND

19

PV

DD

20

PV

DD

11

I

2

S2

59

58

57

54

55

56

60

53

52

GND
D15

D16

D19

D18

D17

GND

D20
D21

51

D22

49

MCL

48

MDA

47

SDA

46

SCL

45

DDSDA

44

DDCSCL

43

GND

42

GND

41

AV

DD

50

D23

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PIN 1

AD9889

TOP VIEW

(Not to Scale)

t

SETUP

t

SETUP

t

HOLD

t

HOLD

t

HOLD

INPUT DATA:

D(23:0), DE, SYNCS

INPUT CLOCK-

RISING EDGE

HS DELAY

R0x35, R0x36[7:6]

VS DELAY
R0x36[5:0]

WIDTH

R0x37[4:0], R0x38[7:1]

HEIGHT
R0x39, R0x3A[7:4]

ACTIVE

VIDEO

a

b

a: HSYNC PLACEMENT

R0x30, R0x31[7:6]

b: HSYNC DURATION

R0x31[5:0], R0x32[7:4]

EAV

HSYNC

SAV

a

b

a: VSYNC PLACEMENT

R0x32[3:0], R0x33[7:2]

b: VSYNC DURATION

R0x33[1:0], R0x34

EAV

VSYNC

SAV

�

4096

1

�

�

2

2

1

0

�

4

+

+

+

a1[12:0]

R

IN

[11:0]

�

4096

1

�

a2[12:0]

B

IN

[11:0]

�

4096

1

�

a3[12:0]

G

IN

[11:0]

CSC_Mode[1:0]

R

OUT

[11:0]

a4[12:0]

DIVIDE

BY

N

DIVIDE

BY

CTS

CTS

1

N

1

TMDS

CLOCK

VIDEO CLOCK

N

128

�

f

S

128

�

f

S

SINK DEVICE

SOURCE DEVICE

1

N AND CTS VALUES ARE TRANSMITTED USING THE

"

AUDIO CLOCK REGENERATION

"

PACKET. VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

REGISTER

N

MULTIPLY

BY

N

CYCLE

TIME

COUNTER

LINE1, PIXEL 1

4:3 DISPLAY

TOP HORIZONTAL BAR

BOTTOM HORIZONTAL BAR

ACTIVE LINE START

R0x48, R0x49

ACTIVE LINE END

R0x4A, R0x4B

LINE1, PIXEL 1

4:3 DISPLAY

ACTIVE PIXEL END

R0x4E, R0x4F

ACTIVE PIXEL START

R0x4C, R0x4D

SDA

SCL

t

BUFF

t

STAH

t

DHO

t

DSU

t

DAL

t

DAH

t

STASU

t

STOSU

BIT 7

ACK

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SDA

SCL

POWER PLANE

AD9

88

D

P

NE

DIGITA DATA

E

CE

E

COMPLIANT TO JEDEC STANDARDS MS-026-BEC

1.45
1.40
1.35

0.15
0.05

0.20
0.09

0.10 MAX

COPLANARITY

VIEW A

ROTATED 90

�

CCW

SEATING

PLANE

7

�

3.5

�

0

�

61

60

1

80

20

41

21

40

VIEW A

1.60

MAX

0.75
0.60
0.45

16.20
16.00 SQ
15.80

14.20
14.00 SQ
13.80

0.65

BSC

LEAD PITCH

0.38
0.32
0.22

TOP VIEW

(PINS DOWN)

PIN 1

1