REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Laser Diode Driver

with Light Power Control

AD9661A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FEATURES
< 2 ns Rise/Fall Times
Output Current: 120 mA
Single +5 V Power Supply
Switching Rate: 200 MHz typ
Onboard Light Power Control Loop

APPLICATIONS
Laser Printers and Copiers

and fall times are 2 ns to complement printer applications that
use image enhancing techniques such as pulse width modula-
tion to achieve gray scale and resolution enhancement. Control
signals are TTL/CMOS compatible.

The driver output provides up to 120 mA of current into an
infrared N type laser, and the onboard disable circuit turns off
the output driver and returns the light power control loop to a
safe state.

The AD9661A can also be used in closed-loop applications in
which the output power level follows an analog POWER LEVEL
voltage input. By optimizing the external hold capacitor and
the photo detector, the loop can achieve bandwidths as high as
25 MHz.

The AD9661A is offered in a 28-pin plastic SOIC for
operation over the commercial temperature range (0

C to

+70

C).

GENERAL DESCRIPTION

The AD9661A is a highly integrated driver for laser diode appli-
cations such as printers and copiers. The AD9661A gets feed-
back from an external photo detector and includes an analog
feedback loop to allow users to set the power level of the laser,
and switch the laser on and off at up to 100 MHz. Output rise

FUNCTIONAL BLOCK DIAGRAM

PULSE2

DISABLE

CIRCUIT

DELAY

TTL

DISABLE

PULSE

DAC

GAIN

ANALOG

POWER

LEVEL

SHIFT OUT

LEVEL

SHIFT IN

REF

5pF

*13ns DELAY ON RISING

EDGE; 0ns ON FALLING

1:10

3120mA

OUT

VOLT

REF

1:1

HOLD

REF

LASER

DIODE

+5V

PHOTO
DETECTOR

REF

MONITOR

ANALOG

POWER

MONITOR

GAIN

01.6V

CAL

LEVEL SHIFT IN

REF

SENSE IN

1.0V

MONITOR

OUTPUT

LEVEL

SHIFT

CIRCUIT

AD9661A

AD9661ASPECIFICATIONS

Test

AD9661AKR

Parameter

Level

Temp

Min

Typ

Max

Units

Conditions

ANALOG INPUT

Input Voltage Range, POWER LEVEL

Full

REF

+ 1.6

Input Bias Current, POWER LEVEL

+25

+50

Analog Bandwidth, Control Loop

+25

MHz

HOLD

= 33 pF, R

= 1 k

, C

= 2 pF

Input Voltage Range, LEVEL SHIFT IN

Full

0.1

1.6

Input Bias Current, LEVEL SHIFT IN

+25

Analog Bandwidth, Level Shift

Full

130

MHz

Level Shift Offset

+25

+32

Level Shift Gain

+25

0.95

1.0

1.05

V/V

OUTPUTS

Output Current, I

OUT

+25

120

OUT

= 2.5 V

Output Compliance Range

+25

2.50

5.25

Idle Current

+25

5.0

PULSE = LOW, DISABLE = LOW

Disable Current

+25

1.0

PULSE = LOW, DISABLE = HIGH

SWITCHING PERFORMANCE

Maximum Pulse Rate

+25

200

MHz

Output Current 3 dB

Output Propagation Delay (t

), Rising

Full

2.9

3.9

5.0

Output Propagation Delay (t

), Falling

Full

3.2

3.7

4.3

Output Current Rise Time

Full

1.5

2.0

Output Current Fall Time

Full

1.5

2.0

CAL Aperture Delay

Full

Disable Time

+25

HOLD NODE

Input Bias Current

+25

200

HOLD

= 2.5 V

Input Voltage Range

Full

REF

+ 1.6

Open-Loop Application Only

Minimum External Hold Cap

Full

TTL/CMOS INPUTS

Logic "1" Voltage

+25

2.0

Logic "1" Voltage

Full

2.0

Logic "0" Voltage

+25

0.8

Logic "0" Voltage

Full

0.8

Logic "1" Current

+25

HIGH

= 5.0 V

Logic "0" Current

+25

1.5

LOW

= 0.8 V

BANDGAP REFERENCE

Output Voltage (V

REF

)

+25

1.6

1.8

1.9

Temperature Coefficient

+25

0.1

mV/

Output Current

+25

0.5

1.0

SENSE IN

Current Gain

+25

0.95

1.02

mA/mA

Voltage

+25

0.7

1.0

1.3

Input Resistance

+25

<150

POWER SUPPLY

Voltage

+25

4.75

5.00

5.25

Current

+25

DISABLE = HIGH, V

HOLD

= V

REF

= 5.0 V

NOTES

Based on rise time of closed-loop pulse response. See Performance Curves.

Based on rise time of pulse response.

Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to the 50% point of the rising/falling edge of the output modulation
current.

Rise time measured between the 10% and 90% points of the rising transition of the modulation current.

Fall time measured between the 10% and 90% points of the falling transition of the modulation current.

Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is
held during this test.

Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable
is similar to fall time during normal operation.

PULSE,

PULSE2, DISABLE, and CAL are TTL/CMOS compatible inputs.

Specifications subject to change without notice.

REV. 0

(+V

= +5 V, Temperature = +25 C unless otherwise noted)

AD9661A

REV. 0

ABSOLUTE MAXIMUM RATINGS*

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

POWER LEVEL, LEVEL SHIFT IN . . . . . . . . . . . 0 V to +V

TTL/CMOS INPUTS . . . . . . . . . . . . . . . . . . . . 0.5 V to +V

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Operating Temperature

AD9661AKR . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to +70

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Maximum Junction Temperature . . . . . . . . . . . . . . . . . +150

Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300

*Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.

ORDERING GUIDE

Model

Temperature Range Package Option

AD9661AKR

C to +70

R-28

AD9661AKR-REEL 0

C to +70

R-28 (1000/Reel)

100

450

1250

BANDGAP

REF

1mA

SENSE

1mA

T/H

HOLD

OUTPUT

TTL

INPUT

Equivalent Circuits

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9661A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

EXPLANATION OF TEST LEVELS
Test Level

100% production tested.

II 100% production tested at +25

C, and sample tested at

specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization

testing.

Parameter is a typical value only.

VI All devices are 100% production tested at +25

C; 100%

production tested at temperature extremes for military
devices; sample tested at temperature extremes for
commercial/industrial devices.

AD9661A

REV. 0

PIN DESCRIPTIONS

Pin

Function

OUTPUT

Analog laser diode current output. Connect to cathode of laser diode, anode connected to +V

externally.

POWER LEVEL

Analog voltage input, V

REF

to V

REF

+ 1.6 V. Output current is set proportional to the POWER LEVEL

during calibration as follows:

MONITOR

POWER LEVEL

REF

GAIN

CAL

TTL/CMOS compatible, feedback loop T/H control signal. Logic LOW enables calibration mode, and
the feedback loop T/H goes into track mode 13 ns after (the aperture delay) PULSE goes logic HIGH
(there is no aperture delay if PULSE goes high before CAL transitions to a LOW level). Logic HIGH dis-
ables the T/H and immediately places it in hold mode. PULSE should be held HIGH while calibrating.
Floats logic HIGH.

HOLD

External hold capacitor for the bias loop T/H. Approximate droop in the output current while CAL is

logic HIGH is:

OUT

HOLD

Bandwidth of the loop is:

(550

) C

HOLD

PULSE

TTL/CMOS compatible, current control signal. Logic HIGH supplies I

OUT

to the laser diode. Logic

LOW turns I

OUT

off. Floats logic HIGH.

PULSE 2

TTL/CMOS compatible, current control signal. Logic LOW supplies I

OUT

to the laser diode. Logic

HIGH turns I

OUT

off. Floats logic HIGH.

SENSE IN

Analog current input, I

MONITOR

, from PIN photo detector diode. SENSE IN should be connected to the

anode of the PIN diode, with the PIN cathode connected to +V

or another positive voltage. Voltage at

SENSE IN varies slightly with temperature and current, but is typically 1.0 V.

GAIN

External connection for the feedback network of the transimpedance amplifier. External feedback network,
R

GAIN

and C

GAIN

, should be connected between GAIN and POWER MONITOR. See text for choosing

values.

POWER MONITOR

Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from
photo diode, I

MONITOR

DISABLE

TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH
disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to V

REF

(minimizes the output current when the device is re-enabled). DISABLE floats logic HIGH.

REF

Analog Voltage output, internal bandgap voltage reference, ~1.8 V, provided to user for power level offset.

Power Supply, nominally +5 V. All +V

connections should be tied together externally.

GROUND

Ground reference. All GROUND connections should be tied together externally.

LEVEL SHIFT IN

Analog input to the on board level shift circuit. Input Range 0.1 V 1.6 V.

LEVEL SHIFT OUT

Voltage output from on board level shift circuit. Connect to POWER LEVEL externally to use the on
board level shift circuit. Output voltage is V

LEVEL SHIFT OUT

= V

LEVEL SHIFT IN

REF

PIN ASSIGNMENTS

AD9661AKR

(Not to Scale)

PULSE2

DNC

REF

LEVEL SHIFT IN

GAIN

SENSE INPUT

GROUND

HOLD

POWER LEVEL

DISABLE

GROUND

OUTPUT

GROUND

OUTPUT

GROUND

OUTPUT

GROUND

OUTPUT

GROUND

CAL

PULSE1

POWER MONITOR

LEVEL SHIFT OUT

AD9661A

REV. 0

THEORY OF OPERATION

The AD9661A combines a very fast output current switch with
an onboard analog light power control loop to provide the user
with a complete laser diode driver solution. The block diagram
illustrates the key internal functions. The control loop of the
AD9661A adjusts the output current level, I

OUT

, so that the

photo diode feedback current, I

MONITOR

, into SENSE IN is pro-

portional to the analog input voltage at POWER LEVEL. Since
the monitor current is proportional to the laser diode light
power, the loop effectively controls laser power to a level pro-
portional to the analog input. The control loop should be peri-
odically calibrated (see Choosing C

HOLD

The disable circuit turns off I

OUT

and returns the hold capacitor

voltages to their minimum levels (minimum output current)
when DISABLE = logic HIGH. It is used during initial power
up of the AD9661A or during time periods where the laser is
inactive. When the AD9661A is re-enabled the control loop
must be recalibrated.

Normal operation of the AD9661A involves the following (in
order, see Figure 1):

1. The AD9661A is enabled (DISABLE = logic LOW).

2. The input voltage (POWER LEVEL) is driven to the

appropriate level to set the calibrated laser diode output
power level.

3. The feedback loop is closed for calibration (

CAL = logic

LOW, and PULSE = logic HIGH), and then opened (

CAL

= logic HIGH).

4. While the feedback loop is open, the laser is pulsed on and

off by PULSE.

5. The feedback loop is periodically recalibrated as needed.

6. The AD9661A is disabled when the laser will not be pulsed

for an indefinite period of time.

Control Loop Transfer Function

The relationship between I

MONITOR

and V

POWER LEVEL

MONITOR

POWER LEVEL

REF

GAIN

)

once the loop is calibrated. When the loop is open (

CAL = logic

HIGH), the output current, I

OUT

, is proportional to the held

voltage at HOLD; the external hold capacitor on this pin
determines the droop error in the output current between
calibrations.

The sections below discuss choosing the external components in
the feedback loop for a particular application.

Choosing R

GAIN

The gain resistor, R

GAIN

, allows the user to match the feedback

loop's transfer function to the laser diode/photo diode
combination.

The user should define the maximum laser diode output power
for the intended application, P

LD MAX

, and the corresponding

photo diode monitor current, I

MONITOR MAX

. A typical laser

diode transfer function is illustrated below. R

GAIN

should be

chosen as:

GAIN

1.6V

MONITOR MAX

120

100

OPTICAL OUTPUT mW

CONSTANT WRITE POWER

C CASE

CASE

C CASE

OUT

FORWARD CURRENT mA

Figure 2. Laser Diode Current-to-Optical Power Curve

POWER-UP

OR LASER

NOT IN USE

CAL

TIME

RECALIBRATE

LASER POWER

MODULATED

DISABLE

CAL

PULSE

LASER

OUTPUT POWER

CALIBRATED LEVEL

HOLD TIME

Figure 1. Normal Operating Mode

AD9661A

REV. 0

To choose a value, the user will need to determine the amount
of time the loop will be in hold mode, t

HOLD

, the maximum

change in laser output power the application can tolerate, and
the laser efficiency (defined as the change in laser output power
to the change in laser diode current). As an example, if an ap-
plication requires 5 mW of laser power

5%, and the laser diode

efficiency is 0.25 mW/mA, then

MAX

5 mW

(5%)/ 0.25

1.0 mA

If the same application had a hold time requirement of 250

then the minimum value of the hold capacitor would be:

HOLD

250

1.0 mA

4.5 nF

When determining the calibration time, the T/H and the exter-
nal hold capacitor can be modeled using the simple RC circuit
illustrated below.

HOLD

AD9661A

T/H

TZA

POWER LEVEL

POWER MONITOR

HOLD

EXTERNAL HOLD
CAPACITOR

Figure 3. Circuitry Model for Determining Calibration Times

Using this model, the voltage at the hold capacitor is

CHOLD

) 1 e

where t = 0 is when the calibration begins (

CAL goes logic

LOW), V

t = 0

is the voltage on the hold cap at t = 0, V

t =

is the

steady state voltage at the hold cap with the loop closed, and

= R

CHOLD

is the time constant. With this model the error in

CHOLD

for a finite calibration time, as compared to V

t =

, can

be estimated from the following table and chart:

Table II.

CALIBRATION

% Final Value

Error %

99.9

0.09

99.7

0.25

99.2

0.79

98.1

1.83

95.0

4.97

86.5

13.5

63.2

36.8

The laser diode's output power will then vary from 0 to P

LD MAX

for an input range of V

REF

to V

REF

+1.6 V @ the POWER

LEVEL input.

Minimum specifications for I

MONITOR MAX

should be used when

choosing R

GAIN

. Users are cautioned that laser diode/photo

diode combinations that produce monitor currents that are less
than I

MONITOR MAX

in the equation above will produce higher la-

ser output power than predicted, which may damage the laser
diode. Such a condition is possible if R

GAIN

is calculated using

typical instead of minimum monitor current specifications. In
that case the input range to the AD9661A POWER LEVEL
input should be limited to avoid damaging laser diodes.

Another approach would be to use a potentiometer for R

GAIN

This allows users to optimize the value of R

GAIN

for each laser

diode/photo diode combination's monitor current. The draw-
back to this approach is that potentiometers' stray inductance
and capacitance may cause the transimpedance amplifier to
overshoot and degrade its settling, and the value of C

GAIN

may

not be optimized for the entire potentiometer's range.

GAIN

optimizes the response of the transimpedance amplifier

and should be chosen as from the table below. Choosing C

GAIN

larger than the recommended value will slow the response of the
amplifier. Lower values improve TZA bandwidth but may cause
the amplifier to oscillate.

Table I.

Recommended

GAIN

2.5 k

2 pF

1.5 k

3 pF

1 k

4 pF

500

8 pF

Choosing C

HOLD

Choosing values for the hold capacitor, C

HOLD

, is a tradeoff

between output current droop when the control loop is open,
and the time it takes to calibrate and recalibrate the laser power
when the loop is closed.

The amount of output current droop is determined by the value
of the hold capacitor and the leakage current at that node.
When the control loop is open (

CAL logic HIGH), the pin con-

nection for the hold capacitor (HOLD) is a high impedance in-
put. Leakage current will range from

200; this low current

minimizes the droop in the output power level. Assuming the
worst case current of

200 nA, the output current will change

as follows:

OUT

HOLD

AD9661A

REV. 0

TIME CONSTANTS 

100

% FINAL VALUE % of Volts

Figure 4. Calibration Time

Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9661A drives the
hold capacitor to

REF

. In this case, or in any case where the

output current is more than 10% out of calibration, R will range
from 300

to 550

for the model above; the higher value should

be used for calculating the worst case calibration time. Following
the example above, if C

HOLD

were chosen as 4.5 nF, then

= RC = 550

4.5 nF would be 2.48

s. For an initial

calibration error < 1%, the initial calibration time should be
> 5

= 12.36

Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660's T/H decreases as the hold voltage approaches its
final value.

Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (< 10%), the
resistance for the model above will be in the range of 75

140

. Again, the higher value should be used to estimate the

worst case time needed for recalibration.

Continuing with the example above, since the droop error dur-
ing hold time is < 5%, we meet the criteria for recalibration and

= RC = 140

4.5 nF = 0.64

s. To get a final error of 1%

after recalibration, the 5% droop must be corrected to within a
20% error (20%

5% = 1%). A 2

recalibration time of 1.2

is sufficient.

Continuous Recalibration

In applications where the hold capacitor is small (< 500 pF) and
the WRITE PULSE signals always have a pulse width > 25 ns,
the user may continuously calibrate the feedback loop. In such
an application, the

CAL signal should be held logic LOW, and

the PULSE signal will control loop calibration via the internal
AND gate. In such application, it is important to optimize the
layout for the TZA (POWER MONITOR, GAIN, R

GAIN

and

GAIN

Driving the Analog Inputs

The POWER LEVEL input of the AD9661A drives the track
and hold amplifier and allows the user to adjust the amount of
output current as described above. The input voltage range is
V

REF

to V

REF

+ 1.6 V, requiring the user to create an offset of

REF

for a ground based signal (see below for description of the

on board level shift circuit). The circuit below will perform the
level shift and scale the output of a DAC whose output is from
ground to a positive voltage. This solution is especially attrac-
tive because both the DAC and the op amp can run off a single
+5 V supply, and the op amp doesn't have to swing rail to rail.

DAC

OP191

+5V

REF

DAC

= V

POWER LEVEL

R2
R1

BIAS LEVEL

REF

AD9661A

Figure 5. Driving the Analog Inputs

Using the Level Shift Circuit

The AD9661A includes an on board level shift circuit to provide
the offset described above. The input, LEVEL SHIFT IN, has
an input range from 0.1 V to 1.6 V. The output, LEVEL
SHIFT OUT, has a range from V

REF

to V

REF

+1.6 V, and can

drive POWER MONITOR. The linearity of the level shift cir-
cuit is poor for inputs below 100 mV. Between 100 mV and
1.6 V it is about 7 bits accurate.

Layout Considerations

As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as
possible, and isolated from digital signals to avoid coupling in
noise. In particular, digital lines should be isolated from
OUTPUT, SENSE IN, POWER LEVEL, LEVEL SHIFT IN
POWER MONITOR, and HOLD traces. Digital signal paths
should also be kept short, and run lengths matched to avoid
propagation delay mismatch.

Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1

surface mount capacitors, placed as close as possible to the
AD9661A +V

connections, and the +V

connection to the laser

diode meet this requirement. Multilayer circuit boards allow
designers to lay out signal traces without interrupting the ground
plane, and provide low impedance power planes to further
reduce noise.

AD9661A

REV. 0

Minimizing the Impedance of the Output Current Path

Because of the very high current slew that the AD9661A is
capable of producing (120+ mA in 1.5 ns), the inductance of
the output current path to and from the laser diode is critical.
A good layout of the output current path will yield high quality
light pulses with rise times of about 1.5 ns and less than 5%
overshoot. A poor layout can result in significant overshoot and
ringing. The most important guideline for the layout is to mini-
mize the impedance (mostly inductance) of the output current
path to the laser.

It is important to recognize that the laser current path is a
closed loop. The figure illustrates the path that current travels:
(1) from the +V

connection at the anode of the laser to the

cathode (2) from the cathode to the output pins of the
AD9661A (3) through the output drive circuit of the
AD9661A, (4) through the return path (GROUND plane in the
illustration) (5) through the bypass capacitors back to the +V

connection of the laser diode. The inductance of this loop can
be minimized by placing the laser as close to the AD9661A as
possible to keep the loop short, and by placing the send and re-
turn paths on adjacent layers of the PC board to take advantage
of mutual coupling of the path inductances. This mutual cou-
pling effect is the most important factor in reducing inductance
in the current path.

The trace from the output pins of the AD9661A to the cathode
of the laser should be several millimeters wide and should be as
direct as possible. The return current will choose the path of
least resistance. If the return path is the GROUND plane, it
should have an unbroken path, under the output trace, from the
laser anode back to a the AD9661A. If the return path is not
the ground plane (such as on a two layer board, or on the +V

plane), it should still be on the board plane adjacent to the
plane of the output trace. If the current cannot return along a
path that follows the output trace, the inductance will be drasti-
cally increased and performance will be degraded.

GROUND PLANE

BYPASS CAPS

GROUND PIN

CONNECTIONS

OUTPUT PIN

CONNECTIONS

PIN ASSIGNMENTS

LASER DIODE CURRENT

PATH SEGMENTS (See Text)

MUTUAL COUPLING

REDUCES INDUCTANCE

AD9661A

PLANE

Figure 6. Laser Diode Current Loop

Optimizing the Feedback Layout

In applications where the dynamic performance of the analog
feedback loop is important, it is necessary to optimize the layout
of the gain resistor, R

GAIN

, as well as the monitor current path to

SENSE IN. Such applications include systems which recali-
brate the write loop on pulses as short as 25 ns, and closed-loop
applications.

The best possible TZA settling will be achieved by using a single
carbon surface mount resistor (usually 5% tolerance) for R

GAIN

and small surface mount capacitor for C

GAIN

. Because the

GAIN pin (Pin 5) is essentially connected to the inverting input
of the TZA, it is very sensitive to stray capacitance. R

GAIN

should be placed between Pin 5 and Pin 6, as close as possible
to Pin 5. Small traces should be used, and the ground and +V

planes adjacent to the trace should be removed to further mini-
mize stray capacitance.

The trace from SENSE IN to the anode of the PIN photodetec-
tor should be thin and routed away from the laser cathode trace.

Example Calculations

The example below (in addition to the one included in the sec-
tions above) should guide users in choosing R

GAIN

, C

GAIN

, the

hold capacitor values, and worst case calibration times.

System Requirements:

Laser power: 4 mW

Hold Time: 0.5 ms

Laser diode/photo diode characteristics:

Laser efficiency 0.3 mW/mA

Monitor current : 0.2 mA/mW

From the laser power requirements and efficiency we can
estimate:

OUT MAX

4 mW

(2.0%)/ 0.3

266.6

AD9661A

REV. 0

AD9661A EVALUATION BOARD

The AD9661A Evaluation Board is comprised of two printed
circuit boards. The Laser Diode Driver (LDD) Resource Board
is both a digital pattern generator and an analog reference gen-
erator (see LDD Resource Board Block Diagram.) The board is
controlled by an IBM compatible personal computer through a
standard printer cable. The resource board interfaces to the
AD9661A DUT board, which contains the AD9661A, a level
shift circuit for the analog input, and a socket for an N type

laser diode. A dummy load circuit for the laser diode is in-
cluded for evaluation. Power for all the boards is provided
through the banana jacks on the AD9661A DUT board.
These should be connected to a linear, +5 V power supply.
Schematics for the LDD Resource Board, AD9661A DUT,
and Dummy Load are included, along with a bill of mate-
rial and layout information. Please contact Applications for
additional information.

Figure 10. LDD Resource Board Block Diagram

AD9661A

DUMMY LOAD CIRCUIT/

LASER DIODE SOCKET

OPTIONAL

LEVEL SHIFT

CIRCUIT

AD9661A

EVALUATION BOARD

INPUT SMB CONNECTORS
FOR DIGITAL CONTROLS

20-PIN HEADER
FOR ANALOG
CONTROLS

Figure 11. Evaluation Board Block Diagram

40MHz

CLOCK

OSCILLATOR

32K x 16

MEMORY

OUTPUT

SMB

CONNECTORS

ADDRESS
COUNTER

AND

RESOURCE

CONTROLLER

READBACK

LATCH

DIGITAL PATTERN GENERATOR

CENTRONICS

CONNECTOR

STANDARD PARALLEL

PRINTER CABLE

IBM-COMPATIBLE

WITH WINDOWS

PARALLEL

PRINTER PORT

02.55V

ANALOG REFERENCE

LASER DIODE DRIVER RESOURCE BOARD

J5
J7

J6
J2

CAL

(JCALB)

DISABLE (JDIS)

PULSE2

(JPULB)

UNUSED
TRIGGER

PULSE1 (JPUL)

20-PIN

HEADER

AD9661A
LEVEL SHIFT IN

+5V POWER SUPPLY

GROUND

1720

110

EXTERNAL LEVEL SHIFT CIRCUIT

PULSE
WIDTH

MODULATOR

(AD9560)

OUTPUT
BUFFER

INTERFACE TO

AD9661A

EVALUATION

BOARD

DAC 1

DAC 2

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD9661A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD9661A