AD9237 12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter Data Sheet (Rev. 0)
12-Bit, 20 MSPS/40 MSPS/65 MSPS
3 V Low Power A/D Converter
AD9237
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Ultralow power
85 mW at 20 MSPS
135 mW at 40 MSPS
190 mW at 65 MSPS
SNR = 66 dBc to Nyquist at 65 MSPS
SFDR = 80 dBc to Nyquist at 65 MSPS
DNL = 0.7 LSB
Differential input with 500 MHz bandwidth
Flexible analog input: 1 V p-p to 4 V p-p range
Offset binary, twos complement, or gray code data formats
Output enable pin
2-step power-down
Full power-down and sleep mode
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound and medical imaging
Battery-powered instruments
Hand-held scope meters
Low cost digital oscilloscopes
Low power digital still cameras and copiers
Low power communications
FUNCTIONAL BLOCK DIAGRAM
SHA
VIN+
VIN
DRVDD
CLK
PDWN
MODE
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
DGND
OTR
D11
D0
AVDD
MDAC1
CORRECTION LOGIC
OUTPUT BUFFERS
REF
SELECT
AGND
0.5V
VREF
SENSE
AD9237
05455-001
REFT
REFB
MODE2
A/D
A/D
4
15
12
3
OE
10-STAGE
1 1/2-BIT
PIPELINE
Figure 1.
GENERAL DESCRIPTION
The AD9237 is a family of monolithic, single 3 V supply, 12-bit,
20 MSPS/40 MSPS/65 MSPS analog-to-digital converters
(ADC). This family features a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9237 uses a
multistage differential pipelined architecture with output error
correction logic to provide 12-bit accuracy at 20 MSPS/
40 MSPS/65 MSPS data rates and guarantees no missing codes
over the full operating temperature range.
With significant power savings over previously available ADCs,
the AD9237 is suitable for applications in imaging and medical
ultrasound.
Fabricated on an advanced CMOS process, the AD9237 is
available in a 32-lead LFCSP and is specified over the industrial
temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
1.
Evaluation boards available for all speed grades.
2.
Operating at 65 MSPS, the AD9237 consumes a low 190 mW
at 65 MSPS, 135 mW at 40 MSPS, and 85 mW at 20 MSPS.
3.
Power scaling reduces the operating power further when
running at lower speeds.
4.
The AD9237 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
5.
The patented SHA input maintains excellent performance
for input frequencies beyond Nyquist and can be configured
for single-ended or differential operation.
6.
The AD9237 is optimized for selectable and flexible input
ranges from 1 V p-p to 4 V p-p.
7.
An output enable pin allows for multiplexing of the outputs.
8.
Two-step power-down supports a standby mode in addition
to a power-down mode.
9.
The OTR output bit indicates when the signal is beyond the
selected input range.
10.
The clock duty cycle stabilizer (DCS) maintains converter
performance over a wide range of clock pulse widths.
AD9237
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 4
Switching Specifications .............................................................. 5
Timing Diagram ............................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .......................................................................................9
Equivalent Circuits......................................................................... 10
Typical Performance Characteristics ........................................... 11
Applying the AD9237 .................................................................... 16
Theory of Operation .................................................................. 16
Analog Input and Reference Overview ................................... 16
Voltage Reference ....................................................................... 18
Clock Input Considerations...................................................... 19
Power Dissipation, Power Scaling, and Standby Mode......... 19
Digital Outputs ........................................................................... 21
LFCSP Evaluation Board........................................................... 22
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
10/05--Revision 0: Initial Version
AD9237
Rev. 0 | Page 3 of 28
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, -0.5 dBFS input, 1.0 V internal reference, T
MIN
to T
MAX
,
unless otherwise noted.
Table 1.
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
12
12
12
Bits
ACCURACY
No Missing Codes Guaranteed
12
12
12
Bits
Offset
Error
1.30 1.95
1.30 1.95
1.30 1.95 %
FSR
Gain Error
1
0.70 2.10
0.75 2.10
1.05 2.25 %
FSR
Differential Nonlinearity (DNL)
2
0.70 0.95
0.70 0.95 -1.00 0.70 +1.25 LSB
Integral Nonlinearity (INL)
2
0.90 1.35
0.90 1.35
0.90 2.00 LSB
TEMPERATURE
DRIFT
Offset
Error
2
2
2
ppm/C
Gain Error
1
12
12
12
ppm/C
INTERNAL
VOLTAGE
REFERENCE
Output
Voltage
Error
(1
V
Mode)
5 25 5 25
5 25 mV
Load Regulation @ 1.0 mA
0.8
0.8
0.8
mV
Output
Voltage
Error
(0.5
V
Mode)
2.5
2.5
2.5
mV
Load Regulation @ 0.5 mA
0.1
0.1
0.1
mV
Reference
Input
Resistance
7
7
7
k
INPUT
REFERRED
NOISE
VREF
=
0.5
V
1.35
1.35
1.35
LSB
rms
VREF
=
1.0
V
0.70
0.70
0.70
LSB
rms
ANALOG
INPUT
Input
Span
VREF = 0.5 V; MODE2 = 0 V
1
1
1
V p-p
VREF = 1.0 V; MODE2 = 0 V
2
2
2
V p-p
VREF = 0.5 V; MODE2 = AVDD
2
2
2
V p-p
VREF = 1.0 V; MODE2 = AVDD
4
4
4
V p-p
Input Capacitance
3
7
7
7
pF
POWER
SUPPLIES
Supply
Voltages
AVDD
2.7
3.0 3.6 2.7
3.0 3.6 2.7 3.0 3.6 V
DRVDD
2.25
2.5 3.6 2.25
2.5 3.6 2.25
2.5 3.6 V
Supply Current
IAVDD
2
30.5
45.5
64.5
mA
IDRVDD
2
3.0
4.5
5.5
mA
PSRR
0.01
0.01
0.01
%
FSR
POWER
CONSUMPTION
DC Input
4
85
135
190
mW
Sine Wave Input
2
100 120 150 180
210 270 mW
Power-Down
Mode
1
1
1
mW
Standby
Power
20
20
20
mW
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
AD9237
Rev. 0 | Page 4 of 28
DIGITAL SPECIFICATIONS
Table 2.
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
LOGIC INPUTS
High
Level
Input
Voltage
2.0
2.0
2.0
V
Low
Level
Input
Voltage
0.8
0.8
0.8
V
High Level Input Current
10
+10
10
+10
10
+10
A
Low Level Input Current
10
+10
10
+10
10
+10
A
Input
Capacitance
2 2 2 pF
LOGIC OUTPUTS
1
DRVDD
=
3.3
V
High-Level Output Voltage (IOH = 50 A)
3.29
3.29
3.29
V
High-Level Output Voltage (IOH = 0.5 mA)
3.25
3.25
3.25
V
Low-Level Output Voltage (IOL = 1.6 mA)
0.2
0.2
0.2
V
Low-Level Output Voltage (IOL = 50 A)
0.05
0.05
0.05
V
DRVDD
=
2.5
V
High-Level Output Voltage (IOH = 50 A)
2.49
2.49
2.49
V
High-Level Output Voltage (IOH = 0.5 mA)
2.45
2.45
2.45
V
Low-Level Output Voltage (IOL = 1.6 mA)
0.2
0.2
0.2
V
Low-Level Output Voltage (IOL = 50 A)
0.05
0.05
0.05
V
1
Output voltage levels measured with 5 pF load on each output.
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, A
IN
= 0.5 dBFS, 1.0 V internal reference, T
MIN
to T
MAX
,
unless otherwise noted.
Table 3.
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter
Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE
RATIO
(SNR)
f
INPUT
= 2.4 MHz
66.8
66.5
66.5
dBc
f
INPUT
= 9.7 MHz
65.6
66.6
dBc
f
INPUT
= 19.6 MHz
65.3
66.6
dBc
f
INPUT
= 34.2 MHz
64.0
66.1
dBc
f
INPUT
= 70 MHz
66.0
66.3
65.9
dBc
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
f
INPUT
= 2.4 MHz
66.7
66.4
66.3
dBc
f
INPUT
= 9.7 MHz
65.1
66.5
dBc
f
INPUT
= 19.6 MHz
64.4
66.4
dBc
f
INPUT
= 34.2 MHz
63.5
65.8
dBc
f
INPUT
= 70 MHz
65.6
65.8
65.2
dBc
EFFECTIVE NUMBER OF BITS (ENOB)
f
INPUT
= 9.7 MHz
10.8
Bits
f
INPUT
=
19.6
MHz
10.7
Bits
f
INPUT
= 34.2 MHz
10.6
Bits
AD9237
Rev. 0 | Page 5 of 28
AD9237BCP-20 AD9237BCP-40 AD9237BCP-65
Parameter
Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS-FREE
DYNAMIC
RANGE
(SFDR)
f
INPUT
= 2.4 MHz
88.0
83.5
85.5
dBc
f
INPUT
= 9.7 MHz
72.4
87.5
dBc
f
INPUT
= 19.6 MHz
72.2
82.4
dBc
f
INPUT
= 34.2 MHz
69.4
80.1
dBc
f
INPUT
= 70 MHz
80.5
77.9
74.9
dBc
WORST HARMONIC (SECOND OR THIRD)
f
INPUT
= 2.4 MHz
-88.0
-83.5
-85.5
dBc
f
INPUT
= 9.7 MHz
-72.4
-87.5
dBc
f
INPUT
= 19.6 MHz
-72.2
-82.4
dBc
f
INPUT
= 34.2 MHz
-69.4
-80.1
dBc
f
INPUT
= 70 MHz
-80.5
-77.9
-74.9
dBc
WORST
OTHER
SPUR
f
INPUT
= 2.4 MHz
-90
-90
-90
dBc
f
INPUT
= 9.7 MHz
-73.4
-90
dBc
f
INPUT
= 19.6 MHz
-73.1
-90
dBc
f
INPUT
= 34.2 MHz
-72.0
-90
dBc
f
INPUT
= 70 MHz
-90
-90
-90
dBc
SWITCHING SPECIFICATIONS
Table 4.
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min Typ Max Min Typ Max Min Typ Max Unit
CLK
INPUT
PARAMETERS
Maximum
Conversion
Rate
20
40
65
MSPS
Minimum
Conversion
Rate
1 1 1 MSPS
CLK
Period
50.0
25.0
15.4
ns
CLK Pulse Width High
1
15.0
8.8
6.2
ns
CLK Pulse Width Low
1
15.0
8.8
6.2
ns
DATA
OUTPUT
PARAMETERS
Output Delay (t
PD
)
2
3.5
3.5
3.5
ns
Pipeline
Delay
(Latency)
8 8 8 Cycles
Output
Enable
Time
6 6 6 ns
Output
Disable
Time
3 3 3 ns
Aperture Delay (t
A
)
1.0
1.0
1.0
ns
Aperture Uncertainty (Jitter, t
J
)
0.5
0.5
0.5
ps
rms
Wake-Up Time (Sleep Mode)
3
3.0
3.0
3.0
ms
Wake-Up Time (Standby Mode)
3
3.0
3.0
3.0
s
OUT-OF-RANGE
RECOVERY
TIME
1 1 2 Cycles
1
With duty cycle stabilizer enabled.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB.
AD9237
Rev. 0 | Page 6 of 28
TIMING DIAGRAM
N9
N8
N7
N6
N5
N4
N3
N2
N1
N
ANALOG
INPUT
CLK
DATA
OUT
N1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N10
t
PD
t
A
05455-
002
Figure 2. Timing Diagram
AD9237
Rev. 0 | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Pin Name
With
Respect to
Min Max
Unit
ELECTRICAL
AVDD AGND
0.3
+3.9 V
DRVDD DGND 0.3
+3.9
V
AGND DGND
0.3
+0.3 V
AVDD DRVDD
3.9
+3.9 V
Digital
Outputs, OE
DGND
0.3
DRVDD + 0.3
V
CLK, MODE,
MODE2
AGND
-0.3
AVDD + 0.3
V
VIN+, VIN
AGND
0.3
AVDD + 0.3
V
VREF
AGND
0.3
AVDD + 0.3
V
SENSE
AGND
0.3
AVDD + 0.3
V
REFB, REFT
AGND
0.3
AVDD + 0.3
V
PDWN
AGND
0.3
AVDD + 0.3
V
ENVIRONMENTAL
1
Operating Temperature
40
+85
C
Junction Temperature
150
C
Lead Temperature (10 sec)
300
C
Storage Temperature
65
+150
C
1
Typical thermal impedances (32-lead LFCSP),
JA
= 32.5C/W,
JC
= 32.71C/W.
These measurements were taken on a 4-layer board in still air, in accordance
with EIA/JESD51-1.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings are limiting values to be applied
individually and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for
an extended period may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9237
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05455-003
DNC = DO NOT CONNECT
PIN 1
INDICATOR
1
MODE2
2
CLK
3
OE
4
PDWN
5
GC
6
DNC
7
D0 (LSB)
8
D1
24 VREF
23 SENSE
22 MODE
21 OTR
20 D11 (MSB)
19 D10
18 D9
17 D8
9
D
2
1
0
D
3
1
1
D
4
1
2
D
5
1
3
D
6
1
4
D
7
1
5
D
G
N
D
1
6
D
R
V
D
D
3
2
A
V
D
D
3
1
A
G
N
D
3
0
V
I
N
2
9
V
I
N
+
2
8
A
G
N
D
2
7
A
V
D
D
2
6
R
E
F
T
2
5
R
E
F
B
TOP VIEW
(Not to Scale)
AD9237
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
Description
1
MODE2
SHA Gain Select and Power Scaling Control (see Table 8).
2
CLK
Clock Input Pin.
3
OE
Output Enable Pin (Active Low).
4
PDWN
Power-Down Function Selection (see Table 9).
5
GC
Gray Code Control (Active High).
6
DNC
Do Not Connect.
7 to 14, 17 to 20
D0 (LSB) to D11 (MSB)
Data Output Bits.
15
DGND
Digital Output Ground.
16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 F capacitor.
Recommended decoupling is 0.1 F in parallel with 10 F.
21 OTR
Out-of-Range
Indicator.
22
MODE
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10).
23
SENSE
Reference Mode Selection (see Table 7).
24
VREF
Voltage Reference Input/Output (see Table 7).
25
REFB
Differential Reference (-). Must be decoupled to REFT with a minimum 10 F capacitor.
26
REFT
Differential Reference (+).
27, 32
AVDD
Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 F capacitor.
Recommended decoupling is 0.1 F in parallel with 10 F.
28, 31
AGND
Analog Ground.
29
VIN+
Analog Input Pin (+).
30
VIN-
Analog Input Pin (-).
AD9237
Rev. 0 | Page 9 of 28
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (t
A
)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Jitter (t
J
)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used
as negative full scale occurs LSB before the first code
transition. Positive full scale is defined as a level 1 LSBs
beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
LSB below VIN+ = VIN. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value
LSB above negative full scale. The last transition should occur
at an analog value 1 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25C) value to the value
at T
MIN
or T
MAX
.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum
limit.
Total Harmonic Distortion (THD)
1
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Signal-To-Noise and Distortion (SINAD)
1
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
The effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD using the following formula:
ENOB = (SINAD
dBFS
- 1.76)/6.02
Signal-to-Noise Ratio (SNR)
1
The ratio of the rms signal to the rms value of the sum of all
other spectral components below the Nyquist frequency,
excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
1
SFDR is the difference in dB between the rms amplitude of the
input signal and the rms value of the peak spurious signal. The
peak spurious signal may not be an harmonic.
Two-Tone SFDR
1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (t
PD
)
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes the ADC to reacquire the analog input after a
transition from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
AD9237
Rev. 0 | Page 10 of 28
EQUIVALENT CIRCUITS
05455-
004
AVDD
VIN+, VIN
Figure 4. Equivalent Analog Input Circuit
05455-005
MODE,
MODE2,
GC, OE
375
70k
Figure 5. Equivalent MODE, MODE2, GC, OE Input Circuit
D11D0,
OTR
DRVDD
05455-006
Figure 6. Equivalent Digital Output Circuit
05455-007
CLK,
PDWN
375
Figure 7. Equivalent CLK, PDWN Input Circuit
AD9237
Rev. 0 | Page 11 of 28
6
8
4
2
05455-008
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate with DCS disabled, T
A
= 25C, 2 V p-p differential input, A
IN
= 0.5 dBFS,
VREF = 1.0 V internal, FFT length 16 K, unless otherwise noted.
FREQUENCY (MHz)
AMP
LITUDE
(dBFS
)
0
20
40
60
80
100
120
0
10
SNR = 66.9dBc
SFDR = 87.0dBc
Figure 8. AD9237-20 10 MHz FFT
FREQUENCY (MHz)
AMP
LITUDE
(dBFS
)
0
20
40
60
80
100
120
0
20
CLOCK FREQUENCY (MSPS)
S
NR/S
F
DR (dBc
)
90
85
80
75
70
65
60
10.0
20.0
17.5
15.0
12.5
05455-011
SNR
SFDR
12
16
8
4
18
10
14
6
2
05455-009
SNR = 66.8dBc
SFDR = 83.1dBc
Figure 9. AD9237-40 20 MHz FFT
FREQUENCY (MHz)
AMP
LITUDE
(dBFS
)
0
20
40
60
80
100
120
05455-010
SNR = 66.0dBc
SFDR = 78.6dBc
0
30 32.5
25
20
15
10
5
Figure 10. AD9237-65 70 MHz FFT
Figure 11. AD9237-20 SNR/SFDR vs. Clock Frequency with f
IN
= 10 MHz
CLOCK FREQUENCY (MSPS)
S
NR/S
F
DR (dBc
)
90
85
80
75
SFDR
SNR
70
65
20
40
35
30
25
05455-012
Figure 12. AD9237-40 SNR/SFDR vs. Clock Frequency with f
IN
= 20 MHz
CLOCK FREQUENCY (MSPS)
S
NR/S
F
DR (dBc
)
90
85
80
75
70
65
60
40
65
55
60
50
45
05455-013
SNR
SFDR
Figure 13. AD9237-65 SNR/SFDR vs. Clock Frequency with f
IN
= 35 MHz
AD9237
Rev. 0 | Page 12 of 28
FREQUENCY (MHz)
AMP
L
ITUDE
(dBc
)
0
120
100
80
60
40
20
SNR = 65.6dBc
SFDR = 67.1dBc
05455-014
0
30 32.5
25
20
15
10
5
Figure 14. AD9237-65 100 MHz FFT
INPUT AMPLITUDE (dBFS)
S
NR/S
FDR (dBc
a
nd dBFS
)
90
80
70
60
50
40
30
30
0
5
10
15
20
25
05455-017
SFDR dBFS 4V p-p
SFDR dBc 4V p-p
SNR dBFS 2V p-p
SNR dBFS 4V p-p
SNR dBc 2V p-p
SNR dBc 4V p-p
SFDR dBFS 2V p-p
SFDR dBc 2V p-p
Figure 15. AD9237-65 SNR/SFDR vs. Input Amplitude with f
IN
= 35 MHz
INPUT AMPLITUDE (dBFS)
SNR/SFDR (dBc and dBFS)
100
90
80
70
60
50
40
30
30
0
5
10
15
20
25
05455-019
SFDR dBFS 2V p-p
SNR dBc 2V p-p
SNR dBc 1V p-p
SFDR dBFS 1V p-p
SFDR dBc 2V p-p
SFDR dBc 1V p-p
SNR dBFS 2V p-p
SNR dBFS 1V p-p
Figure 16. AD9237-40 SNR/SFDR vs. Input Amplitude with f
IN
= 20 MHz
DUTY CYCLE (%)
SN
R
/SFD
R
(
d
B
c
)
90
50
55
60
65
70
75
80
85
30
70
65
60
55
50
45
40
35
05455-030
SFDR DCS
ENABLED
SFDR DCS
DISABLED
SNR DCS ENABLED
SNR DCS DISABLED
Figure 17. SNR/SFDR vs. Clock Duty Cycle
INPUT AMPLITUDE (dBFS)
S
NR/S
FDR (dBc
a
nd dBFS
)
90
80
70
60
50
40
30
30
0
5
10
15
20
25
05455-018
SFDR dBFS 2V p-p
SNR dBFS 2V p-p
SNR dBFS 1V p-p
SNR dBc 2V p-p
SNR dBc 1V p-p
SFDR dBc 2V p-p
SFDR dBc 1V p-p
SFDR dBFS 1V p-p
Figure 18. AD9237-65 SNR/SFDR vs. Input Amplitude with f
IN
= 35 MHz
INPUT AMPLITUDE (dBFS)
SNR/SFDR (dBc and dBFS)
100
90
80
70
60
50
40
30
30
0
5
10
15
20
25
05455-020
SFDR dBFS 2V p-p
SNR dBc 2V p-p
SNR dBc 1V p-p
SFDR dBFS 1V p-p
SFDR dBc 2V p-p
SFDR dBc 1V p-p
SNR dBFS 2V p-p
SNR dBFS 1V p-p
Figure 19. AD9237-20 SNR/SFDR vs. Input Amplitude with f
IN
= 10 MHz
AD9237
Rev. 0 | Page 13 of 28
FREQUENCY (MHz)
AMP
L
ITUDE
(dBc
)
0
20
40
60
80
100
120
0
30 32.5
25
20
15
10
5
05455-095
SNR = 67.0dBFS
SFDR = 87.8dBFS
Figure 20. AD9237-65 Two-Tone FFT, f
IN1
= 45 MHz, f
IN2
= 46 MHz
FREQUENCY (MHz)
AMP
L
ITUDE
(dBc
)
0
20
40
60
80
100
120
0
20
15
10
5
05455-021
SNR = 67.2dBFS
SFDR = 88.3dBFS
25
20
15
10
5
05455-094
Figure 21. AD9237-40 Two-Tone FFT
f
IN1
= 45 MHz, f
IN2
= 46 MHz
FREQUENCY (MHz)
AMP
LITUDE
(dBFS
)
0
20
40
60
80
100
120
0
30
SNR = 66.9dBFS
SFDR = 84.1dBFS
Figure 22. AD9237-65 Two-Tone FFT, f
IN1
= 69 MHz, f
IN2
= 70 MHz
SFDR dBFS
SFDR dBc
SNR dBc
INPUT AMPLITUDE (AIN)
SNR/SFDR (dBc and dBFS)
100
30
40
50
60
70
80
90
30
10
6.5
15
20
25
05455-024
SNR dBFS
Figure 23. AD9237-65 Two-Tone SNR/SFDR , vs. Analog Input with
f
IN1
= 45 MHz, f
IN2
= 46 MHz
SFDR dBFS
SFDR dBc
SNR dBc
INPUT AMPLITUDE (AIN)
S
NR/S
FDR (dBc
a
nd dBFS
)
100
30
40
50
60
70
80
90
30
10
6.5
15
20
25
05455-025
SNR dBFS
Figure 24. AD9237-40 Two-Tone SNR/SFDR , vs. Analog Input with
f
IN1
= 45 MHz, f
IN2
= 46 MHz
SFDR dBFS
SFDR dBc
SNR dBc
INPUT AMPLITUDE (AIN)
SNR/SFDR (dBc and dBFS)
100
30
40
50
60
70
80
90
30
10
6.5
15
20
25
05455-098
SNR dBFS
Figure 25. AD9237-65 Two-Tone SNR/SFDR vs. Analog Input with
f
IN1
= 69 MHz, f
IN2
= 70 MHz
AD9237
Rev. 0 | Page 14 of 28
15
10
5
05455-026
FREQUENCY (MHz)
AMP
L
ITUDE
(dBc
)
0
20
40
60
80
100
120
0
20
SNR = 67.1dBFS
SFDR = 87.3dBFS
SFDR dBFS
SFDR dBc
SNR dBc
INPUT AMPLITUDE (AIN)
SNR/SFDR (dBc and dBFS)
100
30
40
50
60
70
80
90
30
10
6.5
15
20
25
05455-097
SNR dBFS
Figure 26. AD9237-40 Two-Tone FFT
f
IN1
= 69 MHz, f
IN2
= 70 MHz
INPUT FREQUENCY (MHz)
S
N
R/S
FDR (dBc
)
90
85
80
SFDR
SNR
75
70
60
65
55
0
125
100
75
50
25
05455-015
Figure 27. AD9237-65 SNR/SFDR vs. Input Frequency
CODE
INL (
L
SB)
1.00
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
0
4096
3584
3072
2560
2048
1536
1024
512
05455-032
Figure 28. Typical INL
Figure 29. AD9237-40 Two-Tone SNR/SFDR vs. Analog Input with
f
IN1
= 69 MHz, f
IN2
= 70 MHz
INPUT FREQUENCY (MHz)
S
N
R/S
FDR (dBc
)
90
55
60
65
70
75
80
85
0
125
100
75
50
25
05455-016
SFDR
SNR
Figure 30. AD9237-40 SNR/SFDR vs. Input Frequency
CODE
DNL (LS
B
)
1.00
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
0
4096
3584
3072
2560
2048
1536
1024
512
05455-035
Figure 31. Typical DNL
AD9237
Rev. 0 | Page 15 of 28
CLOCK FREQUENCY (MSPS)
S
I
NAD (dBc
)
ENOB (
B
it
s)
67.5
67.0
66.5
66.0
65.5
65.0
10.83
10.75
10.67
10.59
10.50
10
20
70
60
50
40
30
05455-062
AD9237-40
AD9237-65
AD9237-20
Figure 32. AD9237 SINAD/ENOB vs. Clock Frequency with f
IN
= Nyquist
TEMPERATURE (C)
SN
R
/SFD
R
(
d
B
c
)
90
SNR
SFDR
85
80
75
70
65
60
40
20
85
80
60
40
20
0
05455-063
Figure 33. AD9237-65 SNR/SFDR vs. Temperature with f
IN
= 32.5MHz
AD9237
Rev. 0 | Page 16 of 28
APPLYING THE AD9237
THEORY OF OPERATION
The AD9237 uses a calibrated, 11-stage pipeline architecture
with a patented input SHA implemented. Each stage of the
pipeline, excluding the last, consists of a low resolution flash
ADC connected to a switched capacitor digital-to-analog
converter (DAC) and an interstage residue amplifier (MDAC).
The MDAC magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the
pipeline. One bit of redundancy is used in each stage to facilitate
digital correction of flash errors. The last stage consists of a
flash ADC.
The pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on preceding
samples. While the converter captures a new input sample every
clock cycle, it takes eight clock cycles for the conversion to be
fully processed and to appear at the output, as shown in Figure 2.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of
the output voltage swing. During power-down and stand-by
operation, the output buffers go into a high impedance state.
The ADC samples the analog input on the rising edge of
the clock. System disturbances just prior to, or immediately
following, the rising edge of the clock and/or excessive clock
jitter can cause the SHA to acquire the wrong input value and
should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9237 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The SHA input can support a wide common-mode range
and maintain excellent performance, as shown in Figure 34.
An input common-mode voltage of midsupply minimizes
signal-dependant errors and provides optimum performance.
Figure 35 shows the clock signal alternately switching the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source.
INPUT COMMON-MODE LEVEL (V)
S
NR/S
F
DR (dBc
)
90
80
70
60
50
40
30
0
3.0
2.5
2.0
1.5
1.0
0.5
05455-038
2.5MHz SFDR
34.2MHz SFDR
2.5MHz SNR
34.2MHz SNR
Figure 34. AD9237-65 SNR/SFDR vs. Input Common-Mode Level
In addition, a small shunt capacitor placed across the inputs
provides dynamic charging currents. This passive network
creates a low-pass filter at the ADC's input; therefore, the
precise values are dependant on the application. In IF under-
sampling applications, the shunt capacitor(s) should be reduced
or removed depending on the input frequency. In combination
with the driving source impedance, the capacitors limit the
input bandwidth.
05455-
039
VIN+
VIN
C
PAR
C
PAR
5pF
5pF
T
T
H
T
T
H
Figure 35. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched so that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core.
AD9237
Rev. 0 | Page 17 of 28
The output common mode of the reference buffer is set to mid-
supply, and the REFT and REFB voltages and input span are
defined as:
REFT = (AVDD + VREF)
REFB = (AVDD - VREF)
(
)
Factor
Span
VREF
Factor
Span
REFB
REFT
Span
_
4
_
4
=
-
=
The previous equations show that the REFT and REFB voltages
are symmetrical about the midsupply voltage, and the input
span is proportional to the value of the VREF voltage, see Table 7
for more details.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within this range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9237
set to an input span of 2 V p-p or greater. The relative SNR
degradation is 3 dB when changing from 2 V p-p mode to
1 V p-p mode.
The SHA must be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
VCM
MIN
= VREF/2
VCM
MAX
= (AVDD + VREF)/2
The minimum common-mode input level allows the AD9237 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source can be driven into VIN+ or VIN.
In this configuration, one input accepts the signal while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN. The
AD9237 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies and
in the lower speed grade models (AD9237-40 and AD9237-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9237 in a differential input configuration. For
baseband applications, the AD8351 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8351 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal. Figure 36
details a typical configuration using the AD8351.
05455-041
AD8351
AD9237
VIN+
AVDD
AGND
VIN
+
33
1k
0.1
F
0.1
F 33
15pF
0.1
F
0.1
F
1.2k
25
1k
49.9
25
2V p-p
Figure 36. Differential Input Configuration Using the AD8351
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9237. This is especially true in IF
undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 37.
05455-042
AD9237
VIN+
AVDD
AGND
VIN
33
0.1
F
33
15pF
1k
1k
2V p-p
49.9
Figure 37. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can cause core
saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 38 details a typical single-
ended input configuration.
05455-099
AD9237
VIN+
AVDD
AGND
VIN
33
0.1
F
33
15pF
1k
1k
1k
1k
25
0.1
F
49.9
2V p-p
Figure 38. Single-Ended Input Configuration
AD9237
Rev. 0 | Page 18 of 28
Table 7. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Span Factor
Resulting Differential Span (V p-p)
External Reference
AVDD
N/A
2
Factor
Span
Reference
External
_
4
1
Internal Fixed Reference
VREF
0.5
2
1.0 V
1
4.0
V
Programmable Reference
0.2 V to VREF
0.5 (1 + R2/R1)
(See Figure 40)
2
Factor
Span
VREF
_
4
1
Internal Fixed Reference
AGND to 0.2 V
1.0
2
2.0 V
1
1.0
V
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into
the AD9237. The input range can be adjusted by varying
the reference voltage applied to the AD9237, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
In all reference configurations, REFT and REFB drive the
A/D conversion core and, in conjunction with the span factor,
establish its input span. The input range of the ADC always
equals four times the voltage at the reference pin divided by
the span factor for either an internal or an external reference.
It is required to decouple REFT to REFB with 0.1 F and 10 F
decoupling capacitors, as shown in Figure 39.
Internal Reference Connection
A comparator within the AD9237 detects the potential at
the SENSE pin and configures the reference into one of four
possible states, which are summarized in Table 7. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider, setting VREF to 1 V (see Figure 39).
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected, as shown in Figure 40, then the switch is again set to
the SENSE pin. This puts the reference amplifier in a non-
inverting mode with the VREF output defined as
+
=
1
2
1
5
0
R
R
.
VREF
05455-043
ADC
CORE
VIN
SENSE
VREF
VIN+
REFT
REFB
0.1
F
0.1
F
0.1
F
10
F
+
0.5V
SELECT
LOGIC
0.1
F
+
10
F
AD9237
Figure 39. Internal Reference Configuration
05455-044
ADC
CORE
VIN
SENSE
R2
R1
VREF
VIN+
REFT
REFB
0.1
F
0.1
F
0.1
F
10
F
+
0.5V
SELECT
LOGIC
0.1
F
+
10
F
AD9237
Figure 40. Programmable Reference Configuration
AD9237
Rev. 0 | Page 19 of 28
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 41 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes. When
multiple ADCs track one another, a single reference (internal or
external) reduces gain matching errors.
When the SENSE pin is connected to AVDD, the internal
reference is disabled, allowing the use of an external reference.
An internal reference buffer loads the external reference with
an equivalent 7 k load. The internal buffer still generates the
positive and negative full-scale references, REFT and REFB, for
the ADC core. The input span is always four times the value of
the reference voltage divided by the span factor; therefore, the
external reference must be limited to a maximum of 1 V.
TEMPERATURE (C)
VR
EF ER
R
OR
(
%
)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
20
85
80
60
40
20
0
05455-046
1V REFERENCE
0.5V REFERENCE
Figure 41. Typical VREF Drift
If the internal reference of the AD9237 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 42
shows how the internal reference voltage is affected by loading.
A 2 mA load is the maximum recommended load.
LOAD (mA)
E
RROR (%)
0.05
0
0.05
0.10
0.15
0.20
0.25
0
3.0
2.5
2.0
1.5
1.0
0.5
05455-093
0.5V ERROR (%)
1V ERROR (%)
Figure 42. VREF Accuracy vs. Load
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, can be
sensitive to clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9237 contains a clock
duty cycle stabilizer (DCS) that retimes the nonsampling, or
falling edge, providing an internal clock signal with a nominal
50% duty cycle. This allows a wide range of clock input duty
cycles without affecting the performance of the AD9237. As
shown in Figure 17, noise and distortion performance are
nearly flat over a 30% range of duty cycle with the DCS enabled.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
INPUT
) due only to rms aperture jitter (t
J
) can
be calculated by
=
J
INPUT
t
f
log
n
Degradatio
SNR
2
1
20
10
In this equation, the rms aperture jitter represents the root-
sum-square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in
cases where aperture jitter can affect the dynamic range of the
AD9237. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (such as gating, dividing, or other
methods), then it should be retimed by the original clock at the
last step.
The lowest typical conversion rate of the AD9237 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
POWER DISSIPATION, POWER SCALING, AND
STANDBY MODE
As shown in Figure 43, the power dissipated by the AD9237 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
N
f
C
V
I
CLK
LOAD
DRVDD
DRVDD
=
where N is 12, the number of output bits.
AD9237
Rev. 0 | Page 20 of 28
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
CLK
/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
SAMPLE RATE (MSPS)
P
O
WE
R (mW)
190
170
150
130
110
90
70
10
60
65
50
40
30
20
05455-047
AD9237-65
AD9237-40
AD9237-20
Figure 43. Total Power vs. Sample Rate with f
IN
= 10 MHz
For the AD9237-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 43 was taken with a 5 pF load on each output driver.
The AD9237 is designed to provide excellent performance with
minimum power. The analog circuitry is optimally biased so
that each speed grade provides excellent performance while
affording reduced power consumption. Each speed grade
dissipates a baseline power at low sample rates that increases
linearly with the clock frequency, as shown in Figure 43.
The power scaling feature provides an additional power savings
when enabled, as shown in Figure 44. The power scaling mode
cannot be enabled if the clock is varied during operation. This is
because the internal circuitry cannot quickly track a changing
clock, and the part does not have enough power to operate
properly.
SAMPLE RATE (MSPS)
P
O
WE
R (mW)
190
170
150
130
110
90
70
10
60
65
50
40
30
20
05455-096
AD9237-65
AD9237-40
AD9237-20
Figure 44. Total Power vs. Sample Rate with Power Scaling Enabled
The MODE2 pin is a multilevel input that controls the span
factor and power scaling modes. The MODE2 pin is internally
pulled down to AGND by a 70 k resistor. The input threshold
and corresponding mode selections are outlined in Table 8.
Table 8. MODE2 Selection
MODE2 Voltage
Span Factor
Power Scaling
AVDD 1 Disabled
2/3 AVDD
1
Enabled
1/3 AVDD
2
Enabled
AGND (Default)
2
Disabled
The PDWN pin is a multilevel input that controls the power
states. The input threshold values and corresponding power
states are outlined in Table 9.
Table 9. PDWN Selection
PDWN Voltage
Power State
Power (mW)
AVDD Power-Down
Mode
1
1/3 AVDD
Standby Mode
20
AGND (Default)
Normal Operation
Based on speed grade
By asserting the PDWN pin high, the AD9237 is placed in
power-down mode. In this state, the ADC typically dissipates
1 mW. During power-down, the output drivers are placed in a
high impedance state. Low power dissipation in power-down
mode is achieved by shutting down the reference, reference
buffer, biasing networks, clock, and duty cycle stabilizer
circuitry. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must
be recharged when returning to normal operation.
As a result, the wake-up time is related to the time spent
in power-down mode and shorter standby cycles result in
proportionally shorter wake-up times. With the recommended
0.1 F and 10 F decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
AD9237
Rev. 0 | Page 21 of 28
By asserting the PDWN pin to AVDD/3, the AD9237 is placed
in standby mode. In this state, the ADC typically dissipates
20 mW. The output drivers are placed in a high impedance
state. The reference circuitry is enabled, allowing for a quick
start upon bringing the ADC into normal operating mode.
DIGITAL OUTPUTS
The AD9237 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that can affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9237;
these transients can detract from the converter's dynamic
performance.
As detailed in Table 10, the data format can be selected for
either offset binary, twos complement, or gray code.
Operational Mode Selection
The AD9237 can output data in either offset binary, twos
complement, or gray code format. There is also a provision
for enabling or disabling the duty cycle stabilizer (DCS).
The MODE pin is a multilevel input that controls the data
format (except for gray code) and DCS state. The MODE pin
is internally pulled down to AGND by a 70 k resistor. The
input threshold values and corresponding mode selections are
outlined in Table 10.
The gray code output format is obtained by connecting GC to
AVDD. When the part is in gray code mode, the MODE pin
controls the DCS function only. The GC pin is internally pulled
down to AGND by a 70 k resistor.
Table 10. MODE Selection
MODE Voltage
Data Format
Duty Cycle Stabilizer
AVDD Twos
Complement
Disabled
2/3 AVDD
Twos Complement
Enabled
1/3 AVDD
Offset Binary
Enabled
AGND (Default)
Offset Binary
Disabled
Out of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. The OTR pin is a digital
output that is updated along with the data output corresponding
to the particular sampled input voltage. Therefore, the OTR pin
has the same pipeline latency as the digital data. OTR is low
when the analog input voltage is within the analog input range,
and high when the analog input voltage exceeds the input range,
as shown in Figure 45. OTR remains high until the analog input
returns to within the input range and another conversion is
completed. By logically AND-ing OTR with the MSB and its
complement, overrange high or underrange low conditions can
be detected. Table 11 is a truth table for the overrange/ under-
range circuit in Figure 46, which uses NAND gates. Systems
requiring programmable gain condition of the AD9237 can,
after eight clock cycles, detect an out-of-range condition;
therefore, eliminating gain selection iterations. In addition,
OTR can be used for digital offset and gain calculation.
05455-049
FS 1/2 LSB
OTR
FS
FS + 1/2 LSB
FS 1/2 LSB
+FS 1 LSB
+FS
1 1111 1111 1111
0 1111 1111 1111
0 1111 1111 1110
0 0000 0000 0001
0 0000 0000 0000
0 0000 0000 0000
OTR DATA OUTPUTS
Figure 45. OTR Relation to Input Voltage and Output Data
Table 11. Output Data Format
OTR
MSB
Analog Input Is
0 0 Within
range
0 1 Within
range
1 0 Underrange
1 1 Overrange
05455-
050
MSB
OTR
MSB
OVER = 1
UNDER = 1
Figure 46. Overrange/Underrange Logic
Digital Output Enable Function (OE)
The AD9237 has three-state ability. The OE pin is internally
pulled down to AGND by a 70 k resistor. If the OE pin is low,
the output data drivers are enabled. If the OE pin is high, the
output data drivers are placed in a high impedance state. It is
not intended for rapid access to the data bus. Note that the
OE pin is referenced to the digital supplies (DRVDD) and
should not exceed that voltage.
Timing
The AD9237 provides latched data outputs with a pipeline delay
of eight clock cycles. Data outputs are available one propagation
delay (t
PD
) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
AD9237
Rev. 0 | Page 22 of 28
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance of
the AD9237 is shown in Figure 47. The AD9237 can be driven
single-ended or differentially through a transformer. Separate
power pins are provided to isolate the DUT from the support
circuitry. Each input configuration can be selected by proper
connection of various jumpers (refer to the schematics).
An alternative differential analog input path using an
AD8351
op amp is included in the layout but is not populated
in production. Designers interested in evaluating the op amp
with the ADC should remove C15, R12, and R3 and populate
the op amp circuit. The passive network between the AD8351
outputs and the AD9237 allows the user to optimize the
frequency response of the op amp for the application.
05455-
051
DATA
CAPTURE
AND
PROCESSING
3V
+
2.5V
+
2.5V
+
5V
+
REFIN
10MHz
REFOUT
HP8644, 2V p-p
SIGNAL SYNTHESIZER
HP8644, 2V p-p
CLOCK SYNTHESIZER
BAND-PASS
FILTER
J1
ANALOG
IN
J2
ENCODE
AVDD
DRVDD
GND
GND VDL
VAMP
AD9237
EVALUATION BOARD
P12
CLOCK
DIVIDER
Figure 47. LFCSP Evaluation Board Connections
AD9237
Rev. 0 | Page 23 of 28
AG
ND
VIN+
VIN
AVDD
CLK
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DG
ND
DRVDD
MODE
D1
OTR
PDWN
REF
B
REF
T
SENSE
VREF
AG
ND
AVDD
D0
DNC
GC
OE
MODE
2
E. PO
W
E
R DO
W
N
F
.
ST
ANDBY
G
.
PO
W
E
R UP
EXTREF
(MS
B
)
O
VER RANG
E BIT
1V MAX
AB
C
D
3.0V
3.0V
2.5V
5.0V
2
1
3
4
SINGLE ENDED INPUT
R1
2
,
R4
2
,
C1
7
ON
LY
ON
E
S
H
OU
LD
BE O
N
BO
ARD AT
A T
I
M
E
R3
, R1
8
,
C2
7
ON
LY
ON
E
S
H
OU
LD
B
E
O
N BO
ARD AT
A T
I
M
E
5
6
7
8
G
F
E
E1
4
E4
E30
E28
E27
E26
E2
2
AVDD
E2
4
E2
3
E1
8
MOD
E
E2
1
E1
9
E4
5
GN
D
AVDD
E1
5
E1
6
E1
3
9
10
12
13
14
15
2
3
4
5
6
7
8
11
6
11
E1
1
E1
0
E1
2
AVDD
E6
E7
E5
E2
GN
D
GN
D
31
28
29
30
32
27
2
17
18
19
20
22
13
21
456
78
25
26
10
13
12
11
9
14
16
15
23
24
U4
AD9237
E1
AM
PIN
AM
PINB
XFRIN
AM
P
XO
UT
XO
UTB
GN
D
AVDD
GN
D
AVDD
AIN
GN
D
GN
D
VAMP
AVDD
GN
D
AVDD
GN
D
H1 MTH
O
LE6
H2 MTH
O
LE6
H3 MTH
O
LE6
H4 MTH
O
LE6
GN
D
VDL
GND
DRVDD
D0
X
D1
X
D2
X
D3
X
D4
X
D5
X
D6
X
CL
K
D7
X
D8
X
D9
X
D1
0
X
D1
1
X
D1
2
X
D1
3
X
OR
X
GN
D
GN
D
GN
D
DRVDD
GN
D
AVDD
GN
D
GN
D
GN
D
GND
GN
D
AVDD
AIN
GN
D
GN
D
GN
D
9
10
12
13
14
15
2
3
4
5
6
7
8
11
6
11
RP2 220
RP1 220
4
5
6
2
1
3
P2
GND
E3
MODE
2
E8
E9
GND
GND
AVDD
E1
7
E2
0
E2
5
GN
D
E2
9
E32
E33
E34
E3
6
T
P
1
(
G
RAYCO
DE)
(LS
B
)
PW
DN
MO
DE 2
5
:
SHA G
A
IN 1
/
AUT
O
PO
W
E
R CO
NT
RO
L
O
F
F
6
:
SHA G
A
IN 1
/
AUT
O
PO
W
E
R CO
NT
RO
L
O
N
7
:
SHA G
A
IN 2
/
AUT
O
PO
W
E
R CO
NT
RO
L
O
N
8
:
SHA G
A
IN 2
/
AUT
O
PO
W
E
R CO
NT
RO
L
O
F
F
MO
DE SEL
ECT
1
:
2
CO
M
P
/DUT
Y CYCL
E O
F
F
2
:
2
CO
M
P
/DUT
Y CYCL
E O
N
3
:
O
F
F
E
T
BINARY/DUT
Y CYCL
E O
N
4
:
O
F
F
E
T
BINARY/DUT
Y CYCL
E O
F
F
REFERENCE
A:
EXT
ERNAL
VO
L
T
A
G
E
DIVIDER
B:
INT
E
RNAL
1
V
REF
E
RENCE
C:
EXT
ERNAL
REF
E
RENCE
D:
INT
E
RNAL
0
.
5
V
REF
E
RENCE
FOR SINGLE ENDED INPUT
PL
ACE R1
9
(
5
0
ON
B
O
TTOM)
R
42 (0
)
,
C6
, C1
8
(
0
.1
F)
AND R1
8
(
2
5
)
REM
O
VE R1
2
,
R3
, C2
7
,
C1
7
R45
1k
R8 1k
R4
6
1k
R4
7
1k
R44
1k
R43
1k
R2
5
1k
R1
3
1k
R1
8
25
R6 1k
R7 1k
R5 1k
C8 0.
1
F
C1
2
0.
1
F
C9 0.
1
F
C7 0.
1
F
C2
3
10pF
C1
6
0.
1
F
C4
2
0.
1
F
C2
6
10pF
C5
0.
1
F
C1
5
0.
1
F
C6
0.
1
F
C1
8
0.
1
F
R SING
L
E
ENDED
C1
1
0.
1
F
C1
3
0.
1
F
R1 10k
R9 10k
R3
6
1k
R4
2
0
R1
2
0
R3 0
R1
5
33
R4 33
R2
6
1k
C2
2
10
F
+
C2
9
10
F
+
C2
1
10pF
C1
9
15pF
OR
L1
FOR
FILTER
R1
0
36
R1
1
36
R2 XX
T1
A
D
T
1-1WT
16
5
NC
PRI
SEC
2
34
GND
L1
10nH
ANALOG INPUT
OP
TI
ON
A
L
X
F
R
T2
E
T
C
1-1-13
15
XO
UT
XFRIN
34
PRI
SEC
XO
UTB
GN
D
2
CT
05455-
080
GN
D
J1
Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs, and DUT
AD9237
Rev. 0 | Page 24 of 28
05455-081
TO USE AMPLIFIER
PLACE ALL COMPONENTS SHOWN HERE (RIGHT)
EXCEPT R40 OR R41
REMOVE R12, R3, R18, R42, C6, C18
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
DRVDD
DRVDD
GND
LSB
D11X
CLKLAT/DAC
D0X
GND
GND
D9X
D10X
D12X
D13X
ORX
CLKLAT/DAC
MSB
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D8X
GND
DRVDD
DRVDD
ORY
GND
GND
GND
GND
GND
GND
1CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2CLK
U1
74LVTH162374
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
GND4
GND5
GND6
GND7
VCC2
VCC3
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GND
GND1
GND2
GND3
VCC
VCC1
1OE
2OE
HEADER 40
P12
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
GND
GND
DR
GND
MSB
ORY
C27
0.1
F
C44
0.1
F
R16
0
C17
0.1
F
C28
0.1
F
C35
0.1
F
R17
0
1
PWDN
10 VOCM
2
RGP1
9 VPOS
3
INHI
8 OPHI
4
INLO
7 OPLO
5
RPG2
6 COMM
GND
AMPINB
AMPIN
GND
VAMP
VAMP
GND
C24
10
F
GND
C45
0.1
F
GND
R39
1k
R38
1k
R34
1.2k
+
R14
25
VAMP
GND
GND
POWER DOWN
USE R40 OR R41
R41
10k
R40
10k
R33
100
R35
25
GND
AMP
AMP IN
R19
50
U3
AD8351
Figure 49. LFCSP Evaluation Board Schematic, Digital Path
AD9237
Rev. 0 | Page 25 of 28
05455-082
VDL
DRVDD
DUT
BYPASSING
AVDD
C10 10
F
+
C4 10
F
+
C3 10
F
+
ANALOG
BYPASSING
AVDD
GND
C32 0.001
F
C33 0.1
F
C14 0.001
F
C41 0.1
F
C25 10
F
+
VDL
GND
C37 0.1
F
C40 0.001
F
C20 10
F
+
VAMP
GND
C46 10
F
+
LATCH
BYPASSING
DIGITAL
BYPASSING
DRVDD
GND
C30 0.001
F
C31 0.1
F
C34 0.1
F
C36 0.1
F
C38 0.001
F
C39 0.001
F
C1 0.1
F
C47 0.1
F
C48 0.001
F
C49 0.001
F
C2 10
F
+
FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27
CL
O
CK T
I
MI
NG
ADJUST
M
ENT
S
ENCX
CLK
ENC
R28 0
R27 0
U5
74VC
X
86
1A
1B
1Y
3
6
8
11
14
7
PWR
GND
2A
2B
2Y
3A
3B
3Y
4A
4B
1
2
4
5
9
10
12
13
4Y
GND
VDL
E51
E50
R32 1k
GND
VDL
E53
E52
R20 1k
GND
VDL
E35
E31
R21 1k
GND
VDL
E44
E43
R24 1k
ENC
ENCX
DR
Rx
CLKLAT/DAC
GND
ENCO
DE
J2
GND
VDL
GND
VDL
GND
C43 0.1
F
R31 1k
R30 1k
R29 50
R22 0
R37 0
R23 0
SCHEMATIC SHOWS 2 GATE DELAY SETUP FOR ONE DELAY, REMOVE BOTH RESISTORS AND ATTACH ONE FROM 2Y TO DR (Rx)
Figure 50. LFCSP Evaluation Board Schematic, Clock Input
AD9237
Rev. 0 | Page 26 of 28
05455-056
Figure 51. LFCSP Evaluation Board Layout, Primary Side
05455-057
Figure 52. LFCSP Evaluation Board Layout, Secondary Side
05455-058
Figure 53. LFCSP Evaluation Board Layout, Ground Plane
05455-059
Figure 54. LFCSP Evaluation Board Layout, Power Plane
05455-060
Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen
05455-061
Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen
AD9237
Rev. 0 | Page 27 of 28
Table 12. LFCSP Evaluation Board Bill of Materials
Item Qty. Omit
1
Reference Designator
Device
Package
Value
Recommended Vendor/
Part Number
Supplied
by ADI
18
C1, C5, C7, C8, C9, C11, C12,
C13, C15, C16, C31, C33, C34,
C36, C37, C41, C43, C47
1
9 C6, C17, C18, C27, C28,
C35, C42, C44, C45
Chip Capacitors
0603
0.1 F
8
C2, C3, C4, C10, C20,
C22, C25, C29
2
2 C24,
C46
Tantalum Capacitors
TAJD
10 F
3 8
C14, C30, C32,
C38, C39, C40, C48, C49
Chip Capacitors
0603
0.001 F
4
1
C19
Chip Capacitor
0603
15 pF
1
C26
5
2 C21,
C23
Chip Capacitors
0603
10 pF
41
E2 to E36, E43, E44, E50 to E53
2 E1,
E45
EHOLE
6
4
H1, H2, H3, H4
Headers
MTHOLE
Jumper Blocks
S1031-02-ND
7 2
J1,
J2
SMA
Connectors/50
SMA
8 1
L1
Inductor
0603
10
nH
Coilcraft/0603CS-10NXGBU
9 1
P2
Terminal
Block
TB6
Wieland/25.602.2653.0,
z5-530-0625-0
10 1
P12
Header, Dual
20-Pin RT Angle
HEADER40 Digi-Key
S2131-20-ND
5
R3, R12, R23, R28, Rx
11
6
R16, R17, R22, R27, R37, R42
Chip Resistors
0603
0
12
2
R4, R15
Chip Resistors
0603
33
19
R5 to R8, R13, R20, R21,
R24 to R26, R30 to R32, R36,
R43 to R47
13
2 R38,
R39
Chip Resistors
0603
1 k
14
2
R10, R11
Chip Resistors
0603
36
1
R29
15
1 R19
Chip Resistors
0603
50
16
2
RP1, RP2
Resistor Pack
R_742
220
Digi-Key
CTS/742C163220JTR
17 1
T1
ADT1-1WT
AWT1-1T
Mini-Circuits
18 1
U1
74LVTH162374
CMOS Register
TSSOP-48
19
1
U4
AD9237BCP ADC (DUT) LFCSP-32
Analog Devices, Inc.
X
20 1
U5
74VCX86M
SOIC-14
Fairchild
21
1
PCB
AD92XXBCP/PCB
PCB
Analog Devices, Inc.
X
22
1
U3
AD8351 Op Amp
MSOP-8
Analog Devices, Inc.
X
23 1
T2
M/A-COM
Transformer
ETC1-1-13 1-1
TX M/A-COM/ETC1-1-13
24 1
R2
Chip
Resistor
0603
SELECT
25
3
R14, R18, R35
Chip Resistors
0603
25
26
4
R1, R9, R40, R41
Chip Resistors
0603
10 k
27
1
R34
Chip Resistor
1.2 k
28
1
R33
Chip Resistor
100
Total 118 40
1
These items are included in the PCB design but are omitted at assembly.
AD9237
Rev. 0 | Page 28 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12 MAX
1.00
0.85
0.80
SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9237BCPZ-20
1 , 2
40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
CP-32-2
AD9237BCPZRL7-20
1, 2
40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
CP-32-2
AD9237BCPZ-40
1, 2
40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
CP-32-2
AD9237BCPZRL7-40
1, 2
40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
CP-32-2
AD9237BCPZ-65
1, 2
40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
CP-32-2
AD9237BCPZRL7-65
1, 2
40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
CP-32-2
AD9237BCP-20EB
Evaluation Board
AD9237BCP-40EB
Evaluation Board
AD9237BCP-65EB
Evaluation Board
T
1
Z = Pb-free part.
2
It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of
the package is achieved with exposed paddle soldered to the customer board.
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05455010/05(0)
TTT
Document Outline
-
-
- FUNCTIONAL BLOCK DIAGRAM
-
- PRODUCT HIGHLIGHTS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- External Reference Operation
-
-
-
-
-
PDF 
ZIP