REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8571/AD8572/AD8574
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
Zero-Drift, Single-Supply, Rail-to-Rail
Input/Output Operational Amplifiers
8-Lead SOIC
(R Suffix)
1
2
3
4
8
7
6
5
AD8571
IN A
V
+IN A
V+
OUT A
NC
NC
NC
NC = NO CONNECT
1
2
3
4
8
7
6
5
AD8572
IN A
V
+IN A
OUT B
IN B
V+
+IN B
OUT A
14-Lead SOIC
(R Suffix)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN A
+IN A
V+
+IN B
IN B
OUT B
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
OUT A
AD8574
FEATURES
Low Offset Voltage: 1 V
Input Offset Drift: 0.005 V/ C
Rail-to-Rail Input and Output Swing
5 V/2.7 V Single-Supply Operation
High Gain, CMRR, PSRR: 130 dB
Ultralow Input Bias Current: 20 pA
Low Supply Current: 750 A/Op Amp
Overload Recovery Time: 50 s
No External Capacitors Required
APPLICATIONS
Temperature Sensors
Pressure Sensors
Precision Current Sensing
Strain Gage Amplifiers
Medical Instrumentation
Thermocouple Amplifiers
GENERAL DESCRIPTION
This new family of amplifiers has ultralow offset, drift and bias
current. The AD8571, AD8572 and AD8574 are single, dual and
quad amplifiers featuring rail-to-rail input and output swings. All
are guaranteed to operate from 2.7 V to 5 V single supply.
The AD857x family provides the benefits previously found only in
expensive autozeroing or chopper-stabilized amplifiers. Using Analog
Devices' new topology these new zero-drift amplifiers combine low
cost with high accuracy. (No external capacitors are required.) In
addition, using a patented spread-spectrum autozero technique, the
AD857x family virtually eliminates the intermodulation effects from
interaction of the chopping function with the signal frequency in ac
applications.
With an offset voltage of only 1
V and drift of 0.005
V/
C, the
AD8571 is perfectly suited for applications where error sources
cannot be tolerated. Position, and pressure sensors, medical
equipment, and strain gage amplifiers benefit greatly from nearly
zero drift over their operating temperature range. Many more
systems require the rail-to-rail input and output swings provided
by the AD857x family.
The AD857x family is specified for the extended industrial/automotive
(40
C to +125
C) temperature range. The AD8571 single is
available in 8-lead MSOP and narrow 8-lead SOIC packages. The
AD8572 dual amplifier is available in 8-lead narrow SO and 8-lead
TSSOP surface mount packages. The AD8574 quad is available in
narrow 14-lead SOIC and 14-lead TSSOP packages.
8-Lead MSOP
(RM Suffix)
IN A
IN A
V
V+
OUT A
NC
1
4
5
8
AD8571
NC
NC = NO CONNECT
NC
8-Lead TSSOP
(RU Suffix)
IN A
+IN A
V
OUT B
IN B
+IN B
V+
1
4
5
8
AD8572
OUT A
14-Lead TSSOP
(RU Suffix)
OUT A
IN A
IN A
V
IN D
IN D
V
OUT D
N B
IN B
OUT B
IN C
OUT C
IN C
AD8574
1
14
7
8
PIN CONFIGURATIONS
8-Lead SOIC
(R Suffix)
2
REV. 0
AD8571/AD8572/AD8574SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
1
5
V
40
C
T
A
+125
C
10
V
Input Bias Current
I
B
10
50
pA
40
C
T
A
+125
C
1.0
1.5
nA
Input Offset Current
I
OS
20
70
pA
40
C
T
A
+125
C
150
200
pA
Input Voltage Range
0
5
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 5 V
120
140
dB
40
C
T
A
+125
C
115
130
dB
Large Signal Voltage Gain
1
A
VO
R
L
= 10 k
, V
O
= 0.3 V to 4.7 V
125
145
dB
40
C
T
A
+125
C
120
135
dB
Offset Voltage Drift
V
OS
/
T
40
C
T
A
+125
C
0.005 0.04
V/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
R
L
= 100 k
to GND
4.99
4.998
V
40
C to +125
C
4.99
4.997
V
R
L
= 10 k
to GND
4.95
4.98
V
40
C to +125
C
4.95
4.975
V
Output Voltage Low
V
OL
R
L
= 100 k
to V+
1
10
mV
40
C to +125
C
2
10
mV
R
L
= 10 k
to V+
10
30
mV
40
C to +125
C
15
30
mV
Short Circuit Limit
I
SC
25
50
mA
40
C to +125
C
40
mA
Output Current
I
O
30
mA
40
C to +125
C
15
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 5.5 V
120
130
dB
40
C
T
A
+125
C
115
130
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
850
975
A
40
C
T
A
+125
C
1,000 1,075
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
0.4
V/
s
Overload Recovery Time
0.05
0.3
ms
Gain Bandwidth Product
GBP
1.5
MHz
NOISE PERFORMANCE
Voltage Noise
e
n
pp
0 Hz to 10 Hz
1.3
V pp
e
n
pp
0 Hz to 1 Hz
0.41
V pp
Voltage Noise Density
e
n
f = 1 kHz
51
nV/
Hz
Current Noise Density
i
n
f = 10 Hz
2
fA/
Hz
NOTE
1
Gain testing is highly dependent upon test bandwidth.
Specifications subject to change without notice.
(V
S
= 5 V, V
CM
= 2.5 V, V
O
= 2.5 V, T
A
= 25 C unless otherwise noted)
3
REV. 0
AD8571/AD8572/AD8574
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
1
5
V
40
C
T
A
+125
C
10
V
Input Bias Current
I
B
10
50
pA
40
C
T
A
+125
C
1.0
1.5
nA
Input Offset Current
I
OS
10
50
pA
40
C
T
A
+125
C
150
200
pA
Input Voltage Range
0
2.7
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 2.7 V
115
130
dB
40
C
T
A
+125
C
110
130
dB
Large Signal Voltage Gain
1
A
VO
R
L
= 10 k
, V
O
= 0.3 V to 2.4 V
110
140
dB
40
C
T
A
+125
C
105
130
dB
Offset Voltage Drift
V
OS
/
T
40
C
T
A
+125
C
0.005 0.04
V/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
R
L
= 100 k
to GND
2.685
2.697
V
40
C to +125
C
2.685
2.696
V
R
L
= 10 k
to GND
2.67
2.68
V
40
C to +125
C
2.67
2.675
V
Output Voltage Low
V
OL
R
L
= 100 k
to V+
1
10
mV
40
C to +125
C
2
10
mV
R
L
= 10 k
to V+
10
20
mV
40
C to +125
C
15
20
mV
Short Circuit Limit
I
SC
10
15
mA
40
C to +125
C
10
mA
Output Current
I
O
10
mA
40
C to +125
C
5
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 5.5 V
120
130
dB
40
C
T
A
+125
C
115
130
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
750
900
A
40
C
T
A
+125
C
950
1,000
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
0.5
V/
s
Overload Recovery Time
0.05
ms
Gain Bandwidth Product
GBP
1
MHz
NOISE PERFORMANCE
Voltage Noise
e
n
pp
0 Hz to 10 Hz
2.0
V pp
Voltage Noise Density
e
n
f = 1 kHz
94
nV/
Hz
Current Noise Density
i
n
f = 10 Hz
2
fA/
Hz
NOTE
1
Gain testing is highly dependent upon test bandwidth.
Specifications subject to change without notice.
(V
S
= 2.7 V, V
CM
= 1.35 V, V
O
= 1.35 V, T
A
= 25 C unless otherwise noted)
AD8571/AD8572/AD8574
4
REV. 0
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND to V
S
+ 0.3 V
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . .
5.0 V
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . 2,000 V
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
RM, RU and R Packages . . . . . . . . . . . . . 65
C to +150
C
Operating Temperature Range
AD8571A/AD8572A/AD8574A . . . . . . . . 40
C to +125
C
Junction Temperature Range
RM, RU and R Packages . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Differential input voltage is limited to
5.0 V or the supply voltage, whichever is less.
Package Type
JA
1
JC
Unit
8-Lead MSOP (RM)
190
44
C/W
8-Lead TSSOP (RU)
240
43
C/W
8-Lead SOIC (R)
158
43
C/W
14-Lead TSSOP (RU)
180
36
C/W
14-Lead SOIC (R)
120
36
C/W
NOTE
1
JA
is specified for worst-case conditions, i.e.,
JA
is specified for device in socket
for P-DIP packages,
JA
is specified for device soldered in circuit board for
SOIC and TSSOP packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8571/AD8572/AD8574 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
Brand
1
AD8571ARM
2
40
C to +125
C
8-Lead MSOP
RM-8
AJA
AD8571AR
40
C to +125
C
8-Lead SOIC
SO-8
AD8572ARU
3
40
C to +125
C
8-Lead TSSOP
RU-8
AD8572AR
40
C to +125
C
8-Lead SOIC
SO-8
AD8574ARU
3
40
C to +125
C
14-Lead TSSOP
RU-14
AD8574AR
40
C to +125
C
14-Lead SOIC
SO-14
NOTES
1
Due to package size limitations, these characters represent the part number.
2
Available in reels only. 1,000 or 2,500 pieces per reel.
3
Available in reels only. 2,500 pieces per reel.
AD8571/AD8572/AD8574
5
REV. 0
OFFSET VOLTAGE V
NUMBER OF AMPLIFIERS
180
0
2.5
0.5
120
100
60
20
2.5
V
S
= 2.7V
V
CM
= 1.35V
T
A
= 25 C
40
80
140
160
1.5
0.5
1.5
Figure 1. Input Offset Voltage
Distribution at 2.7 V
OFFSET VOLTAGE V
NUMBER OF AMPLIFIERS
180
0
120
100
60
20
V
S
= 5V
V
CM
= 2.5V
T
A
= 25 C
40
80
140
160
2.5
0.5
2.5
1.5
0.5
1.5
Figure 4. Input Offset Voltage
Distribution at 5 V
LOAD CURRENT mA
10
0.1
0.001
OUTPUT VOLTAGE mV
0.1
1
10
1
100
10k
SOURCE
SINK
V
S
= 2.7V
T
A
= 25 C
100
1k
0.0001
0.01
Figure 7. Output Voltage to Supply
Rail vs. Output Current at 2.7 V
INPUT COMMON-MODE VOLTAGE V
INPUT BIAS CURRENT pA
50
30
0
1
5
2
3
4
40
30
20
10
20
10
0
V
S
= 5V
T
A
= 40 C, +25 C, +85 C
40 C
+25 C
+85 C
Figure 2. Input Bias Current vs.
Common-Mode Voltage
INPUT OFFSET DRIFT nV/ C
NUMBER OF AMPLIFIERS
12
0
0
1
6
2
3
4
5
10
8
4
2
6
V
S
= 5V
V
CM
= 2.5V
T
A
= 40 C TO +125 C
Figure 5. Input Offset Voltage Drift
Distribution at 5 V
TEMPERATURE C
INPUT BIAS CURRENT
p
A
1,000
0
75
50
125
25
0
25
50
75 100
750
500
250
150
V
CM
= 2.5V
V
S
= 5V
Figure 8. Bias Current vs. Temperature
COMMON-MODE VOLTAGE V
INPUT BIAS CURRENT pA
1,500
2,000
0
1
5
2
3
4
1,000
500
0
1,000
1,500
500
V
S
= 5V
T
A
= 125 C
Figure 3. Input Bias Current vs.
Common-Mode Voltage
LOAD CURRENT mA
10
0.1
0.001
OUTPUT VOLTAGE mV
0.1
1
10
1
100
10k
SOURCE
SINK
V
S
= 5V
T
A
= 25 C
100
1k
0.0001
0.01
Figure 6. Output Voltage to Supply
Rail vs. Output Current at 5 V
TEMPERATURE C
SUPPLY CURRENT
m
A
1.0
0.8
0
75
50
125
25
0
25
50
75 100
0.6
0.4
0.2
150
5V
2.7V
Figure 9. Supply Current vs.
Temperature
Typical Performance Characteristics
AD8571/AD8572/AD8574
6
REV. 0
SUPPLY VOLTAGE V
SUPPLY CURRENT PER AMPLIFIER
A
800
0
700
400
300
200
100
600
500
0
1
6
2
3
4
5
T
A
= 25 C
Figure 10. Supply Current vs.
Supply Voltage
FREQUENCY Hz
CLOSED-LOOP GAIN dB
100
1k
10M
10k
100k
1M
60
50
40
40
30
20
10
0
10
20
30
A
V
= 100
V
S
= 2.7V
C
L
= 0pF
R
L
= 2k
A
V
= 10
A
V
= +1
Figure 13. Closed Loop Gain vs.
Frequency at 2.7 V
FREQUENCY Hz
OUTPUT IMPEDANCE
100
1k
10M
10k
100k
1M
300
270
0
240
210
180
150
120
90
60
30
V
S
= 5V
A
V
= 100
A
V
= 1
A
V
= 10
Figure 16. Output Impedance vs.
Frequency at 5 V
FREQUENCY Hz
OPEN-LOOP GAIN dB
10k
100k
100M
1M
10M
60
50
40
40
30
20
10
0
10
20
30
45
90
135
180
225
270
0
PHASE SHIFT De
g
rees
V
S
= 2.7V
C
L
= 0pF
R
L
=
Figure 11. Open-Loop Gain and
Phase Shift vs. Frequency at 2.7 V
A
V
= 100
FREQUENCY Hz
CLOSED-LOOP GAIN dB
100
1k
10M
10k
100k
1M
60
50
40
40
30
20
10
0
10
20
30
V
S
= 5V
C
L
= 0pF
R
L
= 2k
A
V
= 10
A
V
= +1
Figure 14. Closed Loop Gain vs.
Frequency at 5 V
2 s
500mV
V
S
= 2.7V
C
L
= 300pF
R
L
= 2k
A
V
= 1
Figure 17. Large Signal Transient
Response at 2.7 V
FREQUENCY Hz
OPEN-LOOP GAIN dB
10k
100k
100M
1M
10M
60
50
40
40
30
20
10
0
10
20
30
45
90
135
180
225
270
0
PHASE SHIFT De
g
rees
V
S
= 5V
C
L
= 0pF
R
L
=
Figure 12. Open-Loop Gain and
Phase Shift vs. Frequency at 5 V
FREQUENCY Hz
OUTPUT IMPEDANCE
100
1k
10M
10k
100k
1M
300
270
0
240
210
180
150
120
90
60
30
V
S
= 2.7V
A
V
= 100
A
V
= 1
A
V
= 10
Figure 15. Output Impedance vs.
Frequency at 2.7 V
5 s
1V
V
S
= +5V
C
L
= 300pF
R
L
= 2k
A
V
= 1
Figure 18. Large Signal Transient
Response at 5 V
AD8571/AD8572/AD8574
7
REV. 0
5 s
50mV
V
S
= 1.35V
C
L
= 50pF
R
L
=
A
V
= 1
Figure 19. Small Signal Transient
Response at 2.7 V
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT %
10
100
10k
1k
45
0
40
35
30
25
20
15
10
5
+OS
OS
V
S
= 2.5V
R
L
= 2k
T
A
= 25 C
Figure 22. Small Signal Overshoot
vs. Load Capacitance at 5 V
200 s
1V
V
S
= 2.5V
R
L
= 2k
A
V
= 100
V
IN
= 60mV p-p
Figure 25. No Phase Reversal
5 s
50mV
V
S
= 2.5V
C
L
= 50pF
R
L
=
A
V
= 1
Figure 20. Small Signal Transient
Response at 5 V
V
S
= 2.5V
V
IN
= 200mV p-p
(RET TO GND)
C
L
= 0pF
R
L
= 10k
A
V
= 100
20 s
1V
0V
V
IN
V
OUT
0V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
Figure 23. Positive Overvoltage
Recovery
FREQUENCY Hz
CMRR dB
140
80
0
100
1k
10M
10k
100k
1M
60
120
20
40
100
V
S
= 2.7V
Figure 26. CMRR vs. Frequency
at 2.7 V
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT %
10
100
10k
1k
50
45
0
40
35
30
25
20
15
10
5
+OS
OS
V
S
= 1.35V
R
L
= 2k
T
A
= 25 C
Figure 21. Small Signal Overshoot
vs. Load Capacitance at 2.7 V
V
S
= 2.5V
V
IN
= 200mV p-p
(RET TO GND)
C
L
= 0pF
R
L
= 10k
A
V
= 100
20 s
1V
V
IN
0V
0V
V
OUT
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
Figure 24. Negative Overvoltage
Recovery
FREQUENCY Hz
CMRR dB
140
80
0
100
1k
10M
10k
100k
1M
60
120
20
40
100
V
S
= 5V
Figure 27. CMRR vs. Frequency
at 5 V
AD8571/AD8572/AD8574
8
REV. 0
FREQUENCY Hz
PSRR dB
140
80
0
100
1k
10M
10k
100k
1M
60
120
20
40
100
+PSRR
PSRR
V
S
= 1.35V
Figure 28. PSRR vs. Frequency
at
1.35 V
FREQUENCY Hz
OUTPUT SWING V p-p
3.0
2.5
0
100
1k
1M
10k
100k
2.0
1.5
0.5
1.0
3.5
4.0
4.5
5.0
5.5
V
S
= 2.5V
R
L
= 2k
A
V
= 1
THD+N < 1%
T
A
= 25 C
Figure 31. Maximum Output Swing
vs. Frequency at 5 V
e
n
nV/ Hz
V
S
= 2.7V
R
S
= 0
0.5
FREQUENCY kHz
1.0
1.5
2.0
2.5
0
104
156
208
260
312
364
52
Figure 34. Voltage Noise Density at
2.7 V from 0 Hz to 2.5 kHz
FREQUENCY Hz
PSRR dB
140
80
0
100
1k
10M
10k
100k
1M
60
120
20
40
100
+PSRR
PSRR
V
S
= 2.5V
Figure 29. PSRR vs. Frequency
at
2.5 V
1s
50mV
V
S
= 1.35V
A
V
= 120,000
0V
Figure 32. 0.1 Hz to 10 Hz Noise
at 2.7 V
e
n
nV/ Hz
V
S
= 2.7V
R
S
= 0
5
FREQUENCY kHz
10
15
20
25
0
32
48
64
80
96
112
16
Figure 35. Voltage Noise Density at
2.7 V from 0 Hz to 25 kHz
FREQUENCY Hz
OUTPUT SWING V p-p
3.0
2.5
0
100
1k
1M
10k
100k
2.0
1.5
0.5
1.0
V
S
= 1.35V
R
L
= 2k
A
V
= 1
THD+N < 1%
T
A
= 25 C
Figure 30. Maximum Output Swing
vs. Frequency at 2.7 V
1s
50mV
V
S
= 2.5V
A
V
= 120,000
Figure 33. 0.1 Hz to 10 Hz Noise at 5 V
V
S
= 5V
R
S
= 0
0.5
FREQUENCY kHz
1.0
1.5
2.0
2.5
0
52
78
104
130
156
182
26
e
n
nV/ Hz
Figure 36. Voltage Noise Density at
5 V from 0 Hz to 2.5 kHz
AD8571/AD8572/AD8574
9
REV. 0
e
n
nV/ Hz
5
10
15
20
25
0
V
S
= 5V
R
S
= 0
FREQUENCY kHz
32
48
64
80
96
112
16
Figure 37. Voltage Noise Density
at 5 V from 0 Hz to 25 kHz
10
TEMPERATURE C
SHORT-CIRCUIT CURRENT mA
50
30
50
75
50
125
25
0
25
50
75 100
10
150
V
S
= 2.7V
40
30
20
0
20
40
I
SC
I
SC+
Figure 40. Output Short-Circuit
Current vs. Temperature
100
TEMPERATURE C
OUTPUT VOLTAGE SWING mV
250
200
0
75
50
125
25
0
25
50
75 100
150
150
V
S
= 5V
25
50
75
125
175
225
R
L
= 1k
R
L
= 10k
R
L
= 100k
Figure 43. Output Voltage to Supply
Rail vs. Temperature
e
n
nV/ Hz
V
S
= 5V
R
S
= 0
5
10
0
FREQUENCY Hz
60
90
120
150
180
210
30
Figure 38. Voltage Noise Density
at 5 V from 0 Hz to 10 Hz
20
TEMPERATURE C
SHORT-CIRCUIT CURRENT mA
100
60
100
75
50
125
25
0
25
50
75 100
20
150
V
S
= 5V
80
60
40
0
40
80
I
SC
I
SC+
Figure 41. Output Short-Circuit
Current vs. Temperature
TEMPERATURE C
POWER SUPPLY REJECTION dB
150
145
125
75
50
125
25
0
25
50
75 100
140
135
130
150
V
S
= 2.7V TO 5.5V
Figure 39. Power-Supply Rejection
vs. Temperature
100
TEMPERATURE C
OUTPUT VOLTAGE SWING mV
250
200
0
75
50
125
25
0
25
50
75 100
150
150
V
S
= 5V
25
50
75
125
175
225
R
L
= 1k
R
L
= 10k
R
L
= 100k
Figure 42. Output Voltage to
Supply Rail vs. Temperature
AD8571/AD8572/AD8574
10
REV. 0
FUNCTIONAL DESCRIPTION
The AD857x family are CMOS amplifiers that achieve their
high degree of precision through random frequency autozero
stabilization. The autocorrection topology allows the AD857x
to maintain its low offset voltage over a wide temperature range,
and the randomized autozero clock eliminates any intermodulation
distortion (IMD) errors at the amplifier's output.
The AD857x can be run from a single supply voltage as low as
2.7 V. The extremely low offset voltage of 1
V and no IMD
products allows the amplifier to be easily configured for high
gains without risk of excessive output voltage errors. This makes
the AD857x an ideal amplifier for applications requiring both dc
precision and low distortion for ac signals. The extremely small
temperature drift of 5 nV/
C ensures a minimum of offset voltage
error over its entire temperature range of 40
C to +125
C. These
combined features make the AD857x an excellent choice for a
variety of sensitive measurement and automotive applications.
Amplifier Architecture
Each AD857x op amp consists of two amplifiers, a main amplifier
and a secondary amplifier, used to correct the offset voltage of the
main amplifier. Both consist of a rail-to-rail input stage, allowing
the input common-mode voltage range to reach both supply rails.
The input stage consists of an NMOS differential pair operating
concurrently with a parallel PMOS differential pair. The outputs
from the differential input stages are combined in another gain
stage whose output is used to drive a rail-to-rail output stage.
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain-to-source resistance of these
transistors. As the amplifier is required to source or sink more
output current, the voltage drop across these transistors increases
due to their rds. Simply put, the output voltage will not swing as
close to the rail under heavy output current conditions as it will
with light output current. This is a characteristic of all rail-to-rail
output amplifiers. Figures 6 and 7 show how close the output
voltage can get to the rails with a given output current. The out-
put of the AD857x is short circuit protected to approximately
50 mA of current.
The AD857x amplifiers have exceptional gain, yielding greater
than 120 dB of open-loop gain with a load of 2 k
. Because the
output transistors are configured in a common-source configu-
ration, the gain of the output stage, and thus the open-loop gain
of the amplifier, is dependent on the load resistance. Open-loop
gain will decrease with smaller load resistances. This is another
characteristic of rail-to-rail output amplifiers.
Basic Autozero Amplifier Theory
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for over 15 years and some
improvements have been made over time. The AD857x design
offers a number of significant performance improvements over
older versions while attaining a very substantial reduction in
device cost. This section offers a simplified explanation of how
the AD857x is able to offer extremely low offset voltages and
high open-loop gains.
As noted in the previous section on amplifier architecture, each
AD857x op amp contains two internal amplifiers. One is used as
the primary amplifier, the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figures 44 and 45 these are labeled as
V
OSX
, where x denotes the amplifier associated with the offset; A
for the nulling amplifier, B for the primary amplifier. The open-
loop gain for the +IN and IN inputs of each amplifier is given
as A
X
. Both amplifiers also have a third voltage input with an
associated open-loop gain of B
X
.
There are two modes of operation determined by the action of
two sets of switches in the amplifier: An autozero phase and an
amplification phase.
Autozero Phase
In this phase, all
A switches are closed and all
B switches are
opened. Here, the nulling amplifier is taken out of the gain loop
by shorting its two inputs together. Of course, there is a degree of
offset voltage, shown as V
OSA
, inherent in the nulling amplifier,
which maintains a potential difference between the +IN and IN
inputs. The nulling amplifier feedback loop is closed through
A
2
and V
OSA
appears at the output of the nulling amp and on C
M1
,
an internal capacitor in the AD857x. Mathematically, we can
express this in the time domain as:
V
t
A V
t
B V
t
OA
A OSA
A OA
[ ]
=
[ ]
-
[ ]
(1)
which can be expressed as,
V
t
A V
t
B
OA
A OSA
A
[ ]
=
[ ]
+
1
(2)
This shows us that the offset voltage of the nulling amplifier
times a gain factor appears at the output of the nulling amplifier
and thus on the C
M1
capacitor.
V
IN+
V
IN
V
OUT
A
B
A
A
A
B
V
OSA
+
B
B
C
M2
C
M1
A
B
V
NB
V
NA
B
A
V
OA
Figure 44. Autozero Phase of the AD857x
Amplification Phase
When the
B switches close and the
A switches open for the
amplification phase, this offset voltage remains on C
M1
and
essentially corrects any error from the nulling amplifier. The
voltage across C
M1
is designated as V
NA
. Let us also designate
V
IN
as the potential difference between the two inputs to the
primary amplifier, or V
IN
= (V
IN+
V
IN
). Now the output of the
nulling amplifier can be expressed as:
V
t
A V
t
V
t
B V
t
OA
A
IN
OSA
A
NA
[ ]
=
[ ]
-
[ ]
(
)
-
[ ]
(3)
AD8571/AD8572/AD8574
11
REV. 0
V
IN+
V
IN
V
OUT
A
B
A
A
A
B
V
OSA
+
B
B
C
M2
C
M1
A
B
V
NB
V
NA
B
A
V
OA
Figure 45. Output Phase of the Amplifier
Because
A is now open and there is no place for C
M1
to dis-
charge, the voltage V
NA
at the present time t is equal to the
voltage at the output of the nulling amp V
OA
at the time when
A was closed. If we call the period of the autocorrection
switching frequency T
S
, then the amplifier switches between
phases every 0.5
T
S
. Therefore, in the amplification phase:
V
t
V
t
T
NA
NA
S
[ ]
=
-
1
2
(4)
And substituting Equation 4 and Equation 2 into Equation 3 yields:
V
t
A V
t
A V
t
A B V
t
T
B
OA
A
IN
A OSA
A
A OSA
S
A
[ ]
=
[ ]
+
[ ]
-
-
+
1
2
1
(5)
For the sake of simplification, let us assume that the autocorrection
frequency is much faster than any potential change in V
OSA
or
V
OSB
. This is a good assumption since changes in offset voltage are
a function of temperature variation or long-term wear time, both of
which are much slower than the auto-zero clock frequency of the
AD857x. This effectively makes V
OS
time invariant and we can
rearrange Equation 5 and rewrite it as:
V
t
A V
t
A
B
V
A B V
B
OA
A
IN
A
A
OSA
A
A OSA
A
[ ]
=
[ ]
+
+
(
)
-
+
1
1
(6)
or,
V
t
A
V
t
V
B
OA
A
IN
OSA
A
[ ]
=
[ ]
+
+
1
(7)
We can already get a feel for the autozeroing in action. Note the
V
OS
term is reduced by a 1 + B
A
factor. This shows how the
nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Now the primary
amplifier output voltage is the voltage at the output of the
AD857x amplifier. It is equal to:
V
t
A V
t
V
B V
OUT
B
IN
OSB
B
NB
[ ]
=
[ ]
+
(
)
+
(8)
In the amplification phase, V
OA
= V
NB
, so this can be rewritten as:
V
t
A V
t
A V
B
A
V
t
V
B
OUT
B
IN
B OSB
B
A
IN
OSA
A
[ ]
=
[ ]
+
+
[ ]
+
+
1
(9)
Combining terms,
V
t
V
t A
A B
A B V
B
A V
OUT
IN
B
A
B
A
B OSA
A
B OSB
[ ]
=
[ ]
+
(
)
+
+
+
1
(10)
The AD857x architecture is optimized in such a way that
A
A
= A
B
and B
A
= B
B
and B
A
>> 1. Also, the gain product to
A
A
B
B
is much greater than A
B
. These allow Equation 10 to be
simplified to:
V
t
V
t A B
A V
V
OUT
IN
A
A
A
OSA
OSB
[ ]
[ ]
+
+
(
)
(11)
Most obvious is the gain product of both the primary and nulling
amplifiers. This A
A
B
A
term is what gives the AD857x its extremely
high open-loop gain. To understand how V
OSA
and V
OSB
relate to
the overall effective input offset voltage of the complete amplifier,
we should set up the generic amplifier equation of:
V
k
V
V
OUT
IN
OS
EFF
=
+
(
)
,
(12)
Where k is the open-loop gain of an amplifier and V
OS, EFF
is its
effective offset voltage. Putting Equation 12 into the form of
Equation 11 gives us:
V
t
V
t A B
V
A B
OUT
IN
A
A
OS
EFF
A
A
[ ]
[ ]
+
,
(13)
And from here, it is easy to see that:
V
V
V
B
OS
EFF
OSA
OSB
A
,
+
(14)
Thus, the offset voltages of both the primary and nulling ampli-
fiers are reduced by the gain factor B
A
. This takes a typical input
offset voltage from several millivolts down to an effective input
offset voltage of submicrovolts. This autocorrection scheme is
what makes the AD857x family of amplifiers among the most
precise amplifiers in the world.
High Gain, CMRR, PSRR
Common-mode and power supply rejection are indications of the
amount of offset voltage an amplifier has as a result of a change in its
input common-mode or power supply voltages. As shown in the
previous section, the autocorrection architecture of the AD857x
allows it to quite effectively minimize offset voltages. The technique
also corrects for offset errors caused by common-mode voltage
swings and power supply variations. This results in superb CMRR
and PSRR figures in excess of 130 dB. Because the autocorrection
occurs continuously, these figures can be maintained across the
device's entire temperature range, from 40
C to +125
C.
Maximizing Performance Through Proper Layout
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD857x, care
should be taken in the circuit board layout. The PC board sur-
face must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the circuit
board will reduce surface moisture and provide a humidity
barrier, reducing parasitic resistance on the board. The use of
guard rings around the amplifier inputs will further reduce leak-
age currents. Figure 46 shows how the guard ring should be
configured and Figure 47 shows the top view of how a surface
mount layout can be arranged. The guard ring does not need to
be a specific width, but it should form a continuous loop around
both inputs. By setting the guard ring voltage equal to the volt-
age at the noninverting input, parasitic capacitance is minimized
as well. For further reduction of leakage currents, components
can be mounted to the PC board using Teflon standoff insulators.
AD8571/AD8572/AD8574
12
REV. 0
V
OUT
V
IN
AD8572
V
OUT
V
IN
AD8572
V
OUT
V
IN
AD8572
Figure 46. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
V
V+
V
REF
V
IN1
V
IN2
GUARD
RING
R
2
R
2
R
1
R
1
AD8572
V
REF
GUARD
RING
Figure 47. Top View of AD8572 SOIC Layout with
Guard Rings
Other potential sources of offset error are thermoelectric voltages
on the circuit board. This voltage, also called Seebeck voltage,
occurs at the junction of two dissimilar metals and is proportional
to the temperature of the junction. The most common metallic
junctions on a circuit board are solder-to-board trace and solder-
to-component lead. Figure 48 shows a cross-section diagram view
of the thermal voltage error sources. If the temperature of the PC
board at one end of the component (T
A1
) is different from the
temperature at the other end (T
A2
), the Seebeck voltages will not
be equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy com-
ponents to match the thermoelectric error source. Placing the
dummy component as close as possible to its partner will ensure
both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on
the circuit board will further reduce this error. The use of a
ground plane will help distribute heat throughout the board and
will also reduce EMI noise pickup.
SURFACE MOUNT
COMPONENT
COMPONENT
LEAD
SOLDER
PC BOARD
COPPER
TRACE
V
SC2
+
+
V
TS2
T
A2
T
A1
V
SC1
+
+
V
TS1
IF T
A1
=
T
A2
, THEN
V
TS1
+ V
SC1
=
V
TS2
+ V
SC2
Figure 48. Mismatch in Seebeck Voltages Causes a
Thermoelectric Voltage Error
V
OUT
V
IN
AD857x
A
V
= 1 + (R
F
/R
1
)
R
1
R
F
R
S
= R
1
NOTE: R
S
SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R
1
TO BALANCE SEEBECK VOLTAGES
Figure 49. Using Dummy Components to Cancel
Thermoelectric Voltage Errors
1/f Noise Characteristics
Another advantage of autozero amplifiers is their ability to cancel
flicker noise. Flicker noise, also known as 1/f noise, is noise inher-
ent in the physics of semiconductor devices and increases 3 dB
for every octave decrease in frequency. The 1/f corner frequency
of an amplifier is the frequency at which the flicker noise is equal
to the broadband noise of the amplifier. At lower frequencies,
flicker noise dominates, causing higher degrees of error for sub-
Hertz frequencies or dc precision applications.
Because the AD857x amplifiers are self-correcting op amps,
they do not have increasing flicker noise at lower frequencies.
In essence, low frequency noise is treated as a slowly varying
offset error and is greatly reduced as a result of autocorrection.
The correction becomes more effective as the noise frequency
approaches dc, offsetting the tendency of the noise to increase
exponentially as frequency decreases. This allows the AD857x
to have lower noise near dc than standard low-noise amplifiers
that are susceptible to 1/f noise.
Random Autozero Correction Eliminates Intermodulation
Distortion
The AD857x can be used as a conventional op amp for gains up
to 1 MHz. The autozero correction frequency of the device
continuously varies, based on a pseudo-random generator with a
uniform distribution from 2 kHz to 4 kHz. The randomization
of the autocorrection clock creates a continuous randomization
of intermodulation distortion (IMD) products, which show up
as simple broadband noise at the output of the amplifier. This
noise naturally combines with the amplifier's voltage noise in a
root-squared-sum fashion, resulting in an output free of IMD.
Figure 50a shows the spectral output of an AD8572 with the
amplifier configured for unity gain and the input grounded. Figure
50b shows the spectral output with the amplifier configured for a
gain of 60 dB.
AD8571/AD8572/AD8574
13
REV. 0
FREQUENCY kHz
0
160
0
10
1
OUTPUT SIGNAL
2
3
4
5
6
7
8
9
20
40
60
80
100
120
V
S
= 5V
A
V
= 0dB
140
Figure 50a. Spectral Analysis of AD857x Output in
Unity Gain Configuration
FREQUENCY kHz
0
0
10
1
OUTPUT SIGNAL
2
3
4
5
6
7
8
9
20
40
60
80
100
V
S
= 5V
A
V
= 60dB
120
Figure 50b. Spectral Analysis of AD857x Output with
60 dB Gain
Figure 51 shows the spectral output of an AD8572 configured
in a high gain (60 dB) with a 1 mV input signal applied. Note
the absence of any IMD products in the spectrum. The signal-
to-noise (SNR) ratio of the output signal is better than 60 dB,
or 0.1%.
FREQUENCY kHz
0
0
10
1
OUTPUT SIGNAL
2
3
4
5
6
7
8
9
20
40
60
80
100
V
S
= 5V
A
V
= 60dB
120
Figure 51. Spectral Analysis of AD857x in High Gain with
an Input Signal
Broadband and External Resistor Noise Considerations
The total broadband noise output from any amplifier is primarily
a function of three types of noise: Input voltage noise from the
amplifier, input current noise from the amplifier and Johnson
noise from the external resistors used around the amplifier. Input
voltage noise, or e
n
, is strictly a function of the amplifier used.
The Johnson noise from a resistor is a function of the resistance
and the temperature. Input current noise, or i
n
, creates an equiva-
lent voltage noise proportional to the resistors used around the
amplifier. These noise sources are not correlated with each other
and their combined noise sums in a root-squared-sum fashion.
The full equation is given as:
e
e
kTr
i r
n TOTAL
n
s
n s
,
=
+
+
( )
2
2
1
2
4
(15)
Where, e
n
= The input voltage noise of the amplifier,
i
n
= The input current noise of the amplifier,
r
s
= Source resistance connected to the noninverting
terminal,
k = Boltzmann's constant (1.38 10
-23
J/K)
T = Ambient temperature in Kelvin (K = 273.15 +
C)
The input voltage noise density, e
n
,
of the AD857x is 51 nV/
Hz,
and the input noise, i
n
, is 2 fA/
Hz. The e
n
,
TOTAL
will be domi-
nated by input voltage noise provided the source resistance is less
than 172 k
. With source resistance greater than 172 k
, the
overall noise of the system will be dominated by the Johnson
noise of the resistor itself.
Because the input current noise of the AD857x is very small, i
n
does not become a dominant term unless r
s
is greater than 4 G
,
which is an impractical value of source resistance.
The total noise, e
n, TOTAL
, is expressed in volts-per-square-root
Hertz, and the equivalent rms noise over a certain bandwidth
can be found as:
e
e
BW
n
n
TOTAL
=
,
(16)
Where BW is the bandwidth of interest in Hertz.
For a complete treatise on circuit noise analysis, please refer to the
1995 Linear Design Seminar book available from Analog Devices.
Output Overdrive Recovery
The AD857x amplifiers have an excellent overdrive recovery of
only 200
s from either supply rail. This characteristic is particu-
larly difficult for autocorrection amplifiers, as the nulling ampli-
fier requires a substantial amount of time to error correct the
main amplifier back to a valid output. Figure 23 and Figure 24
show the positive and negative overdrive recovery time for the
AD857x.
The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to half-way between the supplies. The time from the input signal
step-down to the output settling to within 100
V of its final
value is the overdrive recovery time. Most competitors' auto-
correction amplifiers require a number of autozero clock cycles
to recover from output overdrive and some can take several
milliseconds for the output to settle properly.
AD8571/AD8572/AD8574
14
REV. 0
Input Overvoltage Protection
Although the AD857x is a rail-to-rail input amplifier, care should
be taken to ensure that the potential difference between the inputs
does not exceed 5 V. Under normal operating conditions, the
amplifier will correct its output to ensure the two inputs are at
the same voltage. However, if the device is configured as a com-
parator, or is under some unusual operating condition, the input
voltages may be forced to different potentials. This could cause
excessive current to flow through internal diodes in the AD857x
used to protect the input stage against overvoltage.
If either input exceeds either supply rail by more than 0.3 V, large
amounts of current will begin to flow through the ESD protection
diodes in the amplifier. These diodes are connected between the
inputs and each supply rail to protect the input transistors against
an electrostatic discharge event and are normally reverse-biased.
However, if the input voltage exceeds the supply voltage, these
ESD diodes will become forward-biased. Without current-limiting,
excessive amounts of current could flow through these diodes
causing permanent damage to the device. If inputs are subject to
overvoltage, appropriate series resistors should be inserted to limit
the diode current to less than 2 mA maximum.
Output Phase Reversal
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage is moved outside of the common-mode range, the outputs
of these amplifiers will suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair shut-
ting down, causing a radical shifting of internal voltages which
results in the erratic output behavior.
The AD857x amplifier has been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
within the supply voltages. If one or both inputs could exceed
either supply voltage, a resistor should be placed in series with
the input to limit the current to less than 2 mA. This will ensure
the output will not reverse its phase.
Capacitive Load Drive
The AD857x has excellent capacitive load-driving capabilities
and can safely drive up to 10 nF from a single 5 V supply.
Although the device is stable, capacitive loading will limit the
bandwidth of the amplifier. Capacitive loads will also increase
the amount of overshoot and ringing at the output. An R-C
snubber network, Figure 52, can be used to compensate the
amplifier against capacitive load ringing and overshoot.
5V
R
X
60
V
OUT
V
IN
200mV p-p
AD857x
C
L
4.7nF
C
X
0.47 F
Figure 52. Snubber Network Configuration for Driving
Capacitive Loads
Although the snubber will not recover the loss of amplifier band-
width from the load capacitance, it will allow the amplifier to drive
larger values of capacitance while maintaining a minimum of over-
shoot and ringing. Figure 53 shows the output of an AD857x
driving a 1 nF capacitor with and without a snubber network.
10 s
100mV
WITH
SNUBBER
WITHOUT
SNUBBER
V
S
= 5V
C
LOAD
= 4.7nF
Figure 53. Overshoot and Ringing are Substantially
Reduced Using a Snubber Network
The optimum value for the resistor and capacitor is a function of
the load capacitance and is best determined empirically since actual
C
LOAD
will include stray capacitances and may differ substantially
from the nominal capacitive load. Table I shows some snubber
network values that can be used as starting points.
Table I. Snubber Network Values for Driving Capacitive Loads
C
LOAD
R
X
C
X
1 nF
200
1 nF
4.7 nF
60
0.47
F
10 nF
20
10
F
Power-Up Behavior
On power-up, the AD857x will settle to a valid output within 5
s.
Figure 54a shows an oscilloscope photo of the output of the ampli-
fier along with the power supply voltage, and Figure 54b shows the
test circuit. With the amplifier configured for unity gain, the device
takes approximately 5
s to settle to its final output voltage. This
turn-on response time is much faster than most other autocorrection
amplifiers, which can take hundreds of microseconds or longer for
their output to settle.
5 s
1V
V
OUT
V+
0V
0V
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV
Figure 54a. AD857x Output Behavior on Power-Up
AD8571/AD8572/AD8574
15
REV. 0
100k
AD857x
100k
V
SY
= 0V TO 5V
V
OUT
Figure 54b. AD857x Test Circuit for Turn-On Time
APPLICATIONS
A 5 V Precision Strain-Gage Circuit
The extremely low offset voltage of the AD8572 makes it an ideal
amplifier for any application requiring accuracy with high gains,
such as a weigh scale or strain-gage. Figure 55 shows a configuration
for a single supply, precision strain-gage measurement system.
A REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference
for the top of the strain-gage resistor bridge. Q1 provides the cur-
rent drive for the 350
bridge network. A1 is used to amplify the
output of the bridge with the full-scale output voltage equal to:
2
1
2
+
(
)
R
R
R
B
(17)
Where R
B
is the resistance of the load cell. Using the values given
in Figure 55, the output voltage will linearly vary from 0 V with
no strain to 4 V under full strain.
V
OUT
350
LOAD
CELL
AD8572-A
R
3
17.4k
R
4
100
R
1
17.4k
R
2
100
0V TO 4V
NOTE:
USE 0.1% TOLERANCE RESISTORS.
20k
A1
AD8572-B
REF192
12k
1k
5V
2.5V
6
4
3
2
4.0V
40mV
FULL-SCALE
Q1
2N2222
OR
EQUIVALENT
A2
Figure 55. A 5 V Precision Strain-Gage Amplifier
3 V Instrumentation Amplifier
The high common-mode rejection, high open-loop gain, and
operation down to 3 V of supply voltage makes the AD857x an
excellent choice of op amp for discrete single supply instrumenta-
tion amplifiers. The common-mode rejection ratio of the AD857x
is greater than 120 dB, but the CMRR of the system is also a
function of the external resistor tolerances. The gain of the differ-
ence amplifier shown in Figure 56 is given as:
V
V
R
R
R
R
R
V
R
R
OUT
=
+
+
-
1
1
2
4
3
4
1
2
2
1
(18)
V2
V1
V
OUT
R
1
R
3
R
4
R
2
AD857x
IF
R
3
R
4
=
R
1
R
2
, THEN V
OUT
=
R
1
R
2
(V1 V2)
Figure 56. Using the AD857x as a Difference Amplifier
In an ideal difference amplifier, the ratio of the resistors are set
exactly equal to:
A
R
R
R
R
V
=
=
2
1
4
3
(19)
Which sets the output voltage of the system to:
V
A V
V
OUT
V
=
-
(
)
1
2
(20)
Due to finite component tolerance the ratio between the four
resistors will not be exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 56, the exact common-mode rejection ratio can be
expressed as:
CMRR
R R
R R
R R
R R
R R
=
+
+
-
1
4
2
4
2
3
1
4
2
3
2
2
2
(21)
In the 3 op amp instrumentation amplifier configuration shown
in Figure 57, the output difference amplifier is set to unity gain
with all four resistors equal in value. If the tolerance of the resis-
tors used in the circuit is given as
, the worst-case CMRR of
the instrumentation amplifier will be:
CMRR
MIN
=
1
2
(22)
V
OUT
R
R
R
R
AD8574-C
V2
R
R
V1
R
G
AD8574-B
AD8574-A
R
TRIM
V
OUT
= 1 +
2R
R
G
(V1 V2)
Figure 57. A Discrete Instrumentation Amplifier
Configuration
Thus, using 1% tolerance resistors would result in a worst-case
system CMRR of 0.02, or 34 dB. Therefore either high precision
resistors or an additional trimming resistor, as shown in Figure 57,
should be used to achieve high common-mode rejection. The value
of this trimming resistor should be equal to the value of R multi-
plied by its tolerance. For example, using 10 k
resistors with 1%
tolerance would require a series trimming resistor equal to 100
.
AD8571/AD8572/AD8574
16
REV. 0
A High Accuracy Thermocouple Amplifier
Figure 58 shows a K-type thermocouple amplifier configuration
with cold-junction compensation. Even from a 5 V supply, the
AD8571 can provide enough accuracy to achieve a resolution
of better than 0.02
C from 0
C to 500
C. D1 is used as a tempera-
ture measuring device to correct the cold-junction error from
the thermocouple and should be placed as close as possible to
the two terminating junctions. With the thermocouple measuring
tip immersed in a zero-degree ice bath, R
6
should be adjusted
until the output is at 0 V.
Using the values shown in Figure 58, the output voltage will
track temperature at 10 mV/
C. For a wider range of tempera-
ture measurement, R
9
can be decreased to 62 k
. This will
create a 5 mV/
C change at the output, allowing measurements
of up to 1000
C.
AD8571
3
8
4
0V TO 5V
(0 C TO 500 C)
5V
0.1 F
+
10 F
REF02EZ
0.1 F
12V
2
6
4
+
+
D1
1N4148
5V
K-TYPE
THERMOCOUPLE
40.7 V/ C
1
R
6
200
R
4
5.62k
R
9
124k
R
3
53.6
R
5
40.2k
R
8
453
R
1
10.7k
2
R
2
2.74k
Figure 58. A Precision K-Type Thermocouple Amplifier
with Cold-Junction Compensation
Precision Current Meter
Because of its low input bias current and superb offset voltage at
single supply voltages, the AD857x is an excellent amplifier for
precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or low-side current
monitor. Using both amplifiers in the AD8572 provides a simple
method to monitor both current supply and return paths for
load or fault detection.
Figure 59 shows a high-side current monitor configuration. Here,
the input common-mode voltage of the amplifier will be at or near
the positive supply voltage. The amplifier's rail-to-rail input provides
a precise measurement, even with the input common-mode voltage
at the supply voltage. The CMOS input structure does not draw any
input bias current, ensuring a minimum of measurement error.
The 0.1
resistor creates a voltage drop to the noninverting
input of the AD857x. The amplifier's output is corrected until
this voltage appears at the inverting input. This creates a current
through R
1
, which in turn flows through R
2
. The Monitor Output
is given by:
Monitor Output
R
R
R
I
SENSE
L
=
2
1
(23)
Using the components shown in Figure 59, the Monitor Output
transfer function is 2.5 V/A.
Figure 60 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8572 will be at or near
ground. Again, a 0.1
resistor provides a voltage drop proportional
to the return current. The output voltage is given as:
V
V
R
R
R
I
OUT
SENSE
L
= + -
2
1
(24)
For the component values shown in Figure 60, the output transfer
function decreases from V at 2.5 V/A.
8
1
4
3
3V
0.1 F
R
SENSE
0.1
V+
I
L
G
S
D
2
M1
Si9433
MONITOR
OUTPUT
3V
1/2
AD8572
R
1
100
R
2
2.49k
Figure 59. A High-Side Load Current Monitor
V+
RETURN TO
GROUND
1/2 AD8572
V+
V
OUT
Q1
R
2
2.49k
R
1
100
R
SENSE
0.1
Figure 60. A Low-Side Load Current Monitor
Precision Voltage Comparator
The AD857x can be operated open-loop and used as a precision
comparator. The AD857x has less than 50
V of offset voltage
when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed-loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the
device has a propagation delay of 15
s on the rising edge and
8
s on the falling edge.
Care should be taken to ensure the maximum differential volt-
age of the device is not exceeded. For more information, please
refer to the section on Input Overvoltage Protection.
AD8571/AD8572/AD8574
17
REV. 0
SPICE Model
The SPICE macro-model for the AD857x amplifier is given in
Listing 1. This model simulates the typical specifications for the
AD857x, and it can be downloaded from the Analog Devices
website at http://www.analog.com. The schematic of the
macro-model is shown in Figure 61.
Transistors M1 through M4 simulate the rail-to-rail input differ-
ential pairs in the AD857x amplifier. The EOS voltage source in
series with the noninverting input establishes not only the 1
V
offset voltage, but is also used to establish common-mode and
power supply rejection ratios and input voltage noise. The differ-
ential voltages from nodes 14 to 16 and nodes 17 to 18 are reflected
to E1, which is used to simulate a secondary pole-zero combination
in the open-loop gain of the amplifier.
The voltage at node 32 is then reflected to G1, which adds an
additional gain stage and, in conjunction with CF, establishes
the slew rate of the model at 0.5 V/
s. M5 and M6 are in a
common-source configuration, similar to the output stage of
the AD857x amplifier. EG1 and EG2 fix the quiescent current
in these two transistors at 100
A, and also help accurately
simulate the V
OUT
vs. I
OUT
characteristic of the amplifier.
The network around ECM1 creates the common-mode voltage
error, with CCM1 setting the corner frequency for the CMRR
roll-off. The power supply rejection error is created by the network
around EPS1, with CPS3 establishing the corner frequency for
the PSRR roll-off. The two current loops around nodes 80 and
81 are used to create a 51 nV/
Hz noise figure across RN2. All
three of these error sources are reflected to the input of the op
amp model through EOS. Finally, GSY is used to accurately
model the supply current versus supply voltage increase in
the AD857x.
This macro-model has been designed to accurately simulate a
number of specifications exhibited by the AD857x amplifier,
and is one of the most true-to-life macro-models available for
any op amp. It is optimized for operation at 27
C. Although the
model will function at different temperatures, it may lose accuracy
with respect to the actual behavior of the AD857x.
17
18
99
11
12
C2
R
C7
R
C8
R
C3
R
C4
D2
I2
V1
10
50
99
+
8
9
EOS
I1
D1
V1
2
R
C2
R
C1
C1
R
C6
R
C5
50
16
M2
M1
1
14
7
M3
M4
13
31
C2
R
2
32
R
3
+
E1
+
EREF
0
98
21
CCM1
R
CM1
22
R
CM2
ECM1
98
+
81
80
+
HN
R
N2
R
N1
VN1
98
72
CPS3
R
PS3
73
R
PS4
EPS1
98
+
99
CPS1
70
R
PS1
0
R
PS2
CPS2
50
71
99
50
GSY
M5
99
EG1
CF
+
D3
97
D4
+
EVP
EVN
98
51
M6
R
1
98
G1
+
EG2
50
47
30
45
98
+
46
Figure 61. Schematic of the AD857x SPICE Macro-Model
AD8571/AD8572/AD8574
18
REV. 0
SPICE macro-model for the AD857x
* AD8572 SPICE Macro-model
* Typical Values
* 7/99, Ver. 1.0
* TAM / ADSC
*
* Copyright 1999 by Analog Devices
*
* Refer to "README.DOC" file for License
* Statement. Use of this model indicates
* your acceptance of the terms and
* provisions in the License Statement.
*
* Node Assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
|
output
*
|
|
|
|
|
*
|
|
|
|
|
.SUBCKT AD8572
1
2
99 50 45
*
* INPUT STAGE
*
M1 4 7 8 8 PIX L=1E-6 W=355.3E-6
M2 6 2 8 8 PIX L=1E-6 W=355.3E-6
M3 11 7 10 10 NIX L=1E-6 W=355.3E-6
M4 12 2 10 10 NIX L=1E-6 W=355.3E-6
RC1 4 14 9E+3
RC2 6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1 14 16 30E-12
C2 17 18 30E-12
I1 99 8 100E-6
I2 10 50 100E-6
V1 99 9 0.3
V2 13 50 0.3
D1 8 9 DX
D2 13 10 DX
EOS 7 1 POLY(3) (22,98) (73,98) (81,98)
+ 1E-6 1 1 1
IOS 1 2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70 0 1E+6
RPS2 71 0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN 81 98 VN1 51
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 (99,50) 48E-6
EVP 97 98 (99,50) 0.5
EVN 51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=1E-6 W=1.111E-3
M6 45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,
+ VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,
+ VTO=1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,
+ VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,
+ VTO=1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8572
AD8571/AD8572/AD8574
19
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead MSOP
(RM Suffix)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
8-Lead SOIC
(R Suffix)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
8-Lead TSSOP
(RU Suffix)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.0256 (0.65)
BSC
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
14-Lead TSSOP
(RU Suffix)
14
8
7
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
14-Lead SOIC
(R Suffix)
14
8
7
1
0.3444 (8.75)
0.3367 (8.55)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
C37342.510/99
PRINTED IN U.S.A.
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