REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8320
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
Serial Digital Controlled
Variable Gain Line Driver
FEATURES
8-Bit Serial Gain Control
V/V/LSB Linear Gain Response
36 dB Gain Range
0.20 dB Gain Accuracy
Upper Bandwidth: 150 MHz
22 dBm 1 dB Compression Point (75
)
Drives Low Distortion Signals into 75
Load:
57 dBc SFDR at 42 MHz and 12 dBm Out
46 dBc SFDR at 42 MHz and 18 dBm Out
Single Supply Operation from 5 V to 12 V
Maintains 75
Output Impedance
Power-Up and Power-Down Condition
Supports SPI Input Control Standard
APPLICATIONS
Coaxial Cable Driver
HFC Cable Telephony Systems
HFC High Speed Data Modems
Interactive Set-Top Boxes
PC Plug-In Modems
Interfaces with AD9853 I
2
C Controlled Digital Modulator
High Performance Digitally Controlled Variable Gain
Block
DESCRIPTION
The AD8320 is a digitally controlled variable gain amplifier
optimized for coaxial line driving applications. An 8-bit serial
word determines the desired output gain over a 36 dB range
(256 gain levels). The AD8320 provides linear gain response.
The AD8320 is made up of a digitally controlled variable at-
tenuator of 0 dB to 36 dB, which is preceded by a low noise,
fixed gain buffer and followed by a low distortion high power
amplifier. The AD8320 has a 220
input impedance and ac-
cepts a single-ended input signal with a specified analog input
level of up to 0.310 V p-p. The output is specified for driving a
75
load, such as coaxial cable, although the AD8320 is ca-
pable of driving other loads. Distortion performance of 57 dBc
is achieved with an output level up to 12 dBm (3.1 V p-p) at
42 MHz, while 46 dBc distortion is achieved with an output
level up to 18 dBm (6.2 V p-p).
A key performance and cost advantage of the AD8320 results
from the ability to maintain a constant 75
output impedance
during power-up and power-down conditions. This eliminates
the need for external 75
back-termination, resulting in twice
the effective output voltage when compared to a standard opera-
tional amplifier. Additionally, the on-chip 75
termination
results in low glitch output during power-down and power-up
transitions, eliminating the need for an external switch.
The AD8320 is packaged in a 20-lead SOIC and operates from
a single +5 V through +12 V supply and has an operational
temperature range of 40
C to +85
C.
FREQUENCY MHz
1
10
100
20
30
40
50
60
70
80
DISTORTION dBc
P
O
= 4dBm
P
O
= 12dBm
P
O
= 8dBm
P
O
= 18dBm
Figure 1. Worst Harmonic Distortion vs. Frequency for
Various Output Levels at V
CC
= 12 V
FUNCTIONAL BLOCK DIAGRAM
POWER-
DOWN/
SWITCH
INTER.
PWR AMP
DATA SHIFT REGISTER
DATA LATCH
REVERSE
AMP
ATTENUATOR CORE
GND
VCC
VREF
VIN
REFERENCE
INV.
BUF.
DATEN
CLK
SDATA
PD
VOUT
AD8320
2
REV. 0
AD8320SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Full-Scale Input Voltage
Max Gain, P
OUT
= 18 dBm, V
CC
= 12 V
0.310
V p-p
Max Gain, P
OUT
= 12 dBm, V
CC
= 5 V
0.155
V p-p
Input Resistance
220
Input Capacitance
2.0
pF
GAIN CONTROL INTERFACE
Gain Range
36
dB
Full Scale (Max) Gain
26 (20)
dB (V/V)
Gain Offset (Min) Gain
10.0 (0.316)
dB (V/V)
Gain Scaling Factor
0.077
V/V/LSB
OUTPUT CHARACTERISTICS
Bandwidth (3 dB)
All Gain Codes
150
MHz
Bandwidth Roll-Off
F = 65 MHz
0.7
dB
Bandwidth Peaking
F = 65 MHz
0
dB
Output Offset Voltage
All Gain Codes
40
mV
Output Offset Drift
Full Temperature Range
0.25
mV/
C
Output Noise Spectral Density
Max. Gain, Frequency = 10 MHz
73
nV/
Hz
Min. Gain, Frequency = 10 MHz
53
nV/
Hz
PD = 0, Frequency = 10 MHz
4.5
nV/
Hz
1 dB Compression Point
V
CC
= 12 V
22.5
dBm
V
CC
= 5 V
16
dBm
Output Impedance
Power Up and Power Down
65
75
85
Overload Recovery
Max Gain, V
IN
= 500 mV p-p
40
ns
OVERALL PERFORMANCE
Worst Harmonic Distortion
F = 42 MHz, P
OUT
= 12 dBm, V
CC
= 12 V
57.0
52.0
dBc
F = 42 MHz, P
OUT
= 12 dBm, V
CC
= 5 V
43.0
39.0
dBc
F = 42 MHz, P
OUT
= 18 dBm, V
CC
= 12 V
46.0
42.0
dBc
F = 65 MHz, P
OUT
= 12 dBm, V
CC
= 12 V
57.0
52.0
dBc
F = 65 MHz, P
OUT
= 12 dBm, V
CC
= 5 V
42.5
39.0
dBc
F = 65 MHz, P
OUT
= 18 dBm, V
CC
= 12 V
43.0
40.0
dBc
3rd Order Intercept
F = 42 MHz, P
OUT
= 18 dBm, V
CC
= 12 V
34
dBm
F = 42 MHz, P
OUT
= 12 dBm, V
CC
= 5 V
32
dBm
F = 65 MHz, P
OUT
= 18 dBm, V
CC
= 12 V
32.5
dBm
F = 65 MHz, P
OUT
= 12 dBm, V
CC
= 5 V
28.5
dBm
Full-Scale (Max Gain) Accuracy
F = 10 MHz
0.1
dB
Gain Offset (Min Gain) Accuracy
F = 10 MHz
0.2
dB
Gain Accuracy
F = 10 MHz, All Gain Codes
0.75
0.2
0.75
dB
Gain Drift
Full Temperature Range
0.5
mdB/
C
Gain Variation w/Supply
V
CC
= +5 V to 12 V
35
mdB/V
Output Settling to 1 mV
Gain Change @ T
DATEN
= 1
Min to Max Gain, V
IN
= 0.31 V p-p
30
ns
Input Change
Max Gain, V
IN
= 0 V to 0.31 V p-p
25
ns
POWER CONTROL
Power-Down Settling Time to 1 mV
Max Gain, V
IN
= 0
45
ns
Power-Up Settling Time to 1 mV
Max Gain, V
IN
= 0
65
ns
Power-Down Pedestal Offset
Max Gain, V
IN
= 0
30
mV
Spectral Output Leakage
F (
PD) = 400 Hz @ 15% Duty Cycle
70
dBm
5 MHz
F
65 MHz
Maximum Reverse Power
PD = 0
5
dBm
POWER SUPPLY
Specified Operating Range
+5
+12
V
Quiescent Current
PD = 1, V
CC
= +5 V
80
85
mA
Power Down
PD = 0, V
CC
= +5 V
25
30
mA
Power Up, V
CC
= +12 V
PD = 1, V
CC
= +12 V
97
105
mA
Power Down, V
CC
=+12 V
PD = 0, V
CC
= +12 V
32
37
mA
(@ V
CC
= 12 V, T
A
= +25 C, V
IN
= 0.310 V
p-p, R
L
= 75
, R
S
= 75
unless
otherwise noted)
AD8320
3
REV. 0
LOGIC INPUTS (TTL/CMOS Logic)
Parameter
Min
Typ
Max
Units
Logic "1" Voltage
2.1
5.0
V
Logic "0" Voltage
0
0.8
V
Logic "1" Current (V
INH
= 5 V) CLK, SDATA,
DATEN
0
20
nA
Logic "0" Current (V
INL
= 0 V) CLK, SDATA,
DATEN
450
75
nA
Logic "1" Current (V
INH
= 5 V)
PD
0
190
A
Logic "0" Current (V
INL
= 0 V)
PD
320
70
A
TIMING REQUIREMENTS
Parameter
Min
Typ
Max
Units
Clock Pulse Width (T
WH
)
12.0
ns
Clock Period (T
C
)
32.0
ns
Setup Time SDATA vs. Clock (T
DS
)
6.5
ns
Setup Time
DATEN vs. Clock (T
ES
)
17.0
ns
Hold Time SDATA vs. Clock (T
DH
)
5.0
ns
Hold Time
DATEN vs. Clock (T
EH
)
3.0
ns
Input Rise and Fall Times, SDATA,
DATEN, Clock (T
R
, T
F
)
10
ns
T
ES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
T
DS
T
EH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
T
OFF
T
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
T
ON
T
C
T
WH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
T
DS
T
DH
CLK
Figure 3.
(
DATEN, CLK, SDATA, 5 V
V
CC
12 V; Full Temperature Range)
(Full Temperature Range, V
CC
Supply Range, T
R
= T
F
= 4 ns, F
CLK
= 8 MHz unless otherwise noted.)
AD8320
4
REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8320 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
Package Description
JA
Package Option
AD8320ARP
40
C to +85
C
20-Lead Thermally Enhanced Power SOIC*
53
C/W
RP-20
AD8320-EB
Evaluation Board
*Shipped in tubes (38 pieces/tube) and dry packed per J-STD-020.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage +V
S
Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . 0.8 V to +13 V
Input Voltages
Pins 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 V
Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V to +5 V
Internal Power Dissipation
Small Outline (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Operating Temperature Range . . . . . . . . . . . 40
C to +85
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8320
VOUT
VCC
VCC
CLK
DATEN
GND
VCC
PD
VOCM
GND
GND
VIN
VREF
VCC
BYP
GND
GND
SDATA
VCC
GND
PIN FUNCTION DESCRIPTIONS
Pin
Function
Description
1
SDATA
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
2
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0 to 1 transition latches the data bit and a 1 to 0 transfers the data bit to the slave.
This requires the input serial data word to be valid at or before this clock transition.
3
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0 to 1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhib-
its serial data transfer into the register. A 1 to 0 transition inhibits the data latch (holds the previous
gain state) and simultaneously enables the register for serial data load.
4, 11, 12,
13, 15, 16
GND
Common External Ground Reference.
5
VOCM
VCC/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC).
This port should be externally ac decoupled (0.1
F cap).
6
PD
Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the
output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and
disables the reverse amplifier.
7, 8, 9, 17, 20 VCC
Common Positive External Supply Voltage.
10
VOUT
Output Signal Port. DC biased to approximately VCC/2.
14
BYP
Internal Bypass. This pin must be externally ac decoupled (0.1
F cap).
18
VREF
Input Reference Voltage (typically 1.9 V at 27
C). This port should be externally ac decoupled
(0.1
F cap).
19
VIN
Analog Voltage Input Signal Port. DC biased to VREF voltage.
WARNING!
ESD SENSITIVE DEVICE
Typical Performance CharacteristicsAD8320
5
REV. 0
GAIN CONTROL Decimal
GAIN ERROR dB
0
0.3
0.1
0.2
0
0.1
0.2
0.3
V
CC
= 12V
F = 10MHz
T = +85 C
T = +25 C
T = 40 C
64
128
192
256
Figure 4. Gain Error vs. Gain Control
at Various Temperatures
FREQUENCY Hz
30
20
100k
1G
1M
10M
100M
10
0
10
V
CC
= 5V
GAIN dB
20
01D
00D
85D
170D
255D
Figure 7. AC Response
OUTPUT NOISE nV/
Hz
GAIN CONTROL Decimal
80
0
64
128
192
256
75
70
65
60
55
50
45
40
+85 C
40 C
+25 C
F = 10MHz
V
CC
= 12V
Figure 10. Output Referred Noise vs.
Gain Control at Various Temperatures
GAIN CONTROL Decimal
GAIN ERROR dB
0.45
0
0
0.30
0.15
0.45
64
128
192
256
0.15
F = 10MHz
T = +25 C
V
CC
= 5V
V
CC
= 12V
0.30
Figure 6. Gain Error vs. Gain Control
at Different Supply Voltages
FREQUENCY Hz
20
100k
1G
1M
10M
100M
90
V
CC
= 12V, P
IN
= 8dBm
FEEDTHROUGH dB
V
CC
= 5V, P
IN
= 14dBm
MAX GAIN
PD
= 0V
30
40
50
60
70
80
100
Figure 9. Input Signal Feedthrough
vs. Frequency
OUTPUT NOISE nV/
Hz
FREQUENCY Hz
30
100k
1M
10M
100M
40
MAX GAIN, V
CC
= 5V
50
MAX GAIN, V
CC
= 12V
MIN GAIN, V
CC
= 12V
MIN GAIN, V
CC
= 5V
60
70
80
90
Figure 12. Output Referred Noise vs.
Frequency
GAIN CONTROL Decimal
GAIN ERROR dB
0.6
0.3
0
0.9
0.6
1.2
64
128
192
256
10MHz
42MHz
65MHz
0
0.3
V
CC
= 12V
T = +25 C
Figure 5. Gain Error vs. Gain Control
at Various Frequencies
FREQUENCY Hz
30
20
100k
1G
1M
10M
100M
10
0
10
V
CC
= 12V
GAIN dB
20
01D
00D
85D
170D
255D
Figure 8. AC Response
OUTPUT NOISE nV/
Hz
GAIN CONTROL Decimal
80
0
64
128
192
256
F = 10MHz
75
70
65
60
55
50
45
40
V
CC
= 5V
V
CC
= 12V
Figure 11. Output Referred Noise vs.
Gain Control at Different Supply
Voltages
AD8320
6
REV. 0
GAIN CONTROL Decimal
DISTORTION dBc
0
64
128
192
256
F = 65MHz, P
O
= 18dBm
F = 42MHz, P
O
= 18dBm
F = 65MHz, P
O
= 12dBm
F = 42MHz, P
O
= 12dBm
30
40
50
60
70
80
90
V
CC
= 12V
Figure 13. Worst Harmonic Distor-
tion vs. Gain Control
FREQUENCY MHz
DISTORTION dBc
20
30
1
10
100
50
60
70
40
80
P
O
= 4dBm
P
O
= 8dBm
P
O
= 12dBm
P
O
= 18dBm
Figure 16. Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at V
CC
= 10 V
HARMONIC DISTORTION
dBc
PERCENTAGE
0
10
30
45
V
CC
= 12V
P
O
= 18dBm
F = 65MHz
N = 30
40
44
43
42
41
20
Figure 19. Distribution of Worst Har-
monic Distortion
FREQUENCY MHz
1
10
100
P
O
= 4dBm
DISTORTION dBc
P
O
= 10dBm
P
O
= 8dBm
P
O
= 12dBm
20
30
40
50
60
70
80
Figure 15. Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at V
CC
= 6 V
HARMONIC DISTORTION dBc
PERCENTAGE
0
30
10
20
47
V
CC
= 12V
P
O
= 18dBm
F = 42MHz
N = 30
40
46
45
44
43
Figure 18. Distribution of Worst Har-
monic Distortion
HARMONIC DISTORTION
dBc
PERCENTAGE
0
22.5
7.5
15.0
44
V
CC
= 5V
P
O
= 12dBm
F = 65MHz
N = 30
30.0
43
42
41
40
Figure 21. Distribution of Worst Har-
monic Distortion
FREQUENCY MHz
1
10
100
P
O
= 4dBm
DISTORTION dBc
P
O
= 10dBm
P
O
= 8dBm
P
O
= 12dBm
20
30
40
50
60
70
80
Figure 14. Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at V
CC
= 5 V
FREQUENCY MHz
1
10
100
P
O
= 4dBm
20
30
40
50
60
70
80
DISTORTION dBc
P
O
= 12dBm
P
O
= 8dBm
P
O
= 18dBm
Figure 17. Worst Harmonic Distor-
tion vs. Frequency for Various Output
Levels at V
CC
= 12 V
HARMONIC DISTORTION
dBc
PERCENTAGE
0
15
59
V
CC
= 12V
P
O
= 12dBm
F = 42MHz
N = 30
20
58
57
56
55
10
5
Figure 20. Distribution of Worst Har-
monic Distortion
AD8320
7
REV. 0
TEMPERATURE C
DISTORTION
dBc
60
55
25
50
100
F = 65MHz, V
CC
= 12V, P
O
= 12dBm
35
40
45
50
F = 42MHz
V
CC
= 12V
P
O
= 18dBm
65
50
25
0
75
F = 42MHz, V
CC
= 5V, P
O
= 12dBm
50
F = 65MHz
V
CC
= 12V
P
O
= 18dBm
50
Figure 22. Harmonic Distortion vs.
Temperature
V
CC
= 12V
V
IN
= 310mV p-p
MIN GAIN
F = 10MHz
12.5nsec
20mV
Figure 25. Transient Response
5nsec
500mV
V
CC
= 5V
MAX GAIN
F = 1MHz
OUTPUT VOLTAGE Volts
TIME Seconds
C
L
= 0pF
C
L
= 22pF
C
L
= 100pF
C
L
= 150pF
Figure 28. Transient Response for
Various Capacitive Loads
FREQUENCY MHz
45
1
10
100
35
30
3RD ORDER INTERCEPT dBm
40
25
V
CC
= 12V
P
O
= 12dBm
20
P
O
= 18dBm
Figure 24. Third Order Intercept vs.
Frequency
FREQUENCY Hz
30
100k
1G
1M
10M
100M
24
21
V
CC
= 5V
MAX GAIN
GAIN dB
27
C
L
= 0pF
18
15
C
L
= 22pF
C
L
= 100pF
C
L
= 150pF
Figure 27. AC Response for Various
Capacitive Loads
5nsec
1V
V
CC
= 12V
MAX GAIN
F = 1MHz
C
L
= 0pF
C
L
= 22pF
C
L
= 100pF
C
L
= 150pF
Figure 30. Transient Response for
Various Capacitive Loads
FREQUENCY MHz
P
OUT
dBm
60
40
20
0
80
41.6
20
P
O
= 18dBm
MAX GAIN
V
CC
= 12V
42.0
41.2
42.4
42.8
Figure 23. Two-Tone Intermodula-
tion Distortion
12.5nsec
1.2V
V
CC
= 12V
V
IN
= 310mV p-p
MAX GAIN
F = 10MHz
Figure 26. Transient Response
FREQUENCY Hz
30
100k
1G
1M
10M
100M
24
21
V
CC
= 12V
MAX GAIN
GAIN dB
27
C
L
= 0pF
18
15
C
L
= 22pF
C
L
= 100pF
C
L
= 150pF
Figure 29. AC Response for Various
Capacitive Loads
AD8320
8
REV. 0
5V
V
CC
= 12V
MAX GAIN
V
IN
= 0V p-p
5V
75nsec
PD
V
OUT
100mV
Figure 31. Power-Up/Power-Down
Glitch
5V
1V
V
CC
= 12V
F = 40MHz
MAX GAIN
20nsec
V
OUT
2.50V
V
IN
Figure 34. Overload Recovery
FREQUENCY Hz
80
100k
1G
1M
10M
100M
60
50
V
CC
= 5V
R
T
= 115
INPUT IMPEDANCE
70
40
Figure 37. Input Impedance vs.
Frequency
5V
500mV
V
CC
= 5V
F = 40MHz
MAX GAIN
20nsec
V
OUT
1.25V
V
IN
Figure 33. Overload Recovery
5V
V
CC
= 12V, F = 40MHz
MIN TO MAX GAIN
V
IN
= .310V p-p
20nsec
V
OUT
2.50V
DATEN
Figure 36. Output Settling Time Due
to Gain Change
TEMPERATURE C
SUPPLY CURRENT mA
120
0
50
25
100
80
60
40
20
V
CC
= 12V,
PD
= 0
V
CC
= 12V,
PD
= 1
V
CC
= 5V,
PD
= 0
V
CC
= 5V,
PD
= 1
0
25
50
75
100
Figure 39. Supply Current vs.
Temperature
5V
V
CC
= 12V
MAX GAIN
V
IN
= 0V p-p
5V
250nsec
DATEN
V
OUT
5mV
CLK
Figure 32. Clock Feedthrough
V
CC
= 12V, F = 40MHz
MAX GAIN
250mV
20nsec
V
OUT
2.00V
V
IN
Figure 35. Output Settling Time Due
to Input Change
FREQUENCY Hz
80
100k
1M
10M
100M
60
50
OUTPUT IMPEDANCE
70
90
V
CC
= 12V,
PD
= 0
V
CC
= 12V,
PD
= 1
V
CC
= 5V,
PD
= 0
V
CC
= 5V,
PD
= 1
Figure 38. Output Impedance vs.
Frequency
AD8320
9
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OPERATIONAL DESCRIPTION
The AD8320 is a digitally controlled variable gain power ampli-
fier that is optimized for driving 75
cable. A multifunctional
bipolar device on single silicon, it incorporates all the analog
features necessary to accommodate reverse path (upstream) high
speed (5 MHz to 65 MHz) cable data modem and cable tele-
phony requirements. The AD8320 has an overall gain range of
36 dB (10 dB to 26 dB) and is capable of greater than 100 MHz
of operation at output signal levels exceeding 18 dBm. Overall,
when considering the device's wide gain range, low distortion,
wide bandwidth and variable load drive, the device can be used
in many variable gain block applications.
The digitally programmable gain is controlled by the three wire
"SPI" compatible inputs. These inputs are called SDATA
(serial data input port),
DATEN (data enable low input port)
and CLK (clock input port). See Pin Function Descriptions and
Functional Block diagram. The AD8320 is programmed by an
8-bit "attenuator" word. These eight bits determine the 256
programmable gain settings. See attenuator core description
below. The gain is linear in V/V/LSB and can be described by
the following equation:
A
V
= 0.316 + 0.077
Code (R
L
= 75
)
where code is the decimal equivalent of the 8-bit word. For ex-
ample, if all 8 bits are at a logic "1," the decimal equivalent is
255 and A
V
equals 19.95 V/V or 26 dB. The gain scaling factor
is 0.077 V/V/LSB, with an offset of 0.316 V/V (10.0 dB). Fig-
ure 40 shows the linear gain versus decimal code and Figure 41
shows the gain in dB versus decimal code. Note the nonlin-
earity that results when viewed in dB versus code. The dB step
size increases as the attenuation increases (i.e., gain decreases)
and reaches a maximum step size of approximately 1.9 dB (gain
change between 01 and 00 decimal).
2
GAIN Code Decimal
0
0
256
32
GAIN V/V
64
96
128
160
192
224
22
16
12
8
6
20
18
14
10
4
POWER-DOWN
POWER-UP
2
A
V
= 0.316 + 0.077 CODE
Figure 40. Linear Gain vs. Gain Control
The AD8320 is composed of three analog functions in the power-
up or forward mode (Figure 42). The input inverter/buffer
amplifier provides single-ended to differential output conver-
sion. The output signals are nominally 180 degrees out of phase
and equal in amplitude with a differential voltage gain of 2 (6 dB).
Maintaining close to 180 degrees and equal amplitude is re-
quired for proper gain accuracy of the attenuator core over the
specified operating frequency. The input buffer/inverter also
provides equal dc voltages to the core inputs via the internal
reference. This is required to ensure proper core linearity over
the full specified power supply range (5 V to 12 V).
16
GAIN Code Decimal
8
0
256
32
GAIN dB
64
96
128
160
192
224
24
8
0
32
16
A
V
= 20 LOG
10
(0.316 + 0.077 CODE)
Figure 41. Log Gain vs. Gain Control
The attenuator core can be viewed as eight binarily weighted
(differential indifferential out) transconductance (gm) stages
with the "in phase" current outputs of all eight stages connected
in parallel to their respective differential load resistors (not
shown). The core differential output signals are also 180 degrees
out of phase and equal in amplitude. The input stages are like-
wise parallel, connected to the inverting input amplifier and
buffer outputs as shown. Nine bits plus of accuracy is achieved
for all gain settings over the specified frequency, supply voltage
and temperature range. The actual total core GM
RL attenua-
tion is determined by which combination of binarily weighted
gm stages are selected by the data latch. With 8 bits, 256 levels
of attenuation can be programmed. This results in a 36 dB
attenuation range (0 dB to 36 dB). See gain equation above.
POWER
DOWN
SWITCH
INTER.
PWR AMP
DATA SHIFT REGISTER
DATA LATCH
REVERSE
AMP
ATTENUATOR CORE
GND
VCC
VREF
VIN
REFERENCE
INV.
BUF.
DATEN
CLK
SDATA
PD
VOUT
AD8320
Figure 42. Functional Block Diagram
To update the AD8320 gain, the following digital load sequence
is required. The attenuation setting is determined by the 8-bit
word in the data latch. This 8-bit word is serially loaded (MSB
first) into the shift register at each rising edge of the clock. See
Figure 43. During this data load time (T),
DATEN is low and
the data latch is latched holding the previous (T 1) data word
keeping the attenuation level unchanged. After eight clock
cycles the new data word is fully loaded and
DATEN is
switched high. This enables the data latch (becomes transpar-
ent) and the loaded register data is passed to the attenuator with
the updated gain value. Also at this
DATEN transition, the
internal clock is disabled, thus inhibiting new serial input data.
AD8320
10
REV. 0
T
ES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
T
DS
T
EH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
T
OFF
T
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
T
ON
T
C
T
WH
VALID DATA WORD G2
Figure 43. Serial Interface Timing
what is referred to as sleep and standby modes, and VCC supply
switching via PFETS or equivalent, as described in the applica-
tions section, would be required.
APPLICATIONS
The AD8320 is primarily intended to be used as the return path
(also called upstream path) line driver in cable modem and
cable telephony applications. Data to be transmitted is modu-
lated in either QPSK or QAM format. This is done either in
DSP or by a dedicated QPSK/QAM modulator such as the
AD9853.
The amplifier receives its input signal either from the dedicated
QPSK/QAM modulator or from a DAC. In both cases, the
signal must be low-pass filtered before being applied to the line
driving amplifier.
DIPLEXER
75
TO MODEM
RECEIVE
CIRCUITRY
CENTRAL
OFFICE
SUBSCRIBER
7TH ORDER
ELLIPTIC
LOW PASS
FILTER
AD8320
AD9853
Figure 44. Block Diagram of Cable Modem's Upstream
Driver Section
The amplifier drives the line through a diplexer. The insertion
loss of a diplexer is typically 3 dB. As a result, the line driver
must deliver a power level roughly 3 dB greater than required by
the applicable cable modem standard so that diplexer losses are
canceled out.
Because the distance to the central office varies from subscriber
to subscriber, signals from different subscribers will be attenu-
ated by differing amounts. As a result, the line driver is required
to vary its gain so that all signals arriving at the central office
have the same amplitude.
The power amplifier has two basic modes of operation; forward
or power-up mode and reverse or power-down mode. In the
power-up mode (
PD = 1), the power amplifier stage is enabled
and the differential output core signal is amplified by 20 dB.
With a core attenuation range of 0 dB to 36 dB and 6 dB of
input gain, the overall AD8320 gain range is 26 dB to 10 dB.
In this mode, the single-ended output signal maintains a dc
level of VCC/2. This dc output level provides for optimum large
signal linearity and allows for dc coupling the output if neces-
sary. The output stage is unique in that it maintains a dynamic
output impedance of 75
. This allows for a direct 75
cable
connection and results in 6 dB of added load power versus using
a series 75
back-termination resistor as required with tradi-
tional low output impedance amplifiers. The power amplifier
will also drive lower or higher output loads, although the device's
gain (not gain range) will change accordingly (see Applications
section).
In the power-down mode (
PD = 0), the power amplifier is turned
off and a "reverse" amplifier (the inner triangle in Figure 42) is
enabled. During this 1 to 0 transition, the output power amplifier's
input stage is also disabled, resulting in no forward output signal
(S21 is 0), although the attenuator core and input amplifier/
buffer signals are not affected (S11
0). The function of the
reverse amplifier is to maintain 75
and VCC/2 at the output
port (VOUT) during power-down. This is required to minimize
line reflections (S22
0) and ensures proper filter operation for
any forward mode device sharing the same bus (i.e., in a multi-
plexed configuration). (See Applications section.) In the time
domain, as
PD switches states, a transitional glitch and pedestal
offset results. (See Figures 31 and 43.) The powered down
supply current drops to 32 mA versus 97 mA (V
CC
= 12 V) in
power-up mode.
Generally, using the power-down low input (
PD) for switching
allows for multiple devices to be multiplexed via splitters (N-1
off, 1 on) and reduces overall total power consumption as re-
quired for cable data applications. For cable telephony, the
power-down current generally needs to be much lower during
AD8320
11
REV. 0
Basic Connection
Figure 45 shows the basic schematic for operating the AD8320.
Because the amplifier operates from a single supply, the input
signal must be ac-coupled using a 0.1
F capacitor. The input
pin has a bias level of about 1.9 V. This bias level is available on
the VREF pin (Pin 18) and can be used to externally bias signals
if dc-coupling is desired. Under all conditions, a 0.1
F decoupling
capacitor must be connected to the VREF pin. If the VREF volt-
age is to be used externally, it should be buffered first.
The VIN pin of the AD8320 (Pin 19) has an input impedance
of 220
. Typically, in video applications, 75
termination is
favored. As a result, an external shunt resistance (R1) to ground
of 115
is required to create an overall input impedance of
75
. If 50
termination is required, a 64.9
shunt resistor
should be used. Note, to avoid dc loading of the VIN pin, the
ac-coupling capacitor should be placed between the input pin
and the shunt resistor as shown in Figure 45.
On the output side, the VOUT pin also has a dc bias level. In
this case the bias level is midway between the supply voltage and
ground. The output signal must therefore be ac-coupled before
being applied to the load. The dc bias voltage is available on the
VOCM pin (Pin 5) and can be used in dc-coupled applications.
This node must be decoupled to ground using a 0.1
F capaci-
tor. If the VOCM voltage is to be used externally, it should be
buffered.
Since the AD8320 has a dynamic output impedance of 75
, no
external back termination resistor is required. If the output
signal is being evaluated on 50
test equipment such as a spec-
trum analyzer, a 75
to 50
adapter (commonly called a pad)
should be used to maintain a properly matched circuit.
Varying the Gain
The gain of the AD8320 can be varied over a range of 36 dB,
from 10 dB to +26 dB, by varying the 8-bit gain setting word.
The timing diagram for AD8320's serial interface is shown in
Figure 43.
The write cycle to the device is initiated by the falling edge of
DATEN. This is followed by eight clock pulses that clock in the
control word. Because the clock signal is level triggered, data is
effectively clocked on the falling edge of CLK.
After the control word has been clocked in, the
DATEN line
goes back high, allowing the gain to be updated (this takes
about 30 ns).
The relationship between gain and control word is given by the
equation:
Gain (V/V) = 0.077
Code + 0.316
where code is the decimal equivalent of the gain control word
(0 to 255).
The gain in dB is given by the equation:
Gain (dB) = 20 log
10
(0.077
Code + 0.316)
The digital interface also contains an asynchronous power-down
mode. The normally high
PD line can be pulled low at any time.
This turns off the output signal after 45 ns, and reduces the
quiescent current to between 25 mA and 32 mA (depending
upon the power supply voltage). In this mode, the programmed
gain is maintained.
Clock Line Feedthrough
Clock feedthrough results in a 5 mV p-p signal appearing super-
imposed on the output signal (see Figure 32). If this impinges
upon the dynamic range of the application, the clock signal
should be noncontinuous, i.e., should only be turned on for
eight cycles during programming.
Power Supply and Decoupling
The AD8320 should be powered with a good quality (i.e., low
noise) single supply of between +5 V and +12 V. In order to
achieve an output power level of +18 dBm (6.2 V p-p) into
C6
0.1 F
CLK
SDATA
DATEN
PD
DATEN
SDATA
GND GND GND GND GND
POWER-
DOWN
/
SWITCH
INTER.
VOUT
VOCM
C10
0.1 F
C8
0.1 F
TO DIPLEXER
RIN = 75
ATTENUATOR CORE
DATA LATCH
DATA SHIFT REGISTER
CLK
C5
0.1 F
C4
0.1 F
C7
10 F
C2
0.1 F
C11
0.1 F
VCC
+5V TO +12V
VREF
C12
0.1 F
VIN
R1*
115
C1
0.1 F
INPUT
C3
0.1 F
REFERENCE
VCC
VCC
VCC
VCC
GND
BYP
AD8320
*FOR A 75 INPUT
IMPEDANCE
PD
VCC
Figure 45. Basic Connection
AD8320
12
REV. 0
75
, a supply voltage of at least +10 V is required. To achieve
a signal level of +12 dBm (about 3.1 V p-p) into 75
, a mini-
mum supply level of +5 V is required. However, for the lowest
possible distortion, the power supply voltage should be raised as
high as possible. In varying the power supply from +5 V to
+12 V, the quiescent current increases from 80 mA to 97 mA.
Careful attention must be paid to decoupling the power supply
pins. A 10
F capacitor, located fairly close to the device, is
required to provide good decoupling for lower frequency signals.
In addition, five 0.1
F decoupling capacitors should be located
close to each of the five power supply pins (7, 8, 9, 17 and 20).
A 0.1
F capacitor must also be connected to the pin labeled
BYP (Pin 14), to provide decoupling to an internal node of the
device. All six ground pins should be connected to a low imped-
ance ground plane.
Alternative Power-Down Mode
As previously mentioned, the AD8320 can be put into a low
power sleep mode by pulling the
PD pin low. If lower power
consumption is required during power-down mode, an alternative
scheme can be used as shown in Figure 46.
AD8320
*
75
AS103
(
SEE TEXT)
GND
VCC
PD
* ADDITIONAL PINS AND DECOUPLING CAPACITORS
OMITTED FOR CLARITY
75
VCC+12V
+5V
VOUT
0.1 F
0.1 F
V1
V2
0.01 F
V2
V1
SDATA
CLK
DATEN
VOUT
VOCM
0.1 F
IRLML5103
0.1 F
D
G
S
J1
J2
J3
VDD
POWER-
DOWN
PD
V2
V1
SDATA
CLK
DATEN
POWER-
DOWN
PD
OUTPUT
QUIESCENT
CURRENT
1012V
0V
0V
35V
0V
35V
0V
97mA
0mA
32mA
97mA
14
0.1 F
Figure 46. Alternative Power-Down Mode with Timing
A HEXFET power MOSFET (International Rectifier part num-
ber IRLML5103) is used to turn on and off the current to the
supply pins of the AD8320. Under normal operating conditions,
the gate (labeled POWER-DOWN) should be grounded. Pull-
ing the gate to within 2 V of the supply will open the switch and
reduce the current to the amplifier to zero.
In cable modem and cable telephony applications the modem
must always present an output impedance of 75
to the line.
This forces the line driver to always present a 75
impedance
to the diplexer. In this application, a single pole double throw
RF switch (AS103, Alpha Semiconductor) is used to switch in
an external 75
impedance when the AD8320 is turned off.
This resistor then mimics the dynamic output impedance of the
AD8320. TTL or CMOS logic can be used to drive the two
voltages driving the RF switch (V1 and V2).
Before the AD8320 is turned back on again, the gain needs to
be set to a known level. This can be done by holding the
PD pin
of the AD8320 low after POWER-DOWN has gone high. While
PD is held low, the 8-bit serial data stream can be clocked into
the AD8320. During this time the quiescent current will in-
crease to 32 mA. However, this time period can be as small as
about 1
s. In this mode the output settles about 45 ns after the
rising edge of
PD.
Alternatively, if
DATEN is held low as the AD8320 is powered
on, the device will power up in minimum gain. In this mode, the
output settles after about 200
s. Note that for both cases, the
capacitor on VOCM has been reduced from 0.1
F to 0.01
F
to facilitate a faster turn-on time. All other capacitors in the
circuit should be connected as shown in Figure 45.
AD8320
13
REV. 0
Enhanced Dynamic Range Application
The AD8320 can be combined with the AD603 to give addi-
tional dynamic range as shown in Figure 47. The AD603 is a
voltage controlled variable gain amplifier. The gain of the AD603 is
determined by the difference in voltage between the GPOS and
GNEG pins. This differential voltage has a range of
0.5 V. In
this example, the voltage on GNEG is tied to +0.5 V. As the
voltage on GPOS is varied from 0 V to 1 V, the gain of the AD603
changes from 10 dB to +30 dB with a slope of 25 mV/dB (i.e.,
linear in dB). The gain control voltage is supplied by the AD7801
DAC. The output voltage of the DAC (0 V to +2.5 V) is divided
down to fit the 0 V to 1 V range of the AD603 using a resistor
attenuator network.
In order that the same gain control word can be used for both
the AD603 and the AD8320, the serial data stream is converted
to the parallel format of the AD7801 DAC using a serial-to-
parallel shift register. The rising edge of the enable pulse simul-
taneously updates both amplifiers.
As the control word is varied from 00Dec to 255Dec, the gain of
the signal chain varies from 26 dB to +50 dB (there is 6 dB of
attenuation between AD603 and AD8320). In practice, this
circuit is not usable at the lower end of the gain range due to the
small input signal (11 dBmV or about 10 mV p-p). Figure 48
shows the spectrum of the output signal at a frequency of
42 MHz and an output level of 61 dBmV (3.1 V p-p, max gain).
The gain vs. code transfer function of the two amplifiers along
with the overall gain is shown in Figure 49. The overall gain
transfer function combines a linear in dB transfer function with
a linear in Volts/Volt transfer function. It is clear from Figure 49
that the overall gain transfer function can be considered to be
approximately linear in dB over the top 50 dB of its range.
Figure 48. Output Spectrum of Enhanced Dynamic Range
Circuit (Output Level = 61 dBmV, Frequency = 42 MHz)
0
GAIN CONTROL WORD Decimal
10
0
161
21
GAIN
41
61
81 101 121 141
50
30
20
60
40
181 201 221 241
10
20
30
AD8320/AD603
AD8320
AD603
Figure 49. Gain Transfer Function of Enhanced Dynamic
Range Circuit
75
TO MODEM
RECEIVE
CHANNEL
AD7801*
DIPLEXER
+12V
VIN
220
220
75
41dBmV
61dBmV
58dBmV
VIN
COMM
1.5
1k
+5V
5V
+0.5V
11dBmV
DATA
CLK
ENABLE
PD
D0D7
CLK
100
GPOS
GNEG
VNEG
FBDK
VOUT
VPOS
AD8320*
CS
D0D7
WR LDAC
AD603*
74HCT164*
8
A B
20pF
0.1 F
*ADDITIONAL PINS AND
DECOUPLING CAPACITORS
OMITTED FOR CLARITY
PD
CLR
VDD
REFIN
5V
AGND DGND
Figure 47. Enhanced Dynamic Range Circuit
AD8320
14
REV. 0
Varying Gain by Varying Load Impedance
As already mentioned, the AD8320 has a dynamic output im-
pedance of 75
. The specified gain range assumes that the
output is terminated with a 75
load impedance. Varying the
load impedance allows the gain to be varied, up to a maximum
of twice the specified gain (for R
L
= ). The variation in gain
with load resistance is shown in Figure 50 for the case of a gain
control word of 255Dec (i.e., max gain).
R
LOAD
32
0
100
GAIN dB
30
28
26
24
22
20
1000
10000
Figure 50. Gain vs. R
LOAD
(Gain Control Word = 255Dec)
The gain can be described by the following equation:
A
V
=
20 log
10
2 R
LOAD
R
LOAD
+
75
0.316
+
0.077
Code
(
)
where Code is the decimal equivalent of the 8-bit word.
Evaluation Board
A two layer evaluation board for the AD8320 is available (part
number AD8320-EB). This board has been carefully laid out
C6
0.1 F
DATEN
SDATA
PD
GND GND GND GND GND
POWER-
DOWN
/
SWITCH
INTER
VOUT
VOCM
C10
0.1 F
C8
0.1 F
ATTENUATOR CORE
DATA LATCH
DATA SHIFT REGISTER
CLK
C5
0.1 F
C4
0.1 F
C7
10 F
C2
0.1 F
C11
0.1 F
VREF
VIN
R1
115
C1
0.1 F
INPUT
C3
0.1 F
REFERENCE
VCC
VCC
VCC
VCC
VCC
GND
BYP
VREF
C12
0.1 F
TP2
VCC
TP4
OUTPUT
36-PIN CENTRONICS CONNECTOR
5
6
2
16, 19-30, 33
AD8320
TP3
VOCM
3
R4
0
C9
OPTIONAL
TP1
Figure 51. Evaluation Board Schematic
and tested to demonstrate the specified high speed performance
of the device. Figure 51 shows the schematic of the evaluation
board. The silkscreen for the component side layer is shown in
Figure 52. The layout of the board is shown in Figure 53 and
Figure 54.
The evaluation board package includes a fully populated board
with BNC-type connectors along with Windows
-based soft-
ware for controlling the board from a PC's printer port via a
standard printer cable.
A prototyping area is provided to allow for additional circuitry
on the board. The single supply and ground to the board are
brought over to this area and are available on two strips. There
are also two extra strips available on the prototyping area which
can be used for additional power supplies.
The board should be powered with a good quality (i.e., low
noise) single supply of between +5 V and +12 V. Extensive
decoupling is provided on the board. A 10
F capacitor, located
fairly close to the device, provides good decoupling for lower
frequency signals. In addition, and more importantly, five
0.1
F decoupling capacitors are located close to each of the
five power supply pins (7, 8, 9, 17 and 20).
Controlling the Evaluation Board from a PC
The evaluation board ships with Windows-based control soft-
ware. A standard printer cable can be used to connect the
evaluation board to a PC's printer port (also called parallel
port). The cable length should be kept to less than about 5 feet.
The wiring of a standard printer cable, with respect to the sig-
nal lines that are used in this application, is shown in Figure 55.
Although the software controls the evaluation board via the
PC's parallel port, the AD8320 digital interface is serial. Three
of the parallel port's eight bits (and one digital ground line) are
used to implement this serial interface. A fourth bit is used to
control the
PD pin.
All trademarks are the property of their respective holders.
AD8320
15
REV. 0
Figure 52. Evaluation Board Silkscreen (Component Side)
The control software requires Windows 3.1 or later to operate.
To install the software, insert the disk labeled "Disk # 1 of 2" in
the PC and run the file called SETUP.EXE. Additional installa-
tion instructions will be given on-screen. Before beginning installa-
tion, it is important to close any other Windows applications
that are running.
When you launch the installed control software from Windows,
you will be asked to select the printer port you are using. Most
modern PCs have only one printer port, usually called LPT1.
However, some laptop computers use the PRN port.
Figure 56 shows the main screen of the control software. Using
the slider, you can set any gain in the AD8320's 36 dB range.
The gain is displayed on-screen in dB and V/V. The 8-bit gain
setting byte is also displayed, in binary, hexadecimal and decimal.
Each time the slider is moved, the software automatically sends
and latches the required 8-bit data stream to the AD8320. You
can power down or reset the device simply by clicking the
appropriate buttons. The software also offers one volatile stor-
age location that can be used to store a particular gain. This
functions in the same way as the memory on a pocket calculator.
Overshoot on PC Printer Ports' Data Lines
The data lines on some printer ports have excessive overshoot.
Overshoot on the pin used as the serial clock (Pin 6 on the D-
Sub-25 connector) can cause communication problems. This
overshoot can be eliminated by applying mild filtering to the
CLK line on the evaluation board. This can be done by putting
a small series resistor on the CLK line, combined with a
capacitor to ground. Pads are provided (C9, R4) on the com-
ponent side of the evaluation board to allow easy insertion of
these devices. Determining the size of these values will take
some experimentation. Depending upon the overshoot from the
printer port, this capacitor may need to be as large as 0.01
F,
while the resistor is typically in the 50
to 100
range.
AD8320
16
REV. 0
Figure 53. Evaluation Board Layout (Component Side)
AD8320
17
REV. 0
Figure 54. Evaluation Board Layout (Solder Side)
36
18
19
1
36 PIN CENTRONICS
SDATA
14
1
25
13
DATEN
PD
CLK
GND
D-SUB 25 PIN (MALE)
SIGNAL
D-SUB-25
36-PIN CENTRONICS
DATEN
2
3
PD
3
1
DATA
5
5
CLK
6
2
DGND
25
16, 1930, 33
EVALUATION BOARD
PC
Figure 55. Interconnection Between AD8320EB and PC Printer Port
AD8320
18
REV. 0
Figure 56. Screen Display of Windows-Based Control Software
AD8320
19
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thermally Enhanced Power Small Outline Package
(RP-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0201 (0.51)
0.0130 (0.33)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
STANDOFF
0.0500 (1.27)
0.0057 (0.40)
8
0
0.0295 (0.75)
0.0098 (0.25)
x 45
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.3340 (8.61)
0.3287 (8.35)
0.1890 (4.80)
0.1791 (4.55)
20
1
11
10
HEAT
SINK
20
C316781/98
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