1 MHz 10 GHz, 40dB
Log Detector/Controller
Preliminary Technical Data
AD8319
Rev. PrC
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. Specifications subject to change without notice. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
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owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Wide bandwidth: 1 MHz to 10 GHz
High accuracy: 1.0 dB over temperature
>40dB Dynamic Range up to 5.8 GHz
Stability over temperature 0.5 dB
Low noise measurement/controller output VOUT
Pulse response time 8/10 nS (fall/rise)
Small footprint 2mm x 3mm CSP package
Supply operation: 2.7V 5.5V @ 20 mA
Fabricated using high speed SiGe process
APPLICATIONS
RF transmitter PA setpoint control and level monitoring
RSSI measurement in base stations, WLAN, WiMAX, radar
GENERAL DESCRIPTION
The AD8319 is a demodulating logarithmic amplifier, capable of
accurately converting an RF input signal to a corresponding
decibel-scaled output. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which is
equipped with a detector cell. The device can be used in either
measurement or controller modes. The AD8319 maintains
accurate log conformance for signals of 1 MHz to 6 GHz and
provides useful operation to 10 GHz. The input dynamic range is
typically 40 dB (re: 50 ) with error less than 1 dB. The
AD8319 has 4-6 ns response time that enables RF burst detection
to beyond 125 MHz. The device provides unprecedented
logarithmic intercept stability versus ambient temperature
conditions. A supply of 2.7V 5.5 V is required to power the
device. Current consumption is typically 20 mA. Power
consumption decreases to <1.0 mW when the device is disabled.
The AD8319 can be configured to provide a control voltage to a
power amplifier or a measurement output, from pin VOUT.
Since the output can be used for controller applications, special
FUNCTIONAL BLOCK DIAGRAM
DET
DET
DET
DET
V - I
I - V
Gain
Bias
Slope
VPOS
TADJ
VSET
VOUT
CLPF
COMM
I
IN
NHI
LO
Figure 1. Functional Block Diagram
attention has been paid to minimize wideband noise. In this
mode, the setpoint control voltage is applied to VSET. The
feedback loop through an RF amplifier is closed via VOUT;
the output of which regulates the amplifier's output to a
magnitude corresponding to V
SET
. The AD8319 provides 0
V to (V
POS
0.4V) output capability at the VOUT pin,
suitable for controller applications. As a measurement
device, VOUT is externally connected to VSET to produce
an output voltage V
OUT
that is a decreasing linear-in-dB
function of the RF input signal amplitude.
The logarithmic slope is -25 mV/dB, determined by the
VSET interface. The intercept is +20 dBm (re: 50 , CW
input) using the INHI input. These parameters are very
stable against supply and temperature variations.
The AD8319 is fabricated on a SiGe bipolar IC process and
is available in a 2 3 mm, 8-pin LFCSP package, for an
operating temperature range of 40
o
C to +85
o
C.
AD8319 Preliminary
Technical
Data
Rev. PrC | Page 2 of 14
TABLE OF CONTENTS
Absolute Maximum Ratings ......................................................... 6
ESD Caution ............................................................................... 6
Pin Configuration and Functional Descriptions ....................... 7
Typical Performance Characteristics........................................... 8
General Description ...................................................................... 9
Using the AD8319........................................................................ 10
Basic Connections ................................................................... 10
Input Signal Coupling ............................................................. 10
Output Interface....................................................................... 10
Setpoint Interface .....................................................................11
Temperature Compensation of Output Voltage...................11
Measurement Mode .................................................................11
Setting the Output Slope in Measurement Mode ................12
Controller Mode.......................................................................12
Evaluation Board .......................Error! Bookmark not defined.
Outline Dimensions.....................................................................14
Ordering Guide ........................................................................14
Monday, Jul 25, 2005 9:25 AM /
Rev. PrC | Page 3 of 14
SPECIFICATIONS
Table 1. V
P
= 5 V, C
LPF
= 220 pF, T
A
= 25C, 52.3 termination resistor at INHI, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Unit
SIGNAL INPUT INTERFACE
INHI (Pin 1)
Specified Frequency Range
0.001
8
GHz
DC Common-Mode Voltage
VPOS
1.6
V
MEASUREMENT MODE
VOUT (Pin 5) shorted to VSET (Pin 4), Sinusoidal
Input Signal
f = 900 MHz
TADJ = 500
Input Impedance
TBD
||pF
1 dB Dynamic Range
T
A
= +25
C
40
dB
-40C < T
A
< +85
C
TBD
dB
Maximum Input Level
1 dB Error
1
dBm
Minimum Input Level
1 dB Error
51
dBm
Slope
TBD 24.5 TBD
mV/dB
Intercept
TBD 22 TBD
dBm
Output Voltage - High Power In
P
IN
= 10dBm
TBD 0.78 TBD
V
Output Voltage - Low Power In
P
IN
= 40dBm
TBD 1.52 TBD
V
Temperature Sensitivity
P
IN
= 10dBm
25C T
A
+85C
TBD
dB/
C
10C T
A
+25C
dB/
C
40C T
A
+25C
TBD
dB/
C
f = 1.9 GHz
TADJ = 500
Input Impedance
TBD
||pF
1 dB Dynamic Range
T
A
= +25
C
40
dB
-40C < T
A
< +85
C
TBD
dB
Maximum Input Level
1 dB Error
2
dBm
Minimum Input Level
1 dB Error
52
dBm
Slope
TBD 24.4 TBD
mV/dB
Intercept
TBD 20.4 TBD
dBm
Output Voltage - High Power In
P
IN
= 10dBm
TBD 0.73 TBD
V
Output Voltage - Low Power In
P
IN
= 35dBm
TBD 1.35 TBD
V
Temperature Sensitivity
P
IN
= 10 dBm
25C T
A
+85C
TBD
dB/
C
10C T
A
+25C
dB/
C
40C T
A
+25C
TBD
dB/
C
f = 2.2 GHz
TADJ = 500
Input Impedance
TBD
||pF
1 dB Dynamic Range
T
A
= +25
C
40
dB
-40C < T
A
< +85
C
TBD
dB
Maximum Input Level
1 dB Error
2
dBm
Minimum Input Level
1 dB Error
-52
dBm
Slope
TBD 24.4 TBD
mV/dB
Intercept
TBD 19.6 TBD
dBm
Output Voltage - High Power In
P
IN
= 10 dBm
TBD 0.73 TBD
V
Output Voltage - Low Power In
P
IN
= 35dBm
TBD 1.34 TBD
V
Temperature Sensitivity
P
IN
= 10 dBm
25C T
A
+85C
TBD
dB/
C
AD8319 Preliminary
Technical
Data
Rev. PrC | Page 4 of 14
Parameter
Conditions
Min
Typ
Max
Unit
10C T
A
+25C
dB/
C
40C T
A
+25C
TBD
dB/
C
f = 3.6 GHz
TADJ = 51
Input Impedance
TBD
||pF
1 dB Dynamic Range
T
A
= +25
C
40
dB
-40C < T
A
< +85
C
TBD
dB
Maximum Input Level
1 dB Error
2
dBm
Minimum Input Level
1 dB Error
52
dBm
Slope
24.3
mV/dB
Intercept
19.8
dBm
Output Voltage - High Power In
P
IN
= 10 dBm
0.717
V
Output Voltage- Low Power In
P
IN
= 40 dBm
1.46
V
Temperature Sensitivity
P
IN
= 10 dBm
25C T
A
+85C
TBD
dB/
C
10C T
A
+25C
dB/
C
40C T
A
+25C
TBD
dB/
C
f = 5.8 GHz
TADJ = 1000
Input Impedance
TBD
||pF
1 dB Dynamic Range
T
A
= +25
C
40
dB
-40C < T
A
< +85
C
TBD
dB
Maximum Input Level
1 dB Error
1
dBm
Minimum Input Level
1 dB Error
51
dBm
Slope
24.3
mV/dB
Intercept
25
dBm
Output Voltage - High Power In
P
IN
= 10dBm
0.86
V
Output Voltage- Low Power In
P
IN
= 40dBm
1.59
V
Temperature Sensitivity
P
IN
= 10dBm
25C T
A
+85C
TBD
dB/
C
10C T
A
+25C
dB/
C
40C T
A
+25C
TBD
dB/
C
f = 8.0 GHz
TADJ = 500
Input Impedance
TBD
||pF
1 dB Dynamic Range
T
A
= +25
C
TBD
dB
-40C < T
A
< +85
C
TBD
dB
Maximum Input Level
3 dB Error
3
dBm
Minimum Input Level
3 dB Error
47
dBm
Slope
23
mV/dB
Intercept
37
dBm
Output Voltage - High Power In
P
IN
= 10dBm
1.06
V
Output Voltage - Low Power In
P
IN
= 40dBm
1.78
V
Temperature Sensitivity
P
IN
= 10dBm
25C T
A
+85C
TBD
dB/
C
10C T
A
+25C
dB/
C
40C T
A
+25C
TBD
dB/
C
Preliminary Technical Data
AD8319
Rev. PrC | Page 5 of 14
Parameter
Conditions
Min
Typ
Max
Unit
OUTPUT INTERFACE
VOUT (Pin 5)
Voltage Swing
VSET = 0 V; RFIN = Open
VPOS 0.1
V
VSET = 1.9 V; RFIN = Open
5
mV
Output Current Drive
VSET = 0 V, RFIN = Open
10
mA
Small Signal Bandwidth
RFIN = -10dBm; From CLPF to VOUT
TBD
MHz
Output Noise
RF Input = 2.2 GHz, 10 dBm, f
NOISE
= 100 kHz,
CLPF = TBD
TBD
nV/
Hz
Fall Time
Input Level = off to 10 dBm, 90 to 10%; CLPF =
open; ROUT = 150 Ohms
8
ns
Rise Time
Input Level = 10 dBm to off, 10 to 90%; CLPF =
open; ROUT = 150 Ohms
10
ns
VSET INTERFACE
VSET (Pin 4)
Nominal Input Range
RFIN = 0 dBm; measurement mode
0.4
RFIN = 65 dBm; measurement mode
1.4
V
Logarithmic Scale Factor
0.043
dB/mV
Input Resistance
RFIN = -20dBm; controller mode; VSET = 1V
40
K
TADJ INTERFACE
TADJ (Pin 6)
Nominal Input Range
Min range
TBD
V
Max
range
TBD
V
Input Resistance
TADJ = 0.9V, Sourcing 50uA
18
K
POWER INTERFACE
VPOS (Pin 7)
Supply Voltage
2.7
5.5
V
Quiescent Current
22
mA
vs. Temperature
40
C T
A
+85C
TBD
mA
Disable Current
TADJ = VPOS
200
uA
AD8319 Preliminary
Technical
Data
Rev. PrC | Page 6 of 14
ABSOLUTE MAXIMUM RATINGS
Table 2. AD8319 Absolute Maximum Ratings
Parameter Rating
Supply Voltage: VPOS
VSET Voltage
Input Power (Single-ended, re: 50
)
Internal Power Dissipation
JA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering
60 sec)
5.7 V
0 to VP
12 dBm
0.73
55
C/W
125
C
40
C to +85C
65
C to +150C
260
C
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Preliminary Technical Data
AD8319
Rev. PrC | Page 7 of 14
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Figure 2. 8-Lead Leadframe Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
7
VPOS
Positive supply voltage: +2.7 V to 5.5 V
3
CLPF
Loop Filter Capacitor
5
VOUT
Measurement and Controller output
4
VSET
Setpoint control input for controller mode, or feedback input for measurement mode
2
COMM
Device common
6
TADJ
Temperature compensation adjustment
1 INHI
RF input. Nominal input range -50 dBm to 0 dBm re: 50
; ac-coupled RF input
8
INLO
RF Common for INHI;
ac-coupled RF common
Paddle
Internally connected to COMM, solder to ground
AD8319 Preliminary
Technical
Data
Rev. PrC | Page 8 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
V
P
= 5 V, T = 25C,
40C, +85C; C
LPF
= 220 pF; T
ADJ
= 500 ; unless otherwise noted. Colors: 25C Black; -40C Blue; 85C Red
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
65
55
45
35
25
15
5
5
15
04853-007
P
IN
(dBm)
V
OUT
(V
)
2.0
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
E
RROR (dB)
PLACEHOLDER
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
65
55
45
35
25
15
5
5
15
04853-007
P
IN
(dBm)
V
OUT
(V
)
2.0
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
E
RROR (dB)
PLACEHOLDER
Figure 3: V
OUT
and Log Conformance vs. Input Amplitude at 900 MHz
Figure 4: V
OUT
and Log Conformance vs. Input Amplitude at 3.6 GHz, T
ADJ
= 51
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
65
55
45
35
25
15
5
5
15
04853-007
P
IN
(dBm)
V
OUT
(V
)
2.0
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
E
RROR (dB)
PLACEHOLDER
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
65
55
45
35
25
15
5
5
15
04853-007
P
IN
(dBm)
V
OUT
(V
)
2.0
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
E
RROR (dB)
PLACEHOLDER
Figure 5: V
OUT
and Log Conformance vs. Input Amplitude at 1.9 GHz
Figure 6: V
OUT
and Log Conformance vs. Input Amplitude at 5.8 GHz, T
ADJ
= 1000
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
65
55
45
35
25
15
5
5
15
04853-007
P
IN
(dBm)
V
OUT
(V
)
2.0
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
E
RROR (dB)
PLACEHOLDER
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
65
55
45
35
25
15
5
5
15
04853-007
P
IN
(dBm)
V
OUT
(V
)
2.0
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
E
RROR (dB)
PLACEHOLDER
Figure 7: V
OUT
and Log Conformance vs. Input Amplitude at 2.2 GHz
Figure 8: VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz
Preliminary Technical Data
AD8319
Rev. PrC | Page 9 of 14
GENERAL DESCRIPTION
The AD8319 is a 5-stage demodulating logarithmic amplifier,
specifically designed for use in RF measurement and power
control applications at frequencies up to 8 GHz. A block
diagram is shown in Figure 9. Sharing much of it's design with
the AD8318 Logarithmic Detector/Controller, the AD8319
maintains tight intercept variability versus temperature over a 40
dB range. Additional enhancements over the AD8318 such as
reduced RF burst response time of 8-10ns, 20mA supply
current, and board space requirements of only 2 mm x 3 mm
add to the low cost and high performance benefits found in the
AD8319.
DET
DET
DET
DET
V - I
I - V
Gain
Bias
Slope
VPOS
TADJ
VSET
VOUT
CLPF
COMM
INHI
INLO
Figure 9: Block Diagram
A fully differential design, using a proprietary high speed
SiGe process, extends high frequency performance. Input INHI
receives the signal with a low frequency impedance of nominally
500 in parallel with 0.7 pF. The maximum input with +/-1 dB
log-conformance error is typically 0 dBm (Re: 50 ). The noise
spectral density referred to the input is 1.15 nV/Hz, which is
equivalent to a voltage of 118 V rms in a 10.5 GHz bandwidth,
or a noise power of 66 dBm (Re: 50 ). This noise spectral
density sets the lower limit of the dynamic range. However, the
low-end accuracy of the AD8319 is enhanced by specially
shaping the demodulating transfer characteristic to partially
compensate for errors due to internal noise. The common pin,
COMM, provides a quality low impedance connection to the
printed circuit board (PCB) ground. The package paddle, which
is internally connected to the COMM pin, should also be
grounded to the PCB to reduce thermal impedance from the die
to the PCB.
The logarithmic function is approximated in a piecewise fashion
by 6 cascaded gain stages. (For a more comprehensive
explanation of the logarithm approximation, please refer to the
AD8307 data sheet, available at
www.analog.com
.) The cells have
a nominal voltage gain of 9 dB each, and a 3 dB bandwidth of
10.5 GHz. Using precision biasing, the gain is stabilized over
temperature and supply variations. The overall dc gain is high
due to the cascaded nature of the gain stages. An offset
compensation loop is included to correct for offsets within the
cascaded cells. At the output of each of the gain stages, a square-
law detector cell is used to rectify the signal. The RF signal
voltages are converted to a fluctuating differential current
having an average value that increases with signal level.
Along with the six gain stages and detector cells, an
additional detector is included at the input of the AD8319,
altogether providing a 40 dB dynamic range. After the
detector currents are summed and filtered, the function
I
D
log
10
(V
IN
/V
INTERCEPT
) is formed at the summing node,
where I
D
is the internally set detector current, V
IN
is the
input signal voltage, and V
INTERCEPT
is the intercept voltage
(i.e., when V
IN
= V
INTERCEPT
, the output voltage would be 0 V,
if it were capable of going to 0 V).
AD8319 Preliminary
Technical
Data
Rev. PrC | Page 10 of 14
USING THE AD8319
BASIC CONNECTIONS
The AD8319 is specified for operation up to 10 GHz, as a result
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 2.7 V
and 5.5 V should be applied to VPOS. 100 pF and 0.1 F power
supply decoupling capacitors should be connected close to this
power supply pin. .
Figure 10: Basic Connections
The paddle of the AD8319's LFCSP package is internally
connected to COMM. For optimum thermal and electrical
performance, the paddle should be soldered to a low impedance
ground plane.
INPUT SIGNAL COUPLING
The RF input to the AD8319 (INHI) is single-ended and must
be ac-coupled. INLO (input common) should be ac-coupled to
ground. Suggested coupling capacitors are 1 nF ceramic 0402
style capacitors for input frequencies of 1 MHz to 8 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the input stage's high-pass cutoff frequency. The high-pass
corner is set by the input coupling capacitors and the internal 10
pF high-pass capacitor. The dc voltage on INHI and INLO will
be about one diode voltage drop below V
S
.
VPOS
2k
A = 9dB
18.7k
18.7k
CURRENT
Gm
STAGE
INLO
INHI
OFFSET
COMP
5pF
5pF
FIRST
GAIN
STAGE
Figure 11: Input Interface
While the input can be reactively matched, in general this is
not necessary. An external 52.3 shunt resistor (connected
on the signal side of the input coupling capacitors, see
Figure 10) combines with the relatively high input
impedance to give an adequate broadband 50 match.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal
10 resistor is placed in series with the emitter follower
output and the VOUT pin. The rise time of the output is
limited mainly by the slew on CLPF. The fall time is an RC
limited slew given by the load capacitance and the pull-
down resistance at VOUT. There is an internal pull-down
resistor of 1.6 k. Any resistive load at VOUT is placed in
parallel with the internal pull-down resistor and provides
additional discharge current.
+
0.2V
1200
400
10
VOUT
VPOS
CLPF
COMM
Figure 12: Output Interface
Preliminary Technical Data
AD8319
Rev. PrC | Page 11 of 14
SETPOINT INTERFACE
The V
SET
input drives the high impedance (20 k) input of an
internal op amp. The V
SET
voltage appears across the internal
1.48 k resistor to generate I
SET
. When a portion of V
OUT
is
applied to VSET, the feedback loop forces -I
D
log
10-
(V
IN
/V
INTERCEPT
) = I
SET
. If V
SET
= V
OUT
/X, then I
SET
=
V
OUT
/(X 1.48 k). The result is:
V
OUT
= (-I
D
1.48k X) log
10
(V
IN
/V
INTERCEPT
)
I
SET
COMM
VSET
20 k
COMM
20 k
1.5 k
V
SET
Figure 13: VSET Interface
The slope is given by I
D
X 1.48 k = 500 mV X. For
example, if a resistor divider to ground is used to generate a V
SET
voltage of V
OUT
/2, then X = 2. The slope will be set to
1 V/decade or 50 mV/dB.
TEMPERATURE COMPENSATION OF OUTPUT
VOLTAGE
The primary component of the variation in V
OUT
versus
temperature, as the input signal amplitude is held constant, is
drift of the intercept. This drift is also a weak function of the
input signal frequency, so provision is made for optimization of
internal temperature compensation at a given frequency by
providing pin TADJ.
COMM
TADJ
COMM
1.5 k
V
INTERNAL
RTADJ
ICOMP
Figure 14: TADJ Interface
A resistor (values TBD) is connected between this pin and
ground (14). The value of this resistor partially determines the
magnitude of an analog correction coefficient, which is
employed to reduce intercept drift.
The relationship between output temperature drift and
frequency is not linear and cannot be easily modeled. As a result,
experimentation is required to choose the correct T
ADJ
resistor.
Table 4: Recommended T
ADJ
Resistor Values
Frequency Recommended
T
ADJ
100 MHz
10 k
900 MHz
10 k
1.8 GHZ
10 k
1.9 GHz
10 k
2.2 GHz
10 k
3.6 GHz
18 k
5.3 GHZ
1 k
5.8 GHz
1 k
8 GHz
28 k
10 GHz
TBD
MEASUREMENT MODE
When the V
OUT
voltage or a portion of the V
OUT
voltage is
fed back to the VSET pin, the device operates in
measurement mode. As seen in Figure 15 the AD8319 has
an offset voltage, a negative slope, and a V
OUT
measurement
intercept at the high end of its input signal range.
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
65 60 55 50 45 40 35 30 25 20 15 10 5
0
5
04853-029
P
IN
(dBm)
INTERCEPT
ERROR (dB)
V
OU
T
(V)
ERROR 25
C
V
OUT
25
C
RANGE FOR CALCULATION
OF SLOPE AND INTERCEPT
Figure 15: Typical Output Voltage vs. Input Signal
The output voltage versus input signal voltage of the
AD8319 is linear-in-dB over a multidecade range. The
equation for this function is of the form
V
OUT
= X V
SLOPE/DEC
log10(V
IN
/V
INTERCEPT
) (1)
= X V
SLOPE/dB
20 log10(V
IN
/V
INTERCEPT
) (2)
where
AD8319 Preliminary
Technical
Data
Rev. PrC | Page 12 of 14
X is the feedback factor in V
SET
= V
OUT
/X
V
SLOPE/DEC
is nominally 500 mV/decade
or -25 mV/dB
V
INTERCEPT
is the x-axis intercept of the linear-in-dB portion of
the V
OUT
vs. V
IN
curve (
Figure 15)
. V
INTERCEPT
is +7 dBV for a
sinusoidal input signal.
An offset voltage, V
OFFSET
, of 0.5 V is internally added to the
detector signal, so that the minimum value for V
OUT
is
X V
OFFSET
, so for X = 1, minimum V
OUT
is 0.5 V.
The slope is very stable versus process and temperature
variation. When base-10 logarithms are used, V
SLOPE/DECADE
represents the "volts/decade." A decade corresponds to 20 dB,
V
SLOPE/DECADE
/20 = V
SLOPE/dB
represents the slope in "volts/dB."
As noted in the equations above, the V
OUT
voltage has a negative
slope. This is also the correct slope polarity to control the gain of
many power amplifiers in a negative feedback configuration.
Since both the slope and intercept vary slightly with frequency, it
is recommended to refer to the specification pages for
application specific values for slope and intercept.
Although demodulating log amps respond to input signal
voltage, not input signal power, it is customary to discuss the
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z
o
, must be
known to convert voltages to their corresponding power levels.
The following equations are used to perform this conversion.
P(dBm) = 10 log
10
(V
rms
2
/(Z
O
1 mW)) (3)
P(dBV) = 20 log
10
(V
rms
/1 V
rms
) (4)
P(dBm) = P(dBV) 10log
10
(Z
O
1 mW/1V
rms
2
) . (5)
For example, P
INTERCEPT
for a sinusoidal input signal expressed in
terms of dBm (decibels referred to 1 mW), in a 50 system is:
P
INTERCEPT
(dBm) = P
INTERCEPT
(dBV) 10 log10(Zo
1 mW/1V
rms
2
) (6)
= +7 dBV 10 log
10
(5010
-3
) = +20 dBm
For a square wave input signal in a 200 system,
P
INTERCEPT
= 4 dBV 10 log
10
(200 1 mW/1V
rms
2
)] =
+11 dBm
Further information on the intercept variation dependence
upon waveform can be found in the AD8313 and AD8307 data
sheets.
SETTING THE OUTPUT SLOPE IN
MEASUREMENT MODE
To operate in measurement mode, VOUT must be
connected to VSET. Connecting VOUT directly to VSET
yields the nominal logarithmic slope of approximately -25
mV/dB. The output swing corresponding to the specified
input range will then be approximately 0.5 V to 2.1 V. The
slope and output swing can be increased by placing a
resistor divider between VOUT and VSET (i.e., one resistor
from VOUT to VSET and one resistor from VSET to
common). For example, if two equal resistors are used (e.g.,
10 k/10 k), the slope will double to approximately
-50 mV/dB. The input impedance of VSET is approximately
500 k. Slope setting resistors should be kept below ~50 k
to prevent this input impedance from affecting the resulting
slope.
Figure 16: Increasing the Slope
CONTROLLER MODE
The AD8319 provides a controller mode feature at the
VOUT pin. Using V
SET
for the setpoint voltage, it is possible
for the AD8319 to control subsystems, such as power
amplifiers (PAs), variable gain amplifiers (VGAs), or
variable attenuators (VVAs) that have output power that
increases monotonically with respect to their gain control
signal.
To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input; VOUT is connected to the gain control terminal of
the variable gain amplifier (VGA) and the detector's RF
input is connected to the output of the VGA (usually using a
directional coupler and some additional attenuation). Based
on the defined relationship between V
OUT
and the RF input
signal when the device is in measurement mode, the
AD8319 will adjust the voltage on VOUT (VOUT is now an
error amplifier output) until the level at the RF input
corresponds to the applied V
SET
. When the AD8319 operates
in controller mode, there is no defined relationship between
V
SET
and V
OUT
voltage; V
OUT
will settle to a value that results
in the correct input signal level appearing at INHI/INLO.
In order for this output power control loop to be stable, a
ground-referenced capacitor must be connected to the C
FLT
pin.
Preliminary Technical Data
AD8319
Rev. PrC | Page 13 of 14
This capacitor integrates the error signal (which is actually a
current) that is present when the loop is not balanced.
Figure 17: AD8318 Controller Mode
.
Preliminary Technical Data
AD8319
Rev. PrC | Page 14 of 14
OUTLINE DIMENSIONS
Figure 35. 8-Lead Lead Frame Chip Scale Package
ORDERING GUIDE
AD8319 Products
Temperature Package
Package Description
Package Outline
Branding
AD8319ACPZ
1
-REEL7
40C to +85C
8-Lead LFCSP
CP-8
AD8319ACPZ
1
-WP
40C to +85C
8-Lead LFCSP
CP-8
1
Z = Pb-free part.
PR05705-0-8/05(PrC)
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